From 8648747380c640e0272c18d13b9ed98b5d4c895b Mon Sep 17 00:00:00 2001 From: otroubi Date: Wed, 22 Jul 2026 22:06:44 +0300 Subject: [PATCH] debugging a module and its wrappers --- .../src/wrapper_controller_dma.sv | 12 ++++++------ .../tests/tb_controller_dma_wrapper_axil.sv | 12 +++++++----- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/designs/controller_dma_connective/src/wrapper_controller_dma.sv b/designs/controller_dma_connective/src/wrapper_controller_dma.sv index d5fa7a4..9c1606c 100644 --- a/designs/controller_dma_connective/src/wrapper_controller_dma.sv +++ b/designs/controller_dma_connective/src/wrapper_controller_dma.sv @@ -53,10 +53,10 @@ module wrapper_controller_dma output logic dac_rst, output logic adc_rst, - axis_if.slave s_axis_read_data, - axis_if.master m_axis_write_data, + axis_if.master m_axis_read_data, + axis_if.slave s_axis_write_data, - axi4_if.slave s_axi + axi4_if.master m_axi ); axis_if #( @@ -160,10 +160,10 @@ axi_dma_wrapper_inst .rst(!rst_n), .s_axis_read_desc(m_axis_desc_read), .m_axis_read_desc_status(s_axis_status_read), - .m_axis_read_data(s_axis_read_data), + .m_axis_read_data(m_axis_read_data), .s_axis_write_desc(m_axis_desc_write), .m_axis_write_desc_status(s_axis_status_write), - .s_axis_write_data(m_axis_write_data), - .m_axi(s_axi) + .s_axis_write_data(s_axis_write_data), + .m_axi(m_axi) ); endmodule \ No newline at end of file diff --git a/designs/controller_dma_connective/tests/tb_controller_dma_wrapper_axil.sv b/designs/controller_dma_connective/tests/tb_controller_dma_wrapper_axil.sv index 1c257e1..176b40b 100644 --- a/designs/controller_dma_connective/tests/tb_controller_dma_wrapper_axil.sv +++ b/designs/controller_dma_connective/tests/tb_controller_dma_wrapper_axil.sv @@ -106,6 +106,8 @@ module tb_controller_wrapper_axil #( input wire m_axi_rlast, input wire m_axi_rvalid, output wire m_axi_rready + + ); logic rst_n; @@ -243,7 +245,7 @@ axi4_if #( .DATA_W(AXI_DATA_WIDTH), .ID_W (AXI_ID_WIDTH), .USER_W(AXI_USER_WIDTH) -) s_axi ( +) m_axi ( .aclk(ctrl_clk), .aresetn(rst_n) ); @@ -258,7 +260,7 @@ axi4_if_to_flat #( .ID_W (AXI_ID_WIDTH), .USER_W (AXI_USER_WIDTH) ) u_axi_if_to_flat ( - .s_axi(s_axi), + .s_axi(m_axi), .m_axi_awid (m_axi_awid), .m_axi_awaddr (m_axi_awaddr), @@ -362,10 +364,10 @@ axi4_if_to_flat #( .dac_rst(dac_rst), .adc_rst(adc_rst), - .s_axis_read_data(dma_read_data), - .m_axis_write_data(dma_write_data), + .m_axis_read_data(dma_read_data), + .s_axis_write_data(dma_write_data), - .s_axi(s_axi) + .m_axi(m_axi) ); endmodule : tb_controller_wrapper_axil