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debugging a module and its wrappers

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otroubi
2026-07-22 22:06:44 +03:00
parent e06ef3a16b
commit 8648747380
2 changed files with 13 additions and 11 deletions
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12
designs/controller_dma_connective/tests/tb_controller_dma_wrapper_axil.sv
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@ -106,6 +106,8 @@ module tb_controller_wrapper_axil #(
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
logic rst_n;
@ -243,7 +245,7 @@ axi4_if #(
.DATA_W(AXI_DATA_WIDTH),
.ID_W (AXI_ID_WIDTH),
.USER_W(AXI_USER_WIDTH)
) s_axi (
) m_axi (
.aclk(ctrl_clk),
.aresetn(rst_n)
);
@ -258,7 +260,7 @@ axi4_if_to_flat #(
.ID_W (AXI_ID_WIDTH),
.USER_W (AXI_USER_WIDTH)
) u_axi_if_to_flat (
.s_axi(s_axi),
.s_axi(m_axi),
.m_axi_awid (m_axi_awid),
.m_axi_awaddr (m_axi_awaddr),
@ -362,10 +364,10 @@ axi4_if_to_flat #(
.dac_rst(dac_rst),
.adc_rst(adc_rst),
.s_axis_read_data(dma_read_data),
.m_axis_write_data(dma_write_data),
.m_axis_read_data(dma_read_data),
.s_axis_write_data(dma_write_data),
.s_axi(s_axi)
.m_axi(m_axi)
);
endmodule : tb_controller_wrapper_axil