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debugging during the test

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otroubi
2026-08-25 15:01:01 +03:00
parent 9c66f1b530
commit 820f3400ea
4 changed files with 109 additions and 11 deletions
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rtl/accum/src/accum_top.sv
+1 -1
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@@ -107,7 +107,7 @@ module accumulator_top
.m_axis_tdata (m_axis_accum.req.t.data),
.m_axis_tvalid (m_axis_accum.req.t.valid),
.m_axis_tready (m_axis_accum.resp.ready),
.m_axis_tready (accum_done),
.m_axis_tlast (m_axis_accum.req.t.last),
.acc_din (out_data),
rtl/accum/src/out_axis_fifo.sv
+4 -2
View File
@@ -238,9 +238,11 @@ module out_axis_fifo #(
RD_SEND: begin
// udp is ready and fifo is ready = sent
send_req <= 1'b0;
m_axis_tvalid <= rd_valid;
rd_en <= m_axis_tvalid && m_axis_tready;
if (m_axis_tready && rd_valid) begin
rd_en <= 1'b1;
m_axis_tvalid <= 1'b1;
//rd_en <= 1'b1;
//m_axis_tvalid <= 1'b1;
sent_cnt <= sent_cnt + 1;
// final packet of the batch
if (sent_cnt == PACKET_RD_WORDS-1) begin