From 820f3400ea574df05fa66c78af35e58c4b11ca12 Mon Sep 17 00:00:00 2001 From: otroubi Date: Tue, 25 Aug 2026 15:01:01 +0300 Subject: [PATCH] debugging during the test --- .../src/axi_dma_wrapper_if.sv | 22 +++-- rtl/accum/src/accum_top.sv | 2 +- rtl/accum/src/out_axis_fifo.sv | 6 +- rtl/controller_new/src/shaper_axis_status.sv | 90 ++++++++++++++++++- 4 files changed, 109 insertions(+), 11 deletions(-) diff --git a/designs/full_new_reflectometer/src/axi_dma_wrapper_if.sv b/designs/full_new_reflectometer/src/axi_dma_wrapper_if.sv index 4e2db3b..42cab3b 100644 --- a/designs/full_new_reflectometer/src/axi_dma_wrapper_if.sv +++ b/designs/full_new_reflectometer/src/axi_dma_wrapper_if.sv @@ -5,9 +5,9 @@ // AXI memory, AXI-Stream data, DMA descriptor, and DMA status channels are all // exposed through compact interfaces. The original Forencich core remains // untouched and is connected through local flat wires. -`timescale 1 ns / 1 ns -`default_nettype none + import dma_reg_pkg::*; +import axi_pkg::*; // DMA Specific wrappers & converters module axi_dma_wrapper #( @@ -67,6 +67,16 @@ module axi_dma_wrapper #( logic m_axis_write_desc_status_valid; assign m_axis_write_desc_status.req.t.valid = m_axis_write_desc_status_valid; +logic [1:0] dma_awburst; +logic [1:0] dma_arburst; +logic [1:0] dma_bresp; +logic [1:0] dma_rresp; + +assign m_axi.req.aw.burst = axi_pkg::axi_burst_t'(dma_awburst); +assign m_axi.req.ar.burst = axi_pkg::axi_burst_t'(dma_arburst); + +assign dma_bresp = logic'(m_axi.resp.b.resp); +assign dma_rresp = logic'(m_axi.resp.r.resp); // Original DMA: flat ports only. axi_dma #( @@ -142,7 +152,7 @@ module axi_dma_wrapper #( .m_axi_awaddr (m_axi.req.aw.addr), .m_axi_awlen (m_axi.req.aw.len), .m_axi_awsize (m_axi.req.aw.size), - .m_axi_awburst (m_axi.req.aw.burst), + .m_axi_awburst (dma_awburst), .m_axi_awlock (m_axi.req.aw.lock), .m_axi_awcache (m_axi.req.aw.cache), .m_axi_awprot (m_axi.req.aw.prot), @@ -156,7 +166,7 @@ module axi_dma_wrapper #( .m_axi_wready (m_axi.resp.w_ready), .m_axi_bid (m_axi.resp.b.id), - .m_axi_bresp (m_axi.resp.b.resp), + .m_axi_bresp (dma_bresp), .m_axi_bvalid (m_axi.resp.b.valid), .m_axi_bready (m_axi.req.b_ready), @@ -164,7 +174,7 @@ module axi_dma_wrapper #( .m_axi_araddr (m_axi.req.ar.addr), .m_axi_arlen (m_axi.req.ar.len), .m_axi_arsize (m_axi.req.ar.size), - .m_axi_arburst (m_axi.req.ar.burst), + .m_axi_arburst (dma_arburst), .m_axi_arlock (m_axi.req.ar.lock), .m_axi_arcache (m_axi.req.ar.cache), .m_axi_arprot (m_axi.req.ar.prot), @@ -173,7 +183,7 @@ module axi_dma_wrapper #( .m_axi_rid (m_axi.resp.r.id), .m_axi_rdata (m_axi.resp.r.data), - .m_axi_rresp (m_axi.resp.r.resp), + .m_axi_rresp (dma_rresp), .m_axi_rlast (m_axi.resp.r.last), .m_axi_rvalid (m_axi.resp.r.valid), .m_axi_rready (m_axi.req.r_ready), diff --git a/rtl/accum/src/accum_top.sv b/rtl/accum/src/accum_top.sv index 8bf5a6a..272f123 100644 --- a/rtl/accum/src/accum_top.sv +++ b/rtl/accum/src/accum_top.sv @@ -107,7 +107,7 @@ module accumulator_top .m_axis_tdata (m_axis_accum.req.t.data), .m_axis_tvalid (m_axis_accum.req.t.valid), - .m_axis_tready (m_axis_accum.resp.ready), + .m_axis_tready (accum_done), .m_axis_tlast (m_axis_accum.req.t.last), .acc_din (out_data), diff --git a/rtl/accum/src/out_axis_fifo.sv b/rtl/accum/src/out_axis_fifo.sv index ecb6a8a..c28c17d 100644 --- a/rtl/accum/src/out_axis_fifo.sv +++ b/rtl/accum/src/out_axis_fifo.sv @@ -238,9 +238,11 @@ module out_axis_fifo #( RD_SEND: begin // udp is ready and fifo is ready = sent send_req <= 1'b0; + m_axis_tvalid <= rd_valid; + rd_en <= m_axis_tvalid && m_axis_tready; if (m_axis_tready && rd_valid) begin - rd_en <= 1'b1; - m_axis_tvalid <= 1'b1; + //rd_en <= 1'b1; + //m_axis_tvalid <= 1'b1; sent_cnt <= sent_cnt + 1; // final packet of the batch if (sent_cnt == PACKET_RD_WORDS-1) begin diff --git a/rtl/controller_new/src/shaper_axis_status.sv b/rtl/controller_new/src/shaper_axis_status.sv index 5bad170..2c6a31f 100644 --- a/rtl/controller_new/src/shaper_axis_status.sv +++ b/rtl/controller_new/src/shaper_axis_status.sv @@ -1,4 +1,4 @@ -module shaper_axis_status #( +/* module shaper_axis_status #( parameter int unsigned DATA_WIDTH = 128 )( input logic clk, @@ -21,7 +21,7 @@ typedef enum logic [0:0] { wr_state state; -logic [31:0] data_reg; +logic [DATA_WIDTH-1:0] data_reg; always @(posedge clk) begin if (!rst_n) begin @@ -56,4 +56,90 @@ always @(posedge clk) begin end +endmodule +*/ +module shaper_axis_status #( + parameter int unsigned DATA_WIDTH = 128 +)( + input logic clk, + input logic rst_n, + + input logic [DATA_WIDTH-1:0] data_in, + input logic take, + input logic valid, + output logic ready, + + output logic busy, + output logic handshake, + output logic [DATA_WIDTH-1:0] data_out +); + + typedef enum logic [0:0] { + IDLE, + WAIT_TAKE + } wr_state; + + wr_state state; + + logic [DATA_WIDTH-1:0] data_reg; + + // Запоминаем take, если он пришёл раньше valid + logic take_pending; + + // Готовы принять status только в IDLE + assign ready = (state == IDLE); + + always @(posedge clk) begin + if (!rst_n) begin + state <= IDLE; + busy <= 1'b0; + handshake <= 1'b0; + data_out <= '0; + data_reg <= '0; + take_pending <= 1'b0; + end else begin + + // handshake — импульс + handshake <= 1'b0; + + case (state) + + IDLE: begin + busy <= 1'b0; + + // Запоминаем ранний take + if (take) + take_pending <= 1'b1; + + // Пришёл status + if (valid && ready) begin + data_reg <= data_in; + handshake <= 1'b1; + + // take был раньше ИЛИ пришёл одновременно + if (take_pending || take) begin + data_out <= data_in; + busy <= 1'b1; + take_pending <= 1'b0; + state <= IDLE; + end else begin + state <= WAIT_TAKE; + end + end + end + + WAIT_TAKE: begin + busy <= 1'b1; + + // take пришёл после valid + if (take) begin + data_out <= data_reg; + state <= IDLE; + end + end + + endcase + end + end + endmodule \ No newline at end of file