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debugging during the test

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otroubi
2026-08-25 15:01:01 +03:00
parent 9c66f1b530
commit 820f3400ea
4 changed files with 109 additions and 11 deletions
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designs/full_new_reflectometer/src/axi_dma_wrapper_if.sv
+16 -6
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@@ -5,9 +5,9 @@
// AXI memory, AXI-Stream data, DMA descriptor, and DMA status channels are all
// exposed through compact interfaces. The original Forencich core remains
// untouched and is connected through local flat wires.
`timescale 1 ns / 1 ns
`default_nettype none
import dma_reg_pkg::*;
import axi_pkg::*;
// DMA Specific wrappers & converters
module axi_dma_wrapper #(
@@ -67,6 +67,16 @@ module axi_dma_wrapper #(
logic m_axis_write_desc_status_valid;
assign m_axis_write_desc_status.req.t.valid = m_axis_write_desc_status_valid;
logic [1:0] dma_awburst;
logic [1:0] dma_arburst;
logic [1:0] dma_bresp;
logic [1:0] dma_rresp;
assign m_axi.req.aw.burst = axi_pkg::axi_burst_t'(dma_awburst);
assign m_axi.req.ar.burst = axi_pkg::axi_burst_t'(dma_arburst);
assign dma_bresp = logic'(m_axi.resp.b.resp);
assign dma_rresp = logic'(m_axi.resp.r.resp);
// Original DMA: flat ports only.
axi_dma #(
@@ -142,7 +152,7 @@ module axi_dma_wrapper #(
.m_axi_awaddr (m_axi.req.aw.addr),
.m_axi_awlen (m_axi.req.aw.len),
.m_axi_awsize (m_axi.req.aw.size),
.m_axi_awburst (m_axi.req.aw.burst),
.m_axi_awburst (dma_awburst),
.m_axi_awlock (m_axi.req.aw.lock),
.m_axi_awcache (m_axi.req.aw.cache),
.m_axi_awprot (m_axi.req.aw.prot),
@@ -156,7 +166,7 @@ module axi_dma_wrapper #(
.m_axi_wready (m_axi.resp.w_ready),
.m_axi_bid (m_axi.resp.b.id),
.m_axi_bresp (m_axi.resp.b.resp),
.m_axi_bresp (dma_bresp),
.m_axi_bvalid (m_axi.resp.b.valid),
.m_axi_bready (m_axi.req.b_ready),
@@ -164,7 +174,7 @@ module axi_dma_wrapper #(
.m_axi_araddr (m_axi.req.ar.addr),
.m_axi_arlen (m_axi.req.ar.len),
.m_axi_arsize (m_axi.req.ar.size),
.m_axi_arburst (m_axi.req.ar.burst),
.m_axi_arburst (dma_arburst),
.m_axi_arlock (m_axi.req.ar.lock),
.m_axi_arcache (m_axi.req.ar.cache),
.m_axi_arprot (m_axi.req.ar.prot),
@@ -173,7 +183,7 @@ module axi_dma_wrapper #(
.m_axi_rid (m_axi.resp.r.id),
.m_axi_rdata (m_axi.resp.r.data),
.m_axi_rresp (m_axi.resp.r.resp),
.m_axi_rresp (dma_rresp),
.m_axi_rlast (m_axi.resp.r.last),
.m_axi_rvalid (m_axi.resp.r.valid),
.m_axi_rready (m_axi.req.r_ready),