upd: new TB, sampler refactor

rtl/sampler/src/sampler.sv

@@ -13,18 +13,18 @@ module sampler
     input [31:0] smp_num,
     input request,
 
-    output logic [DATA_WIDTH*PACK_FACTOR-1:0]  m_axis_tdata,   
-    output logic                              m_axis_tvalid,  
+    output logic [DATA_WIDTH*PACK_FACTOR-1:0]  m_axis_tdata, 
+    output logic                              m_axis_tvalid,
     output logic done
 );
-
+    // WARNING: number of samples smp_num must be multiple of PACK_FACTOR
+    // Last (smp_num % PACK_FACTOR) will be lost and not transmitted
     logic [DATA_WIDTH-1:0] data_converted;
     logic [31:0] smp_num_reg, cnt_smp_num;
-    logic synced;   
+    logic synced;
     logic  [$clog2(PACK_FACTOR):0] pack_cnt;
     
     always_comb begin
-            data_converted = '0;
             if (PROCESS_MODE) begin
                 if (out_of_range) begin
                     data_converted = {~data_in[DATA_WIDTH-1], {(DATA_WIDTH-1){data_in[DATA_WIDTH-1]}}};
@@ -39,7 +39,12 @@ module sampler
                 end
             end
     end
-  
+
+    initial begin
+        synced = 0;
+        m_axis_tdata = '0;
+        m_axis_tvalid = 0;
+    end
     
     always_ff @(posedge clk_in) begin
         if (rst) begin
@@ -51,10 +56,9 @@ module sampler
             synced <= 0;
             done <= 0;
         end else begin
-            m_axis_tvalid <= 0;
             if (!synced) begin
                 if (done && request) begin
-                    synced  <= 1;
+                    synced <= 1;
                     done <= 0;
                     cnt_smp_num <= 0;
                     smp_num_reg <= smp_num;
@@ -63,23 +67,21 @@ module sampler
                 end
             end else begin
                 if (cnt_smp_num != smp_num_reg) begin
-                    cnt_smp_num <= cnt_smp_num +1;
+                    cnt_smp_num++;
                     m_axis_tdata[pack_cnt*DATA_WIDTH +: DATA_WIDTH] <= data_converted;
                     if (pack_cnt == PACK_FACTOR-1) begin
                         pack_cnt <= 0;
                         m_axis_tvalid <= 1;
                     end else begin
-                        pack_cnt <= pack_cnt + 1;
+                        pack_cnt++;
+                        m_axis_tvalid <= 0;
                     end
                 end else begin
-                    cnt_smp_num <= '0;
-                    pack_cnt    <= '0;
+                    pack_cnt <= '0;
                     synced <= 0;
-                    done <= 1;
-                    m_axis_tdata <= '0;
+                    m_axis_tvalid <= 0;
                 end
             end
         end
-    end
-    
+    end    
 endmodule