88 lines
2.6 KiB
Systemverilog
88 lines
2.6 KiB
Systemverilog
`timescale 1ns / 1ps
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module sampler
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#(
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parameter DATA_WIDTH = 12,
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parameter PACK_FACTOR = 1,
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parameter PROCESS_MODE = 0
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) (
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input clk_in,
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input rst,
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input [DATA_WIDTH-1:0] data_in,
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input out_of_range,
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input [31:0] smp_num,
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input request,
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output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
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output logic m_axis_tvalid,
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output logic done
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);
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// WARNING: number of samples smp_num must be multiple of PACK_FACTOR
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// Last (smp_num % PACK_FACTOR) will be lost and not transmitted
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logic [DATA_WIDTH-1:0] data_converted;
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logic [31:0] smp_num_reg, cnt_smp_num;
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logic synced;
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logic [$clog2(PACK_FACTOR):0] pack_cnt;
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always_comb begin
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if (PROCESS_MODE) begin
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if (out_of_range) begin
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data_converted = {~data_in[DATA_WIDTH-1], {(DATA_WIDTH-1){data_in[DATA_WIDTH-1]}}};
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end else begin
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data_converted = {~data_in[DATA_WIDTH-1], data_in[DATA_WIDTH-2:0]};
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end
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end else begin
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if (out_of_range) begin
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data_converted = {DATA_WIDTH{data_in[DATA_WIDTH-1]}};
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end else begin
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data_converted = data_in;
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end
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end
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end
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initial begin
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synced = 0;
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m_axis_tdata = '0;
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m_axis_tvalid = 0;
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end
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always_ff @(posedge clk_in) begin
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if (rst) begin
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m_axis_tdata <= '0;
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m_axis_tvalid <= 0;
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cnt_smp_num <= '0;
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smp_num_reg <= '0;
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pack_cnt <= '0;
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synced <= 0;
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done <= 0;
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end else begin
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if (!synced) begin
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if (done && request) begin
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synced <= 1;
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done <= 0;
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cnt_smp_num <= 0;
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smp_num_reg <= smp_num;
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end else begin
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done <= 1;
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end
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end else begin
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if (cnt_smp_num != smp_num_reg) begin
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cnt_smp_num++;
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m_axis_tdata[pack_cnt*DATA_WIDTH +: DATA_WIDTH] <= data_converted;
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if (pack_cnt == PACK_FACTOR-1) begin
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pack_cnt <= 0;
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m_axis_tvalid <= 1;
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end else begin
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pack_cnt++;
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m_axis_tvalid <= 0;
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end
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end else begin
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pack_cnt <= '0;
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synced <= 0;
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m_axis_tvalid <= 0;
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end
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end
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end
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end
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endmodule
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