baulin.fa/reflectometer_fpga_project
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

rtl: sampler synchronizer update

Browse Source
This commit is contained in:
otroubi
2026-05-06 14:30:23 +03:00
parent f719533eb9
commit 7c3fe36df1
1 changed files with 70 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

63
rtl/sampler/src/sampler.sv
View File

@ -13,12 +13,17 @@ module sampler
input rst, input rst,
input [DATA_WIDTH-1:0] data_in, input [DATA_WIDTH-1:0] data_in,
input out_of_range, input out_of_range,
input [31:0] smp_num,
input sample_req,
output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata, output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
output logic m_axis_tvalid output logic m_axis_tvalid,
output logic sample_done
); );
logic [DATA_WIDTH-1:0] data_converted; (* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
logic out_of_range_reg; (* MARK_DEBUG="true" *) logic out_of_range_reg;
(* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
(* MARK_DEBUG="true" *) logic enable;
generate generate
if (PROCESS_MODE) begin if (PROCESS_MODE) begin
@ -50,8 +55,8 @@ module sampler
end end
endgenerate endgenerate
logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer; (* MARK_DEBUG="true" *) logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
logic buffer_ready; (* MARK_DEBUG="true" *) logic buffer_ready;
logic [$clog2(PACK_FACTOR):0] cnt; logic [$clog2(PACK_FACTOR):0] cnt;
@ -61,12 +66,36 @@ module sampler
if (rst) begin if (rst) begin
buffer <= '0; buffer <= '0;
buffer_ready <= 0; buffer_ready <= 0;
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= '0;
sample_done <= 0;
end end
else begin else begin
buffer_ready <= 0; buffer_ready <= 0;
if (sample_done && !sample_req) begin
sample_done <= 1'b0;
end
if (!enable && sample_req && !sample_done) begin
enable <= 1;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end
if (enable) begin
if (!out_of_range_reg) begin if (!out_of_range_reg) begin
if (cnt_smp_num != smp_num_reg-1) begin
buffer <= data_converted; buffer <= data_converted;
buffer_ready <= 1; buffer_ready <= 1;
cnt_smp_num <= cnt_smp_num +1;
end
else begin
cnt_smp_num <= '0;
sample_done <= 1'b1;
buffer_ready <= 0;
buffer <= '0;
enable <= 0;
end
end
end end
end end
end end
@ -76,10 +105,25 @@ module sampler
buffer <= '0; buffer <= '0;
cnt <= '0; // cnt <= '0; //
buffer_ready <= 0; buffer_ready <= 0;
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
sample_done <= 0;
end end
else begin else begin
buffer_ready <= 0; buffer_ready <= 0;
if (sample_done && !sample_req) begin
sample_done <= 1'b0;
end
if (!enable && sample_req && !sample_done) begin
enable <= 1;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end
if (enable) begin
if (!out_of_range_reg) begin if (!out_of_range_reg) begin
if (cnt_smp_num != smp_num_reg-1) begin
cnt_smp_num <= cnt_smp_num +1;
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted}; buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
if (cnt == PACK_FACTOR-1) begin if (cnt == PACK_FACTOR-1) begin
cnt <= 0; cnt <= 0;
@ -90,6 +134,15 @@ module sampler
cnt <= cnt + 1; cnt <= cnt + 1;
end end
end end
else begin
sample_done <= 1'b1;
cnt_smp_num <= '0;
buffer_ready <= 0;
buffer <= '0;
enable <= 0;
end
end
end
end end
end end
end end