From 7c3fe36df1c34ee0772a1c7e5fc7baea56bf015a Mon Sep 17 00:00:00 2001
From: otroubi <ilianovadasha@gmail.com>
Date: Wed, 6 May 2026 14:30:23 +0300
Subject: [PATCH] rtl: sampler synchronizer update

---
 rtl/sampler/src/sampler.sv | 87 ++++++++++++++++++++++++++++++--------
 1 file changed, 70 insertions(+), 17 deletions(-)

diff --git a/rtl/sampler/src/sampler.sv b/rtl/sampler/src/sampler.sv
index 23f0446..a6bd290 100644
--- a/rtl/sampler/src/sampler.sv
+++ b/rtl/sampler/src/sampler.sv
@@ -13,12 +13,17 @@ module sampler
     input rst,
     input [DATA_WIDTH-1:0] data_in,
     input out_of_range,
+    input [31:0] smp_num,
+    input sample_req,
 
     output logic [DATA_WIDTH*PACK_FACTOR-1:0]  m_axis_tdata,
-    output logic                              m_axis_tvalid
+    output logic                              m_axis_tvalid,
+    output logic sample_done
     );
-    logic [DATA_WIDTH-1:0] data_converted;
-    logic out_of_range_reg;
+   (* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
+   (* MARK_DEBUG="true" *) logic out_of_range_reg;
+    (* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
+   (* MARK_DEBUG="true" *) logic enable;
     
     generate
        if (PROCESS_MODE) begin 
@@ -50,8 +55,8 @@ module sampler
      end
     endgenerate
          
-    logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
-    logic buffer_ready;
+  (* MARK_DEBUG="true" *)  logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
+  (* MARK_DEBUG="true" *)  logic buffer_ready;
 
     logic [$clog2(PACK_FACTOR):0] cnt;
     
@@ -61,12 +66,36 @@ module sampler
             if (rst) begin
                 buffer       <= '0;
                 buffer_ready <= 0;
+                cnt_smp_num <= '0;
+                smp_num_reg <= '0;
+                enable <= '0;
+                sample_done <= 0;
             end
             else begin
                 buffer_ready <= 0;
-                if (!out_of_range_reg) begin
-                    buffer       <= data_converted;
-                    buffer_ready <= 1;
+                if (sample_done && !sample_req) begin
+                    sample_done <= 1'b0;
+                end
+                if (!enable && sample_req && !sample_done) begin
+                    enable      <= 1;
+                    cnt_smp_num <= 0;
+                    smp_num_reg <= smp_num;
+                end
+                if (enable) begin
+                    if (!out_of_range_reg) begin
+                        if (cnt_smp_num != smp_num_reg-1) begin
+                            buffer       <= data_converted;
+                            buffer_ready <= 1;
+                            cnt_smp_num <= cnt_smp_num +1;
+                        end 
+                        else begin
+                            cnt_smp_num <= '0;
+                            sample_done <= 1'b1;
+                            buffer_ready <= 0;
+                            buffer <= '0;
+                            enable <= 0;
+                        end
+                    end
                 end
             end
         end
@@ -76,18 +105,42 @@ module sampler
                 buffer <= '0;
                 cnt <= '0; //
                 buffer_ready <= 0;
+                cnt_smp_num <= '0;
+                smp_num_reg <= '0;
+                enable <= 0;
+                sample_done <= 0;
             end
             else begin
                 buffer_ready <= 0;
-                if (!out_of_range_reg) begin
-                    buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
-                    if (cnt == PACK_FACTOR-1) begin
-                        cnt <= 0;
-                        buffer_ready <= 1;
-                        buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
-                    end
-                    else begin
-                        cnt <= cnt + 1;
+                if (sample_done && !sample_req) begin
+                    sample_done <= 1'b0;
+                end
+                if (!enable && sample_req && !sample_done) begin
+                    enable      <= 1;
+                    cnt_smp_num <= 0;
+                    smp_num_reg <= smp_num;
+                end
+                if (enable) begin
+                    if (!out_of_range_reg) begin
+                        if (cnt_smp_num != smp_num_reg-1) begin
+                            cnt_smp_num <= cnt_smp_num +1;
+                            buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
+                            if (cnt == PACK_FACTOR-1) begin
+                                cnt <= 0;
+                                buffer_ready <= 1;
+                                buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
+                            end
+                            else begin
+                                cnt <= cnt + 1;
+                            end
+                        end 
+                        else begin
+                            sample_done <= 1'b1;
+                            cnt_smp_num <= '0;
+                            buffer_ready <= 0;
+                            buffer <= '0;
+                            enable <= 0;
+                        end
                     end
                 end
             end