add: half-baked reflectometer TB

fix: constraints port names; ready: reflectometer top module
2026-07-08 14:56:51 +03:00
parent c3275d5b46
commit 7665afd50b
5 changed files with 285 additions and 378 deletions
--- a/designs/adc_dac_synchoronizer/debug.xdc
+++ b/designs/adc_dac_synchoronizer/debug.xdc
@ -1,3 +1,3 @@
 # Primary clocks
-create_clock -name eth_clk -period 8.000  [get_ports dac_clk_in]
-create_clock -name acc_clk -period 15.385  [get_ports adc_clk_in]
+create_clock -name eth_clk -period 8.000  [get_ports clk_dac]
+create_clock -name acc_clk -period 15.385  [get_ports clk_adc]