add: half-baked reflectometer TB

fix: constraints port names;
ready: reflectometer top module

designs/adc_dac_synchoronizer/debug.xdc

@@ -1,3 +1,3 @@
 # Primary clocks
-create_clock -name eth_clk -period 8.000  [get_ports dac_clk_in]
-create_clock -name acc_clk -period 15.385  [get_ports adc_clk_in]
+create_clock -name eth_clk -period 8.000  [get_ports clk_dac]
+create_clock -name acc_clk -period 15.385  [get_ports clk_adc]

designs/adc_dac_synchoronizer/tb_sync_top.sv

@@ -305,4 +305,4 @@ module tb_top;
         $finish;
     end
 
-endmodule
+endmodule