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add: new reflectometer top design (not ready)

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babintsev.lv
2026-07-03 16:32:48 +03:00
parent d878bac42a
commit 725826b07c
1 changed files with 89 additions and 144 deletions
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201
designs/reflectometer_base/reflectometer.sv
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@ -1,8 +1,8 @@
`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns
module reflectometer_top #( module reflectometer_top #(
parameter DAC_DATA_WIDTH = 14, parameter int unsigned DAC_DATA_WIDTH = 14,
parameter ADC_DATA_WIDTH = 12, parameter int unsigned ADC_DATA_WIDTH = 12,
parameter PACK_FACTOR = 1, parameter PACK_FACTOR = 1,
parameter PROCESS_MODE = 0, parameter PROCESS_MODE = 0,
parameter ZERO_LEVEL = 8192, parameter ZERO_LEVEL = 8192,
@ -11,79 +11,84 @@ module reflectometer_top #(
parameter WINDOW_SIZE = 65, parameter WINDOW_SIZE = 65,
parameter PACKET_SIZE = 1024 parameter PACKET_SIZE = 1024
)( )(
input clk_sys, input clk_in,
input rst_n, input rst_n,
output [3:0] status_led,
// Output AXI-Stream for Accumulator // Accumulator AXI-S bus
input clk_m_axis, input wire clk_m_axis, // GMII PHY RX clock
output wire [7:0] m_axis_tx_tdata, output logic [7:0] m_axis_tdata,
output wire m_axis_tx_tvalid, output logic m_axis_tvalid,
input wire m_axis_tx_tready, input wire m_axis_tready,
output wire m_axis_tx_tlast, output logic m_axis_tlast,
// Input AXI-Stream for Controller // Control AXI-S bus
input clk_s_axis, input wire clk_s_axis, // GMII PHY TX clock
input wire [7:0] s_axis_rx_tdata, input wire [7:0] s_axis__tdata,
input wire s_axis_rx_tvalid, input wire s_axis_tvalid,
input wire s_axis_rx_tlast, input wire s_axis_tlast,
output wire s_axis_rx_tready, output logic s_axis_tready,
// Reflectometer status // RTL-MAC handshake
output wire [3:0] status_leds, // System current status indicators input wire request_ready,
input wire req_ready, // MAC handshake ready output logic send_request,
output wire send_req, // MAC handshake send
// Generator (DAC) // DAC
output wire dac_clock, output logic clk_dac,
output wire [DAC_DATA_WIDTH-1:0] dac_out, output logic [DAC_DATA_WIDTH-1:0] dac_data,
output wire dac_wrt, output logic dac_wrt,
// Sampler (ADC) // ADC
output wire adc_clock, output logic clk_adc,
input wire [ADC_DATA_WIDTH-1:0] adc_data, input wire [ADC_DATA_WIDTH-1:0] adc_data,
input wire adc_otr input wire adc_otr
); );
// // -------------------------------------------------------------------------
// // IDELAYCTRL
// // -------------------------------------------------------------------------
// (* IODELAY_GROUP = "rgmii_idelay_group" *)
// IDELAYCTRL IDELAYCTRL_inst (
// .RDY (),
// .REFCLK (sys_clk),
// .RST (1'b0)
// ); TODO remove
// ------------------------------------------------------------------------- // -------------------------------------------------------------------------
// Generated clocks for controller // Generated clocks for controller
// Need to create this IP in Vivado: // Need to create this IP in Vivado:
// input : 200 MHz // input resetn
// ADC: // input clk_200 : 200 MHz : Reference clock
// output0: 65 Mhz 0* phase for logic // output clk_adc_65 : 65 MHz : ADC RTL clock
// output1: 65 MHz 180* phase for output clocking // output clk_adc_65_180 : 65 MHz, phase 180 deg. : ADC PHY clock
// DAC: // output clk_adc_125 : 125 MHz : DAC RTL clock
// output2: 125 Mhz 0* phase for logic // output clk_adc_125_180 : 125 MHz, phase 180 deg. : DAC PHY clock
// output3: 125 MHz 180* phase for output clocking // output locked
// ------------------------------------------------------------------------- // -------------------------------------------------------------------------
wire clk_adc, clk_adc_180; wire clk_sampler, clk_adc;
wire clk_dac, clk_dac_180; wire clk_generator, clk_dac;
wire locked; wire clk_locked;
clk_wiz_ctrl_inst clk_wiz_inst clk_wiz_ctrl_inst_clk_wiz inst
( (
// Clock in ports
.clk_200(clk_in)
// Clock out ports // Clock out ports
.clk_adc_65(clk_adc), .clk_adc_65(clk_adc),
.clk_adc_65_180(clk_adc_180), .clk_adc_65_180(clk_sampler),
.clk_dac_125(clk_dac), .clk_dac_125(clk_dac),
.clk_dac_125_180(clk_dac_180), .clk_dac_125_180(clk_generator),
// Status and control signals // Status and control signals
.resetn(rst_n), .resetn(rst_n),
.locked(locked), .locked(clk_locked),
// Clock in ports
.clk_sys(clk_sys)
); );
// -------------------------------------------------------------------------
// axis_mac interface
// RX stream from Ethernet goes into controller
// TX stream is unused for now
// -------------------------------------------------------------------------
// ------------------------------------------------------------------------- // -------------------------------------------------------------------------
// Controller reset // Controller reset
// Use both external reset and clk_wiz lock // Use both external reset and clk_wiz lock
// ------------------------------------------------------------------------- // -------------------------------------------------------------------------
wire rst_n_ctrl = rst_n & locked; wire ctrl_rst_n = rst_n & clk_wiz_locked;
logic finish; logic finish;
@ -103,8 +108,7 @@ module reflectometer_top #(
// ------------------------------------------------------------------------- // -------------------------------------------------------------------------
// Controller // Controller TODO
// ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side
// ------------------------------------------------------------------------- // -------------------------------------------------------------------------
control #( control #(
.DAC_DATA_WIDTH(DAC_DATA_WIDTH) .DAC_DATA_WIDTH(DAC_DATA_WIDTH)
@ -136,10 +140,9 @@ module reflectometer_top #(
.adc_rst (adc_rst) .adc_rst (adc_rst)
); );
// ------------------------------------------------------------------------- //------------------------------------------------------------
// DAC // DAC -> ADC CDC TODO
// ------------------------------------------------------------------------- //------------------------------------------------------------
logic sample_req; logic sample_req;
logic sample_req_sync1; logic sample_req_sync1;
logic sample_req_sync2; logic sample_req_sync2;
@ -149,10 +152,6 @@ module reflectometer_top #(
logic sample_done_sync1; logic sample_done_sync1;
logic sample_done_sync2; logic sample_done_sync2;
logic sample_done_sync3; logic sample_done_sync3;
//------------------------------------------------------------
// DAC -> ADC CDC
//------------------------------------------------------------
always_ff @(posedge adc_clk or posedge adc_rst) begin always_ff @(posedge adc_clk or posedge adc_rst) begin
if (adc_rst) begin if (adc_rst) begin
sample_req <= 1'b0; sample_req <= 1'b0;
@ -167,7 +166,7 @@ module reflectometer_top #(
end end
//------------------------------------------------------------ //------------------------------------------------------------
// ADC -> DAC CDC // ADC -> DAC CDC TODO
//------------------------------------------------------------ //------------------------------------------------------------
always_ff @(posedge dac_clk or posedge dac_rst) begin always_ff @(posedge dac_clk or posedge dac_rst) begin
if (dac_rst) begin if (dac_rst) begin
@ -183,9 +182,8 @@ module reflectometer_top #(
end end
//------------------------------------------------------------ //------------------------------------------------------------
// Generator // Generator (DAC) TODO
//------------------------------------------------------------ //------------------------------------------------------------
generator #( generator #(
.DATA_WIDTH(DAC_DATA_WIDTH), .DATA_WIDTH(DAC_DATA_WIDTH),
.ZERO_LEVEL(ZERO_LEVEL) .ZERO_LEVEL(ZERO_LEVEL)
@ -203,64 +201,15 @@ module reflectometer_top #(
.sample_req(sample_req_sync1) .sample_req(sample_req_sync1)
); );
wire ch2_clk_oddr;
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_ch2_clk (
.Q (ch2_clk_oddr),
.C (adc_clk),
.CE(1'b1),
.D1(1'b1),
.D2(1'b0),
.R (1'b0),
.S (1'b0)
);
OBUF OBUF_ch2_clk (
.I(ch2_clk_oddr),
.O(ch2_clk)
);
wire p2_clk_oddr;
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_p2_clk (
.Q (p2_clk_oddr),
.C (dac_clk),
.CE(1'b1),
.D1(1'b1),
.D2(1'b0),
.R (1'b0),
.S (1'b0)
);
OBUF OBUF_p2_clk (
.I(p2_clk_oddr),
.O(p2_clk)
);
// ------------------------------------------------------------------------- // -------------------------------------------------------------------------
// ADC // Sampler (ADC) TODO
// ------------------------------------------------------------------------- // -------------------------------------------------------------------------
sampler #(
logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] accum_m_axis_tdata;
logic acum_m_axis_tvalid;
sampler
#(
.DATA_WIDTH(ADC_DATA_WIDTH), .DATA_WIDTH(ADC_DATA_WIDTH),
.PACK_FACTOR(PACK_FACTOR), .PACK_FACTOR(PACK_FACTOR),
.PROCESS_MODE(PROCESS_MODE) .PROCESS_MODE(PROCESS_MODE)
) ) sampler_dut (
sampler_dut .clk_in(clk_sampler),
(
.clk_in(adc_clk),
.rst(adc_rst), .rst(adc_rst),
.data_in(ch2_data), .data_in(ch2_data),
.out_of_range(ch2_otr), .out_of_range(ch2_otr),
@ -272,20 +221,16 @@ module reflectometer_top #(
); );
// ------------------------------------------------------------------------- // -------------------------------------------------------------------------
// Accumulator // Accumulator TODO
// ------------------------------------------------------------------------- // -------------------------------------------------------------------------
accumulator_top #(
accumulator_top
#(
.DATA_WIDTH(ADC_DATA_WIDTH), .DATA_WIDTH(ADC_DATA_WIDTH),
.ACCUM_WIDTH(ACCUM_WIDTH), .ACCUM_WIDTH(ACCUM_WIDTH),
.N_MAX(N_MAX), .N_MAX(N_MAX),
.WINDOW_SIZE(WINDOW_SIZE), .WINDOW_SIZE(WINDOW_SIZE),
.PACKET_SIZE(PACKET_SIZE) .PACKET_SIZE(PACKET_SIZE)
) ) accumulator_top_dut (
accumulator_top_dut .clk_in(clk_sampler),
(
.clk_in(adc_clk),
.rst(adc_rst), .rst(adc_rst),
.s_axis_tdata(accum_m_axis_tdata), .s_axis_tdata(accum_m_axis_tdata),
.s_axis_tvalid(acum_m_axis_tvalid), .s_axis_tvalid(acum_m_axis_tvalid),
@ -304,12 +249,12 @@ module reflectometer_top #(
.finish(finish) .finish(finish)
); );
// ------------------------------------------------------------------------- // -------------------------------------------------------------------------
// Simple LED status // LED status TODO
// ------------------------------------------------------------------------- // -------------------------------------------------------------------------
assign led[0] = clk_wiz_locked; assign led[0] = clk_locked;
assign led[1] = m_axis_rx_tvalid; assign led[1] = rst_n;
assign led[2] = dac_start; // assign led[2] = ;
// assign led[3] = ;
endmodule endmodule