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controller_wrapper_axil syntaxis corrected

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otroubi
2026-07-14 13:55:42 +03:00
parent c1031f6a26
commit 6c171c55d7
1 changed files with 14 additions and 15 deletions
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29
rtl/controller/src/controller_wrapper_axil.sv
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@ -1,5 +1,11 @@
module controller_wrapper_axil #(
parameter int unsigned ADDR_W = 16,
parameter int unsigned DATA_W = 32,
parameter int unsigned USER_W = 1,
parameter int unsigned DAC_DATA_WIDTH = 12,
parameter int unsigned AXI_ADDR_WIDTH = 16,
parameter int unsigned AXIS_ID_WIDTH = 8,
parameter int unsigned LEN_WIDTH = 20,
@ -9,16 +15,9 @@ parameter int unsigned TAG_WIDTH = 8,
parameter int unsigned READ_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH,
parameter int unsigned WRITE_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH,
parameter int unsigned DESC_CMD_RAW_WIDTH = READ_DESC_WIDTH + WRITE_DESC_WIDTH,
parameter int unsigned DESC_CMD_DATA_WIDTH = ((DESC_CMD_RAW_WIDTH + 7) / 8) * 8,
parameter int unsigned DESC_CMD_KEEP_WIDTH = DESC_CMD_DATA_WIDTH / 8,
parameter int unsigned READ_STATUS_WIDTH = TAG_WIDTH + 4,
parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4,
parameter int unsigned DESC_STATUS_RAW_WIDTH = READ_STATUS_WIDTH + WRITE_STATUS_WIDTH,
parameter int unsigned DESC_STATUS_DATA_WIDTH = ((DESC_STATUS_RAW_WIDTH + 7) / 8) * 8,
parameter int unsigned DESC_STATUS_KEEP_WIDTH = DESC_STATUS_DATA_WIDTH / 8,
parameter int unsigned DESC_STATUS_USER_WIDTH = 2
parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4
)
(
input logic ctrl_clk,
@ -73,6 +72,9 @@ parameter int unsigned DESC_STATUS_USER_WIDTH = 2
logic [31:0] desc_read_addr, desc_read_len, desc_read_config, status_read;
logic [31:0] desc_write_addr, desc_write_len_and_tag, status_write_len, status_write_config;
logic desc_read_dma_busy, desc_write_dma_busy, status_read_dma_busy, status_write_dma_busy;
logic desc_read_dma_hs, desc_write_dma_hs, status_read_dma_hs, status_write_dma_hs;
axi4l_reg_map_controller #(
.ADDR_W(ADDR_W),
.DATA_W(DATA_W),
@ -112,7 +114,7 @@ parameter int unsigned DESC_STATUS_USER_WIDTH = 2
.desc_write_len_and_tag_o(desc_write_len_and_tag),
.status_write_len_i(status_write_len),
.status_write_config_i(status_write_config)
.status_write_config_i(status_write_config),
.desc_read_dma_busy_i(desc_read_dma_busy),
.desc_write_dma_busy_i(desc_write_dma_busy),
@ -176,20 +178,17 @@ parameter int unsigned DESC_STATUS_USER_WIDTH = 2
assign desc_write_cmd = {desc_write_len_and_tag[LEN_WIDTH+TAG_WIDTH-1:0],desc_write_addr[AXI_ADDR_WIDTH-1:0]};
logic [READ_STATUS_WIDTH-1:0] status_read_cmd;
assign status_read_cmd = status_read[TAG_WIDTH+4:0];
assign status_read_cmd = status_read[READ_STATUS_WIDTH-1:0];
logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd;
assign status_write_cmd = {status_write_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH+AXIS_USER_WIDTH+4:0], status_write_len[LEN_WIDTH-1:0]};
logic desc_read_dma_busy, desc_write_dma_busy, status_read_dma_busy, status_write_dma_busy;
logic desc_read_dma_hs, desc_write_dma_hs, status_read_dma_hs, status_write_dma_hs;
assign status_write_cmd = {status_write_config[TAG_WIDTH+AXIS_ID_WIDTH+AXIS_DEST_WIDTH+AXIS_USER_WIDTH+3:0], status_write_len[LEN_WIDTH-1:0]};
dma_controller
#(
.READ_DESC_WIDTH(READ_DESC_WIDTH),
.WRITE_DESC_WIDTH(WRITE_DESC_WIDTH),
.READ_STATUS_WIDTH(READ_STATUS_WIDTH),
.WRITE_STATUS_WIDTH(WRITE_STATUS_WIDTH),
.WRITE_STATUS_WIDTH(WRITE_STATUS_WIDTH)
) dma_controller_inst
(
.dma_clk(ctrl_clk),