change: remove DAC strobing generation. RTL+TB complete

This commit is contained in:
Zer0Nu11
2026-06-10 11:59:36 +03:00
parent d90167984a
commit 6542995930
2 changed files with 3 additions and 14 deletions

View File

@ -15,7 +15,6 @@ module generator
input [15:0] pulse_num,
input request,
output dac_wrt,
output logic [DATA_WIDTH-1:0] dac_out,
output logic done
);
@ -85,11 +84,4 @@ module generator
end
end
end
// Gated DAC write signal from DAC clock. Needed for posedge
OBUF OBUF_pulse_clk (
.I(clk_dac & enable),
.O(dac_wrt)
);
endmodule

View File

@ -20,7 +20,6 @@ module generator_tb;
logic [15:0] pulse_num; // config reg
logic sampler_done; // sampler request for synchronization
// Выходные сигналы
wire dac_wrt; // DAC wrt singnal
wire [DATA_WIDTH-1:0] dac_out; // DAC input logic signal
wire generator_done; // generator request for synchronization
@ -47,7 +46,6 @@ module generator_tb;
.pulse_period(pulse_period),
.pulse_height(pulse_height),
.pulse_num(pulse_num),
.dac_wrt(dac_wrt),
.dac_out(dac_out),
.done(generator_done),
.request(sampler_done)
@ -66,7 +64,6 @@ module generator_tb;
.pulse_period(pulse_period),
.pulse_height(pulse_height),
.pulse_num(pulse_num),
.dac_wrt(dac_wrt),
.dac_out(dac_out),
.done(generator_done),
.request(sampler_done)
@ -74,7 +71,7 @@ module generator_tb;
initial $display("[TB] Generator compiled. ZERO_LEVEL: LOGIC");
end
else begin : gen_dut_error
// защита от дурака
// Защита от дурака
initial begin
$display("[ERROR] Unknown value ZERO_LEVEL: %s", ZERO_LEVEL);
$finish;
@ -181,7 +178,7 @@ module generator_tb;
fork
begin : counter_proc
forever begin
@(posedge dac_wrt);
@(negedge clk); // 180 deg. phase shift for "DAC strobing signal"
if (dac_out == pulse_h) begin
total_impulse_cycles++;
end
@ -253,7 +250,7 @@ module generator_tb;
fork
begin : counter_proc
forever begin
@(posedge dac_wrt);
@(negedge clk); // 180 deg. phase shift for "DAC strobing signal"
if (count_level) begin
if (dac_out == pulse_h) begin
total_impulse_cycles++;