From 6542995930f350adfbf5fb30927f20121d643420 Mon Sep 17 00:00:00 2001
From: Zer0Nu11 <levo950@gmail.com>
Date: Wed, 10 Jun 2026 11:59:36 +0300
Subject: [PATCH] change: remove DAC strobing generation. RTL+TB complete

---
 rtl/generator/src/generator.sv      | 8 --------
 rtl/generator/tests/generator_tb.sv | 9 +++------
 2 files changed, 3 insertions(+), 14 deletions(-)

diff --git a/rtl/generator/src/generator.sv b/rtl/generator/src/generator.sv
index 58d150a..862c59e 100644
--- a/rtl/generator/src/generator.sv
+++ b/rtl/generator/src/generator.sv
@@ -15,7 +15,6 @@ module generator
     input [15:0]           pulse_num,
     input request,
     
-    output dac_wrt,
     output logic [DATA_WIDTH-1:0] dac_out,
     output logic done
 );
@@ -85,11 +84,4 @@ module generator
             end
         end
     end
-
-    // Gated DAC write signal from DAC clock. Needed for posedge
-    OBUF OBUF_pulse_clk (
-        .I(clk_dac & enable),
-        .O(dac_wrt)
-    );
-    
 endmodule
diff --git a/rtl/generator/tests/generator_tb.sv b/rtl/generator/tests/generator_tb.sv
index 36c9d65..fa01045 100644
--- a/rtl/generator/tests/generator_tb.sv
+++ b/rtl/generator/tests/generator_tb.sv
@@ -20,7 +20,6 @@ module generator_tb;
     logic [15:0]            pulse_num;      // config reg
     logic sampler_done;             // sampler request for synchronization
     // Выходные сигналы
-    wire dac_wrt;                   // DAC wrt singnal
     wire [DATA_WIDTH-1:0] dac_out;  // DAC input logic signal
     wire generator_done;            // generator request for synchronization
 
@@ -47,7 +46,6 @@ module generator_tb;
                 .pulse_period(pulse_period),
                 .pulse_height(pulse_height),
                 .pulse_num(pulse_num),
-                .dac_wrt(dac_wrt),
                 .dac_out(dac_out),
                 .done(generator_done),
                 .request(sampler_done)
@@ -66,7 +64,6 @@ module generator_tb;
                 .pulse_period(pulse_period),
                 .pulse_height(pulse_height),
                 .pulse_num(pulse_num),
-                .dac_wrt(dac_wrt),
                 .dac_out(dac_out),
                 .done(generator_done),
                 .request(sampler_done)
@@ -74,7 +71,7 @@ module generator_tb;
             initial $display("[TB] Generator compiled. ZERO_LEVEL: LOGIC");
         end
         else begin : gen_dut_error
-            // защита от дурака
+            // Защита от дурака
             initial begin
                 $display("[ERROR] Unknown value ZERO_LEVEL: %s", ZERO_LEVEL);
                 $finish;
@@ -181,7 +178,7 @@ module generator_tb;
         fork 
             begin : counter_proc
                 forever begin
-                    @(posedge dac_wrt);
+                    @(negedge clk); // 180 deg. phase shift for "DAC strobing signal"
                     if (dac_out == pulse_h) begin
                         total_impulse_cycles++;
                     end
@@ -253,7 +250,7 @@ module generator_tb;
         fork
             begin : counter_proc
                 forever begin
-                    @(posedge dac_wrt);
+                    @(negedge clk); // 180 deg. phase shift for "DAC strobing signal"
                     if (count_level) begin
                         if (dac_out == pulse_h) begin
                             total_impulse_cycles++;