change: remove DAC strobing generation. RTL+TB complete
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@ -20,7 +20,6 @@ module generator_tb;
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logic [15:0] pulse_num; // config reg
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logic sampler_done; // sampler request for synchronization
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// Выходные сигналы
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wire dac_wrt; // DAC wrt singnal
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wire [DATA_WIDTH-1:0] dac_out; // DAC input logic signal
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wire generator_done; // generator request for synchronization
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@ -47,7 +46,6 @@ module generator_tb;
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.pulse_period(pulse_period),
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.pulse_height(pulse_height),
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.pulse_num(pulse_num),
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.dac_wrt(dac_wrt),
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.dac_out(dac_out),
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.done(generator_done),
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.request(sampler_done)
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@ -66,7 +64,6 @@ module generator_tb;
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.pulse_period(pulse_period),
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.pulse_height(pulse_height),
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.pulse_num(pulse_num),
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.dac_wrt(dac_wrt),
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.dac_out(dac_out),
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.done(generator_done),
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.request(sampler_done)
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@ -74,7 +71,7 @@ module generator_tb;
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initial $display("[TB] Generator compiled. ZERO_LEVEL: LOGIC");
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end
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else begin : gen_dut_error
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// защита от дурака
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// Защита от дурака
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initial begin
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$display("[ERROR] Unknown value ZERO_LEVEL: %s", ZERO_LEVEL);
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$finish;
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@ -181,7 +178,7 @@ module generator_tb;
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fork
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begin : counter_proc
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forever begin
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@(posedge dac_wrt);
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@(negedge clk); // 180 deg. phase shift for "DAC strobing signal"
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if (dac_out == pulse_h) begin
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total_impulse_cycles++;
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end
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@ -253,7 +250,7 @@ module generator_tb;
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fork
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begin : counter_proc
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forever begin
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@(posedge dac_wrt);
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@(negedge clk); // 180 deg. phase shift for "DAC strobing signal"
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if (count_level) begin
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if (dac_out == pulse_h) begin
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total_impulse_cycles++;
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