rtl: debug synchronizer project constraints

2026-05-06 14:41:15 +03:00
parent 03d0abbe86
commit 57570bea00
1 changed files with 10 additions and 0 deletions
--- a/designs/adc_dac_synchoronizer/debug.xdc
+++ b/designs/adc_dac_synchoronizer/debug.xdc
@ -0,0 +1,10 @@
+# Primary clocks
+create_clock -name eth_clk -period 8.000  [get_ports dac_clk_in]
+create_clock -name acc_clk -period 15.385  [get_ports adc_clk_in]
+
+
+# Asynchronous clock groups
+
+set_clock_groups -name ASYNC_ETH_ACC -asynchronous \
+    -group [get_clocks eth_clk] \
+    -group [get_clocks acc_clk]