rtl: add window_size register

rtl/controller/src/axi4l_reg_map_controller.sv

@@ -13,6 +13,7 @@ module axi4l_reg_map_controller #(
   output logic [31:0] pulse_num_o,
   output logic [31:0] pulse_height_raw_o,
   output logic [31:0] pulse_period_ADC_o,
+  output logic [31:0] window_size_o,
 
   // DMA read descriptors and status register
   output logic [31:0] desc_read_addr_o,
@@ -74,6 +75,7 @@ module axi4l_reg_map_controller #(
   assign pulse_num_o              = reg_o[REG_DAC_PULSE_NUM];
   assign pulse_height_raw_o       = reg_o[REG_DAC_PULSE_HEIGHT]; 
   assign pulse_period_ADC_o       = reg_o[REG_ADC_PERIOD]; 
+  assign window_size_o            = reg_o[REG_WINDOW_SIZE];
 
   assign desc_read_addr_o         = reg_o[REG_DESC_READ_ADDR];
   assign desc_read_len_o          = reg_o[REG_DESC_READ_LEN];