diff --git a/rtl/controller/src/axi4l_reg_map_controller.sv b/rtl/controller/src/axi4l_reg_map_controller.sv
index a8eec8c..ea7d033 100644
--- a/rtl/controller/src/axi4l_reg_map_controller.sv
+++ b/rtl/controller/src/axi4l_reg_map_controller.sv
@@ -13,6 +13,7 @@ module axi4l_reg_map_controller #(
   output logic [31:0] pulse_num_o,
   output logic [31:0] pulse_height_raw_o,
   output logic [31:0] pulse_period_ADC_o,
+  output logic [31:0] window_size_o,
 
   // DMA read descriptors and status register
   output logic [31:0] desc_read_addr_o,
@@ -74,6 +75,7 @@ module axi4l_reg_map_controller #(
   assign pulse_num_o              = reg_o[REG_DAC_PULSE_NUM];
   assign pulse_height_raw_o       = reg_o[REG_DAC_PULSE_HEIGHT]; 
   assign pulse_period_ADC_o       = reg_o[REG_ADC_PERIOD]; 
+  assign window_size_o            = reg_o[REG_WINDOW_SIZE];
 
   assign desc_read_addr_o         = reg_o[REG_DESC_READ_ADDR];
   assign desc_read_len_o          = reg_o[REG_DESC_READ_LEN];
diff --git a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv
index 8a4b3c6..2410842 100644
--- a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv
+++ b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv
@@ -1,6 +1,6 @@
 package axi4l_reg_map_controller_pkg;
 
-  localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 16;
+  localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 17;
 
 /*
 dac adc configuration registers
@@ -12,25 +12,26 @@ dac adc configuration registers
   localparam logic [31:0] REG_DAC_PULSE_NUM          = 32'd4;
   localparam logic [31:0] REG_DAC_PULSE_HEIGHT       = 32'd5;
   localparam logic [31:0] REG_ADC_PERIOD             = 32'd6;
-  localparam logic [31:0] REG_ERROR                  = 32'd7;
+  localparam logic [31:0] REG_WINDOW_SIZE            = 32'd7;
+  localparam logic [31:0] REG_ERROR                  = 32'd8;
 
 /*
 AXI read descriptor input and AXI read descriptor status output configuration registers
 */
-  localparam logic [31:0] REG_DESC_READ_ADDR         = 32'd8;
-  localparam logic [31:0] REG_DESC_READ_LEN          = 32'd9;
-  localparam logic [31:0] REG_DESC_READ_CONFIG       = 32'd10;
+  localparam logic [31:0] REG_DESC_READ_ADDR         = 32'd9;
+  localparam logic [31:0] REG_DESC_READ_LEN          = 32'd10;
+  localparam logic [31:0] REG_DESC_READ_CONFIG       = 32'd11;
 
-  localparam logic [31:0] REG_READ_STATUS            = 32'd11;
+  localparam logic [31:0] REG_READ_STATUS            = 32'd12;
 
 /*
 AXI write descriptor input and AXI write descriptor status output configuration registers
 */
-  localparam logic [31:0] REG_DESC_WRITE_ADDR        = 32'd12;
-  localparam logic [31:0] REG_DESC_WRITE_LEN_AND_TAG = 32'd13;
+  localparam logic [31:0] REG_DESC_WRITE_ADDR        = 32'd13;
+  localparam logic [31:0] REG_DESC_WRITE_LEN_AND_TAG = 32'd14;
 
-  localparam logic [31:0] REG_STATUS_WRITE_LEN       = 32'd14;
-  localparam logic [31:0] REG_STATUS_WRITE_CONFIG    = 32'd15;
+  localparam logic [31:0] REG_STATUS_WRITE_LEN       = 32'd15;
+  localparam logic [31:0] REG_STATUS_WRITE_CONFIG    = 32'd16;
 
 
   localparam logic [2:0] REG_BIT_RSVD = 3'd0;
@@ -68,6 +69,9 @@ AXI write descriptor input and AXI write descriptor status output configuration
      // REG_ADC_PERIOD
      '{default: REG_BIT_RW},
 
+     // REG_WINDOW_SIZE
+     '{default: REG_BIT_RW},
+
     // REG_ERROR
     '{
       REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,