new test dma-accum connection
This commit is contained in:
otroubi
@@ -0,0 +1,234 @@
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import dma_reg_pkg::*;
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module wrapper_controller_dma_accum
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#(
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parameter int unsigned ADDR_W = 16,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1,
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parameter int unsigned DAC_DATA_WIDTH = 12,
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parameter int unsigned AXI_DATA_WIDTH = 32,
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parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
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parameter int unsigned AXI_ID_WIDTH = 8,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_MAX_BURST_LEN = 16,
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parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
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parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
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parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
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parameter int unsigned AXIS_LAST_ENABLE = 1,
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parameter int unsigned AXIS_ID_ENABLE = 1,
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parameter int unsigned AXIS_DEST_ENABLE = 0,
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parameter int unsigned AXIS_USER_ENABLE = 1,
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parameter int unsigned ENABLE_SG = 0,
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parameter int unsigned ENABLE_UNALIGNED = 0,
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parameter int unsigned PIPELINE_OUTPUT = 0,
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parameter int unsigned ADC_DATA_WIDTH = 12,
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parameter int unsigned ACCUM_WIDTH = 32,
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parameter int unsigned N_MAX = 4096,
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parameter int unsigned PACKET_SIZE = 64,
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parameter int unsigned RD_FIFO_WIDTH = 32
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)
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(
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input logic ctrl_clk,
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input logic clk_generator,
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input logic clk_sampler,
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input logic rst_n,
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axi4l_if.slave s_axil,
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// adc_clk_in domain
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input logic [AXI_DATA_WIDTH-1:0] sampler_m_axis_tdata,
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input logic sampler_m_axis_tvalid,
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// dac_clk_in domain outputs
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output logic [31:0] dac_pulse_width,
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output logic [31:0] dac_pulse_period,
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output logic [DAC_DATA_WIDTH-1:0] dac_pulse_height,
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output logic [15:0] dac_pulse_num,
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// adc_clk_in domain outputs
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output logic [31:0] adc_pulse_period,
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output logic [15:0] adc_pulse_num,
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// pulse outputs
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output logic dac_start,
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output logic dac_rst
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axis_if.master m_axis_read_data
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);
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logic workflow_done, processing_done;
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logic [31:0] window_size;
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logic adc_start, adc_rst;
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axis_if #(
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.DATA_W($bits(dma_read_status_t)),
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.KEEP_W(($bits(dma_read_status_t)+7)/8),
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.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
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.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
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.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
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) s_axis_status_read (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axis_if #(
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.DATA_W($bits(dma_write_status_t)),
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.KEEP_W(($bits(dma_write_status_t)+7)/8),
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.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
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.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
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.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
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) s_axis_status_write (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axis_if #(
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.DATA_W(RD_FIFO_WIDTH),
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.KEEP_W((RD_FIFO_WIDTH+7)/8),
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.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
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.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
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.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
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) m_axis_accum (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axis_if #(
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.DATA_W($bits(dma_read_desc_t)),
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.KEEP_W(($bits(dma_read_desc_t)+7)/8),
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.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
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.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
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.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
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) m_axis_desc_read (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axis_if #(
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.DATA_W($bits(dma_write_desc_t)),
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.KEEP_W(($bits(dma_write_desc_t)+7)/8),
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.ID_W(dma_reg_pkg::AXIS_ID_WIDTH),
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.DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH),
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.USER_W(dma_reg_pkg::AXIS_USER_WIDTH)
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) m_axis_desc_write (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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controller_wrapper_axil #(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W),
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
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) controller_wrapper_axil_inst
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(
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.ctrl_clk(ctrl_clk),
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.dac_clk_in(clk_generator),
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.adc_clk_in(clk_sampler),
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.rst_n(rst_n),
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.s_axil(s_axil),
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.workflow_done(workflow_done),
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.processing_done(processing_done),
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.adc_window_size(window_size),
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.dac_pulse_width(dac_pulse_width),
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.dac_pulse_period(dac_pulse_period),
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.dac_pulse_height(dac_pulse_height),
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.dac_pulse_num(dac_pulse_num),
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.adc_pulse_period(adc_pulse_period),
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.adc_pulse_num(adc_pulse_num),
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.dac_start(dac_start),
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.adc_start(adc_start),
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.dac_rst(dac_rst),
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.adc_rst(adc_rst),
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.s_axis_status_read(s_axis_status_read),
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.s_axis_status_write(s_axis_status_write),
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.m_axis_desc_read(m_axis_desc_read),
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.m_axis_desc_write(m_axis_desc_write)
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);
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axi4_if #(
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.ADDR_W(dma_reg_pkg::AXI_ADDR_WIDTH),
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.DATA_W(AXI_DATA_WIDTH),
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.ID_W (AXI_ID_WIDTH),
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.USER_W(AXI_USER_WIDTH)
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) m_axi (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axi_dma_wrapper
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#(
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.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
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.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
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.AXI_USER_WIDTH(AXI_USER_WIDTH),
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.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
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.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
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.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
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.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
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.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
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.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
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.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
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.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
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.ENABLE_SG(ENABLE_SG),
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.ENABLE_UNALIGNED(ENABLE_UNALIGNED)
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)
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axi_dma_wrapper_inst
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(
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.clk(ctrl_clk),
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.rst(!rst_n),
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.s_axis_read_desc(m_axis_desc_read),
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.m_axis_read_desc_status(s_axis_status_read),
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.m_axis_read_data(m_axis_read_data),
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.s_axis_write_desc(m_axis_desc_write),
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.m_axis_write_desc_status(s_axis_status_write),
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.s_axis_write_data(m_axis_accum),
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.m_axi(m_axi)
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);
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axi_ram_wrapper
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#(
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.DATA_WIDTH(AXI_DATA_WIDTH),
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.ADDR_WIDTH(dma_reg_pkg::AXI_ADDR_WIDTH),
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.ID_WIDTH(dma_reg_pkg::AXIS_ID_WIDTH),
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.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
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) axi_ram_wrapper_inst
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(
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.clk(ctrl_clk),
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.rst(!rst_n),
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.s_axi(m_axi)
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);
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accumulator_top #(
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.DATA_WIDTH(ADC_DATA_WIDTH),
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.ACCUM_WIDTH(ACCUM_WIDTH),
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.N_MAX(N_MAX),
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.PACKET_SIZE(PACKET_SIZE),
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.RW_WIDTH(RD_FIFO_WIDTH)
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) accumulator_top_inst (
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.clk_in(clk_sampler),
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.rst(adc_rst),
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.s_axis_tdata(sampler_m_axis_tdata[ADC_DATA_WIDTH-1:0]),
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.s_axis_tvalid(sampler_m_axis_tvalid),
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.start(adc_start),
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.smp_num(adc_pulse_period),
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.seq_num(adc_pulse_num),
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.window_size(window_size),
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.dma_clk_in(ctrl_clk),
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.req_ready(1'b1),
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.m_axis_accum(m_axis_accum),
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.finish(workflow_done),
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.accum_done(processing_done)
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);
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endmodule
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+279
@@ -0,0 +1,279 @@
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import dma_reg_pkg::*;
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module tb_controller_dma_accum_wrapper_axil #(
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parameter int unsigned ADDR_W = 16,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1,
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parameter int unsigned DAC_DATA_WIDTH = 12,
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parameter int unsigned AXI_DATA_WIDTH = 32,
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parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
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parameter int unsigned AXI_ID_WIDTH = 8,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_MAX_BURST_LEN = 16,
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parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
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parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
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parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
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parameter int unsigned AXIS_LAST_ENABLE = 1,
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parameter int unsigned AXIS_ID_ENABLE = 1,
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parameter int unsigned AXIS_DEST_ENABLE = 0,
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parameter int unsigned AXIS_USER_ENABLE = 1,
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parameter int unsigned ENABLE_SG = 0,
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parameter int unsigned ENABLE_UNALIGNED = 0,
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parameter int unsigned ADC_DATA_WIDTH = 12,
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parameter int unsigned ACCUM_WIDTH = 32,
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parameter int unsigned N_MAX = 4096,
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parameter int unsigned PACKET_SIZE = 64,
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parameter int unsigned RD_FIFO_WIDTH = 32
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)(
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input logic ctrl_clk,
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input logic rst,
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input logic [ADDR_W-1:0] s_axil_awaddr,
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input logic [2:0] s_axil_awprot,
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input logic s_axil_awvalid,
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output logic s_axil_awready,
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input logic [DATA_W-1:0] s_axil_wdata,
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input logic [DATA_W/8-1:0] s_axil_wstrb,
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input logic s_axil_wvalid,
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output logic s_axil_wready,
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output logic [1:0] s_axil_bresp,
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output logic s_axil_bvalid,
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input logic s_axil_bready,
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input logic [ADDR_W-1:0] s_axil_araddr,
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input logic [2:0] s_axil_arprot,
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input logic s_axil_arvalid,
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output logic s_axil_arready,
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output logic [DATA_W-1:0] s_axil_rdata,
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output logic [1:0] s_axil_rresp,
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output logic s_axil_rvalid,
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input logic s_axil_rready,
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep,
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input wire s_axis_write_data_tvalid,
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output wire s_axis_write_data_tready,
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input wire s_axis_write_data_tlast,
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input wire [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid,
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input wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest,
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input wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser,
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep,
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output wire m_axis_read_data_tvalid,
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input wire m_axis_read_data_tready,
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output wire m_axis_read_data_tlast,
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output wire [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid,
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output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
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output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
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output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire m_axi_awlock,
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output wire [3:0] m_axi_awcache,
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output wire [2:0] m_axi_awprot,
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output wire m_axi_awvalid,
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input wire m_axi_awready,
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output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
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output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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output wire m_axi_wvalid,
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input wire m_axi_wready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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input wire m_axi_bvalid,
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output wire m_axi_bready,
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output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [7:0] m_axi_arlen,
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output wire [2:0] m_axi_arsize,
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output wire [1:0] m_axi_arburst,
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output wire m_axi_arlock,
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output wire [3:0] m_axi_arcache,
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output wire [2:0] m_axi_arprot,
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output wire m_axi_arvalid,
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input wire m_axi_arready,
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input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
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input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
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input wire [1:0] m_axi_rresp,
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input wire m_axi_rlast,
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input wire m_axi_rvalid,
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output wire m_axi_rready
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);
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logic rst_n;
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assign rst_n = ~rst;
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// Для минимального теста держим все clock domain-ы на одном clock.
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logic dac_clk_in;
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logic adc_clk_in;
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assign dac_clk_in = ctrl_clk;
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assign adc_clk_in = ctrl_clk;
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logic finish;
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assign finish = 1'b0;
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// ---------------------------------------------------------------------------
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// AXI-Lite flat -> axi4l_if
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// ---------------------------------------------------------------------------
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axi4l_if #(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W)
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) axil_bus (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axi4l_flat_to_if #(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W)
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) u_axil_flat_to_if (
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.s_axil_awaddr (s_axil_awaddr),
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.s_axil_awprot (s_axil_awprot),
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.s_axil_awvalid(s_axil_awvalid),
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.s_axil_awready(s_axil_awready),
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.s_axil_wdata (s_axil_wdata),
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.s_axil_wstrb (s_axil_wstrb),
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.s_axil_wvalid (s_axil_wvalid),
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.s_axil_wready (s_axil_wready),
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.s_axil_bresp (s_axil_bresp),
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.s_axil_bvalid (s_axil_bvalid),
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.s_axil_bready (s_axil_bready),
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.s_axil_araddr (s_axil_araddr),
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.s_axil_arprot (s_axil_arprot),
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.s_axil_arvalid(s_axil_arvalid),
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.s_axil_arready(s_axil_arready),
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.s_axil_rdata (s_axil_rdata),
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.s_axil_rresp (s_axil_rresp),
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.s_axil_rvalid (s_axil_rvalid),
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.s_axil_rready (s_axil_rready),
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.m_axil(axil_bus)
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);
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// ---------------------------------------------------------------------------
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// AXIS interfaces for the updated controller_wrapper_axil
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// ---------------------------------------------------------------------------
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// AXIS READ DMA MASTER output
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axis_if #(
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.DATA_W (AXIS_DATA_WIDTH),
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.KEEP_W (AXIS_KEEP_WIDTH),
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.ID_W (AXIS_ID_WIDTH),
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.DEST_W (AXIS_DEST_WIDTH),
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.USER_W (AXIS_USER_WIDTH)
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) dma_read_data (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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|
||||
logic [AXIS_KEEP_WIDTH-1:0] unused_read_tstrb;
|
||||
|
||||
axis_if_to_flat #(
|
||||
.DATA_W (AXIS_DATA_WIDTH),
|
||||
.KEEP_W (AXIS_KEEP_WIDTH),
|
||||
.ID_W (AXIS_ID_WIDTH),
|
||||
.DEST_W (AXIS_DEST_WIDTH),
|
||||
.USER_W (AXIS_USER_WIDTH)
|
||||
) u_read_data_if_to_flat (
|
||||
.s_axis(dma_read_data),
|
||||
|
||||
.m_axis_tdata (m_axis_read_data_tdata),
|
||||
.m_axis_tkeep (m_axis_read_data_tkeep),
|
||||
.m_axis_tstrb (unused_read_tstrb),
|
||||
.m_axis_tlast (m_axis_read_data_tlast),
|
||||
.m_axis_tid (m_axis_read_data_tid),
|
||||
.m_axis_tdest (m_axis_read_data_tdest),
|
||||
.m_axis_tuser (m_axis_read_data_tuser),
|
||||
.m_axis_tvalid(m_axis_read_data_tvalid),
|
||||
.m_axis_tready(m_axis_read_data_tready)
|
||||
);
|
||||
|
||||
|
||||
|
||||
// Controller ADC/DAC outputs.
|
||||
logic [31:0] adc_window_size;
|
||||
logic [31:0] dac_pulse_width;
|
||||
logic [31:0] dac_pulse_period;
|
||||
logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
|
||||
logic [15:0] dac_pulse_num;
|
||||
logic [31:0] adc_pulse_period;
|
||||
logic [15:0] adc_pulse_num;
|
||||
logic dac_start;
|
||||
logic adc_start;
|
||||
logic dac_rst;
|
||||
logic adc_rst;
|
||||
|
||||
wrapper_controller_dma_accum #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.USER_W(USER_W),
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
|
||||
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
|
||||
.AXI_ID_WIDTH(AXI_ID_WIDTH),
|
||||
.AXI_USER_WIDTH(AXI_USER_WIDTH),
|
||||
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
|
||||
.AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
|
||||
.AXIS_ID_ENABLE(AXIS_ID_ENABLE),
|
||||
.AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
|
||||
.AXIS_USER_ENABLE(AXIS_USER_ENABLE),
|
||||
.ENABLE_SG(ENABLE_SG),
|
||||
.ENABLE_UNALIGNED(ENABLE_UNALIGNED),
|
||||
|
||||
.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
|
||||
.ACCUM_WIDTH(ACCUM_WIDTH),
|
||||
.N_MAX(N_MAX),
|
||||
.PACKET_SIZE(PACKET_SIZE),
|
||||
.RD_FIFO_WIDTH(RD_FIFO_WIDTH)
|
||||
) dut (
|
||||
.ctrl_clk(ctrl_clk),
|
||||
.clk_generator(dac_clk_in),
|
||||
.clk_sampler(adc_clk_in),
|
||||
.rst_n(rst_n),
|
||||
.s_axil(axil_bus),
|
||||
|
||||
.dac_pulse_width(dac_pulse_width),
|
||||
.dac_pulse_period(dac_pulse_period),
|
||||
.dac_pulse_height(dac_pulse_height),
|
||||
.dac_pulse_num(dac_pulse_num),
|
||||
|
||||
.sampler_m_axis_tdata(sampler_m_axis_tdata),
|
||||
.sampler_m_axis_tvalid(sampler_m_axis_tvalid),
|
||||
|
||||
.adc_pulse_period(adc_pulse_period),
|
||||
.adc_pulse_num(adc_pulse_num),
|
||||
|
||||
.dac_pulse_width(dac_pulse_width),
|
||||
.dac_pulse_period(dac_pulse_period),
|
||||
.dac_pulse_height(dac_pulse_height),
|
||||
.dac_pulse_num(dac_pulse_num),
|
||||
|
||||
.dac_start(dac_start),
|
||||
.dac_rst(dac_rst),
|
||||
|
||||
.m_axis_read_data(dma_read_data)
|
||||
);
|
||||
|
||||
endmodule : tb_controller_wrapper_axil
|
||||
@@ -47,6 +47,7 @@ module reflectometer_and_dma_wrapper
|
||||
|
||||
axi4l_if.slave s_axil,
|
||||
axi_if.master m_axi,
|
||||
// todo
|
||||
axis_if.master m_axis_read_data,
|
||||
|
||||
// DAC
|
||||
|
||||
Reference in New Issue
Block a user