diff --git a/designs/controller_dma_connective/src/wrapper_controller_dma_accum.sv b/designs/controller_dma_connective/src/wrapper_controller_dma_accum.sv new file mode 100644 index 0000000..5e7c391 --- /dev/null +++ b/designs/controller_dma_connective/src/wrapper_controller_dma_accum.sv @@ -0,0 +1,234 @@ +import dma_reg_pkg::*; + +module wrapper_controller_dma_accum +#( + parameter int unsigned ADDR_W = 16, + parameter int unsigned DATA_W = 32, + parameter int unsigned USER_W = 1, + + parameter int unsigned DAC_DATA_WIDTH = 12, + + parameter int unsigned AXI_DATA_WIDTH = 32, + + parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8, + parameter int unsigned AXI_ID_WIDTH = 8, + parameter int unsigned AXI_USER_WIDTH = 1, + parameter int unsigned AXI_MAX_BURST_LEN = 16, + + parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH, + parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8, + parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8, + parameter int unsigned AXIS_LAST_ENABLE = 1, + parameter int unsigned AXIS_ID_ENABLE = 1, + parameter int unsigned AXIS_DEST_ENABLE = 0, + parameter int unsigned AXIS_USER_ENABLE = 1, + + parameter int unsigned ENABLE_SG = 0, + parameter int unsigned ENABLE_UNALIGNED = 0, + + parameter int unsigned PIPELINE_OUTPUT = 0, + + parameter int unsigned ADC_DATA_WIDTH = 12, + parameter int unsigned ACCUM_WIDTH = 32, + parameter int unsigned N_MAX = 4096, + parameter int unsigned PACKET_SIZE = 64, + parameter int unsigned RD_FIFO_WIDTH = 32 +) +( + input logic ctrl_clk, + input logic clk_generator, + input logic clk_sampler, + input logic rst_n, + axi4l_if.slave s_axil, + + // adc_clk_in domain + + input logic [AXI_DATA_WIDTH-1:0] sampler_m_axis_tdata, + input logic sampler_m_axis_tvalid, + + // dac_clk_in domain outputs + output logic [31:0] dac_pulse_width, + output logic [31:0] dac_pulse_period, + output logic [DAC_DATA_WIDTH-1:0] dac_pulse_height, + output logic [15:0] dac_pulse_num, + + // adc_clk_in domain outputs + output logic [31:0] adc_pulse_period, + output logic [15:0] adc_pulse_num, + + // pulse outputs + output logic dac_start, + output logic dac_rst + + axis_if.master m_axis_read_data +); + +logic workflow_done, processing_done; +logic [31:0] window_size; +logic adc_start, adc_rst; + +axis_if #( + .DATA_W($bits(dma_read_status_t)), + .KEEP_W(($bits(dma_read_status_t)+7)/8), + .ID_W(dma_reg_pkg::AXIS_ID_WIDTH), + .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH), + .USER_W(dma_reg_pkg::AXIS_USER_WIDTH) + ) s_axis_status_read ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + + axis_if #( + .DATA_W($bits(dma_write_status_t)), + .KEEP_W(($bits(dma_write_status_t)+7)/8), + .ID_W(dma_reg_pkg::AXIS_ID_WIDTH), + .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH), + .USER_W(dma_reg_pkg::AXIS_USER_WIDTH) + ) s_axis_status_write ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + + axis_if #( + .DATA_W(RD_FIFO_WIDTH), + .KEEP_W((RD_FIFO_WIDTH+7)/8), + .ID_W(dma_reg_pkg::AXIS_ID_WIDTH), + .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH), + .USER_W(dma_reg_pkg::AXIS_USER_WIDTH) + ) m_axis_accum ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + + axis_if #( + .DATA_W($bits(dma_read_desc_t)), + .KEEP_W(($bits(dma_read_desc_t)+7)/8), + .ID_W(dma_reg_pkg::AXIS_ID_WIDTH), + .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH), + .USER_W(dma_reg_pkg::AXIS_USER_WIDTH) + ) m_axis_desc_read ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + + axis_if #( + .DATA_W($bits(dma_write_desc_t)), + .KEEP_W(($bits(dma_write_desc_t)+7)/8), + .ID_W(dma_reg_pkg::AXIS_ID_WIDTH), + .DEST_W(dma_reg_pkg::AXIS_DEST_WIDTH), + .USER_W(dma_reg_pkg::AXIS_USER_WIDTH) + ) m_axis_desc_write ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + +controller_wrapper_axil #( + .ADDR_W(ADDR_W), + .DATA_W(DATA_W), + .USER_W(USER_W), + .DAC_DATA_WIDTH(DAC_DATA_WIDTH) + ) controller_wrapper_axil_inst + ( + .ctrl_clk(ctrl_clk), + .dac_clk_in(clk_generator), + .adc_clk_in(clk_sampler), + .rst_n(rst_n), + + .s_axil(s_axil), + + .workflow_done(workflow_done), + .processing_done(processing_done), + + .adc_window_size(window_size), + .dac_pulse_width(dac_pulse_width), + .dac_pulse_period(dac_pulse_period), + .dac_pulse_height(dac_pulse_height), + .dac_pulse_num(dac_pulse_num), + .adc_pulse_period(adc_pulse_period), + .adc_pulse_num(adc_pulse_num), + .dac_start(dac_start), + .adc_start(adc_start), + .dac_rst(dac_rst), + .adc_rst(adc_rst), + + .s_axis_status_read(s_axis_status_read), + .s_axis_status_write(s_axis_status_write), + .m_axis_desc_read(m_axis_desc_read), + .m_axis_desc_write(m_axis_desc_write) + ); + +axi4_if #( + .ADDR_W(dma_reg_pkg::AXI_ADDR_WIDTH), + .DATA_W(AXI_DATA_WIDTH), + .ID_W (AXI_ID_WIDTH), + .USER_W(AXI_USER_WIDTH) + ) m_axi ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + +axi_dma_wrapper +#( + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_STRB_WIDTH(AXI_STRB_WIDTH), + .AXI_USER_WIDTH(AXI_USER_WIDTH), + .AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .AXIS_LAST_ENABLE(AXIS_LAST_ENABLE), + .AXIS_ID_ENABLE(AXIS_ID_ENABLE), + .AXIS_DEST_ENABLE(AXIS_DEST_ENABLE), + .AXIS_USER_ENABLE(AXIS_USER_ENABLE), + .ENABLE_SG(ENABLE_SG), + .ENABLE_UNALIGNED(ENABLE_UNALIGNED) +) +axi_dma_wrapper_inst +( + .clk(ctrl_clk), + .rst(!rst_n), + .s_axis_read_desc(m_axis_desc_read), + .m_axis_read_desc_status(s_axis_status_read), + .m_axis_read_data(m_axis_read_data), + .s_axis_write_desc(m_axis_desc_write), + .m_axis_write_desc_status(s_axis_status_write), + .s_axis_write_data(m_axis_accum), + .m_axi(m_axi) +); + +axi_ram_wrapper +#( + .DATA_WIDTH(AXI_DATA_WIDTH), + .ADDR_WIDTH(dma_reg_pkg::AXI_ADDR_WIDTH), + .ID_WIDTH(dma_reg_pkg::AXIS_ID_WIDTH), + .PIPELINE_OUTPUT(PIPELINE_OUTPUT) +) axi_ram_wrapper_inst +( + .clk(ctrl_clk), + .rst(!rst_n), + .s_axi(m_axi) +); + +accumulator_top #( + .DATA_WIDTH(ADC_DATA_WIDTH), + .ACCUM_WIDTH(ACCUM_WIDTH), + .N_MAX(N_MAX), + .PACKET_SIZE(PACKET_SIZE), + .RW_WIDTH(RD_FIFO_WIDTH) + ) accumulator_top_inst ( + .clk_in(clk_sampler), + .rst(adc_rst), + .s_axis_tdata(sampler_m_axis_tdata[ADC_DATA_WIDTH-1:0]), + .s_axis_tvalid(sampler_m_axis_tvalid), + .start(adc_start), + .smp_num(adc_pulse_period), + .seq_num(adc_pulse_num), + .window_size(window_size), + .dma_clk_in(ctrl_clk), + .req_ready(1'b1), + .m_axis_accum(m_axis_accum), + .finish(workflow_done), + .accum_done(processing_done) + ); + +endmodule \ No newline at end of file diff --git a/designs/controller_dma_connective/tests/dma_accum_connection/tb_controller_dma_accum_wrapper_axil.sv b/designs/controller_dma_connective/tests/dma_accum_connection/tb_controller_dma_accum_wrapper_axil.sv new file mode 100644 index 0000000..fea96da --- /dev/null +++ b/designs/controller_dma_connective/tests/dma_accum_connection/tb_controller_dma_accum_wrapper_axil.sv @@ -0,0 +1,279 @@ + +import dma_reg_pkg::*; + +module tb_controller_dma_accum_wrapper_axil #( + parameter int unsigned ADDR_W = 16, + parameter int unsigned DATA_W = 32, + parameter int unsigned USER_W = 1, + + parameter int unsigned DAC_DATA_WIDTH = 12, + + parameter int unsigned AXI_DATA_WIDTH = 32, + + parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8, + parameter int unsigned AXI_ID_WIDTH = 8, + parameter int unsigned AXI_USER_WIDTH = 1, + parameter int unsigned AXI_MAX_BURST_LEN = 16, + + parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH, + parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8, + parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8, + parameter int unsigned AXIS_LAST_ENABLE = 1, + parameter int unsigned AXIS_ID_ENABLE = 1, + parameter int unsigned AXIS_DEST_ENABLE = 0, + parameter int unsigned AXIS_USER_ENABLE = 1, + + parameter int unsigned ENABLE_SG = 0, + parameter int unsigned ENABLE_UNALIGNED = 0, + + parameter int unsigned ADC_DATA_WIDTH = 12, + parameter int unsigned ACCUM_WIDTH = 32, + parameter int unsigned N_MAX = 4096, + parameter int unsigned PACKET_SIZE = 64, + parameter int unsigned RD_FIFO_WIDTH = 32 +)( + input logic ctrl_clk, + input logic rst, + + input logic [ADDR_W-1:0] s_axil_awaddr, + input logic [2:0] s_axil_awprot, + input logic s_axil_awvalid, + output logic s_axil_awready, + + input logic [DATA_W-1:0] s_axil_wdata, + input logic [DATA_W/8-1:0] s_axil_wstrb, + input logic s_axil_wvalid, + output logic s_axil_wready, + + output logic [1:0] s_axil_bresp, + output logic s_axil_bvalid, + input logic s_axil_bready, + + input logic [ADDR_W-1:0] s_axil_araddr, + input logic [2:0] s_axil_arprot, + input logic s_axil_arvalid, + output logic s_axil_arready, + + output logic [DATA_W-1:0] s_axil_rdata, + output logic [1:0] s_axil_rresp, + output logic s_axil_rvalid, + input logic s_axil_rready, + + input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata, + input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep, + input wire s_axis_write_data_tvalid, + output wire s_axis_write_data_tready, + input wire s_axis_write_data_tlast, + input wire [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid, + input wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest, + input wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser, + + output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep, + output wire m_axis_read_data_tvalid, + input wire m_axis_read_data_tready, + output wire m_axis_read_data_tlast, + output wire [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid, + output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest, + output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser, + + output wire [AXI_ID_WIDTH-1:0] m_axi_awid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [7:0] m_axi_awlen, + output wire [2:0] m_axi_awsize, + output wire [1:0] m_axi_awburst, + output wire m_axi_awlock, + output wire [3:0] m_axi_awcache, + output wire [2:0] m_axi_awprot, + output wire m_axi_awvalid, + input wire m_axi_awready, + output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire m_axi_wvalid, + input wire m_axi_wready, + input wire [AXI_ID_WIDTH-1:0] m_axi_bid, + input wire [1:0] m_axi_bresp, + input wire m_axi_bvalid, + output wire m_axi_bready, + output wire [AXI_ID_WIDTH-1:0] m_axi_arid, + output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [7:0] m_axi_arlen, + output wire [2:0] m_axi_arsize, + output wire [1:0] m_axi_arburst, + output wire m_axi_arlock, + output wire [3:0] m_axi_arcache, + output wire [2:0] m_axi_arprot, + output wire m_axi_arvalid, + input wire m_axi_arready, + input wire [AXI_ID_WIDTH-1:0] m_axi_rid, + input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire m_axi_rvalid, + output wire m_axi_rready + + +); + + logic rst_n; + assign rst_n = ~rst; + + // Для минимального теста держим все clock domain-ы на одном clock. + logic dac_clk_in; + logic adc_clk_in; + assign dac_clk_in = ctrl_clk; + assign adc_clk_in = ctrl_clk; + + logic finish; + assign finish = 1'b0; + + // --------------------------------------------------------------------------- + // AXI-Lite flat -> axi4l_if + // --------------------------------------------------------------------------- + + axi4l_if #( + .ADDR_W(ADDR_W), + .DATA_W(DATA_W), + .USER_W(USER_W) + ) axil_bus ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + + axi4l_flat_to_if #( + .ADDR_W(ADDR_W), + .DATA_W(DATA_W), + .USER_W(USER_W) + ) u_axil_flat_to_if ( + .s_axil_awaddr (s_axil_awaddr), + .s_axil_awprot (s_axil_awprot), + .s_axil_awvalid(s_axil_awvalid), + .s_axil_awready(s_axil_awready), + + .s_axil_wdata (s_axil_wdata), + .s_axil_wstrb (s_axil_wstrb), + .s_axil_wvalid (s_axil_wvalid), + .s_axil_wready (s_axil_wready), + + .s_axil_bresp (s_axil_bresp), + .s_axil_bvalid (s_axil_bvalid), + .s_axil_bready (s_axil_bready), + + .s_axil_araddr (s_axil_araddr), + .s_axil_arprot (s_axil_arprot), + .s_axil_arvalid(s_axil_arvalid), + .s_axil_arready(s_axil_arready), + + .s_axil_rdata (s_axil_rdata), + .s_axil_rresp (s_axil_rresp), + .s_axil_rvalid (s_axil_rvalid), + .s_axil_rready (s_axil_rready), + + .m_axil(axil_bus) + ); + + // --------------------------------------------------------------------------- + // AXIS interfaces for the updated controller_wrapper_axil + // --------------------------------------------------------------------------- + +// AXIS READ DMA MASTER output + axis_if #( + .DATA_W (AXIS_DATA_WIDTH), + .KEEP_W (AXIS_KEEP_WIDTH), + .ID_W (AXIS_ID_WIDTH), + .DEST_W (AXIS_DEST_WIDTH), + .USER_W (AXIS_USER_WIDTH) + ) dma_read_data ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + +logic [AXIS_KEEP_WIDTH-1:0] unused_read_tstrb; + +axis_if_to_flat #( + .DATA_W (AXIS_DATA_WIDTH), + .KEEP_W (AXIS_KEEP_WIDTH), + .ID_W (AXIS_ID_WIDTH), + .DEST_W (AXIS_DEST_WIDTH), + .USER_W (AXIS_USER_WIDTH) +) u_read_data_if_to_flat ( + .s_axis(dma_read_data), + + .m_axis_tdata (m_axis_read_data_tdata), + .m_axis_tkeep (m_axis_read_data_tkeep), + .m_axis_tstrb (unused_read_tstrb), + .m_axis_tlast (m_axis_read_data_tlast), + .m_axis_tid (m_axis_read_data_tid), + .m_axis_tdest (m_axis_read_data_tdest), + .m_axis_tuser (m_axis_read_data_tuser), + .m_axis_tvalid(m_axis_read_data_tvalid), + .m_axis_tready(m_axis_read_data_tready) +); + + + + // Controller ADC/DAC outputs. + logic [31:0] adc_window_size; + logic [31:0] dac_pulse_width; + logic [31:0] dac_pulse_period; + logic [DAC_DATA_WIDTH-1:0] dac_pulse_height; + logic [15:0] dac_pulse_num; + logic [31:0] adc_pulse_period; + logic [15:0] adc_pulse_num; + logic dac_start; + logic adc_start; + logic dac_rst; + logic adc_rst; + + wrapper_controller_dma_accum #( + .ADDR_W(ADDR_W), + .DATA_W(DATA_W), + .USER_W(USER_W), + .DAC_DATA_WIDTH(DAC_DATA_WIDTH), + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_ID_WIDTH(AXI_ID_WIDTH), + .AXI_USER_WIDTH(AXI_USER_WIDTH), + .AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN), + .AXIS_LAST_ENABLE(AXIS_LAST_ENABLE), + .AXIS_ID_ENABLE(AXIS_ID_ENABLE), + .AXIS_DEST_ENABLE(AXIS_DEST_ENABLE), + .AXIS_USER_ENABLE(AXIS_USER_ENABLE), + .ENABLE_SG(ENABLE_SG), + .ENABLE_UNALIGNED(ENABLE_UNALIGNED), + + .ADC_DATA_WIDTH(ADC_DATA_WIDTH), + .ACCUM_WIDTH(ACCUM_WIDTH), + .N_MAX(N_MAX), + .PACKET_SIZE(PACKET_SIZE), + .RD_FIFO_WIDTH(RD_FIFO_WIDTH) + ) dut ( + .ctrl_clk(ctrl_clk), + .clk_generator(dac_clk_in), + .clk_sampler(adc_clk_in), + .rst_n(rst_n), + .s_axil(axil_bus), + + .dac_pulse_width(dac_pulse_width), + .dac_pulse_period(dac_pulse_period), + .dac_pulse_height(dac_pulse_height), + .dac_pulse_num(dac_pulse_num), + + .sampler_m_axis_tdata(sampler_m_axis_tdata), + .sampler_m_axis_tvalid(sampler_m_axis_tvalid), + + .adc_pulse_period(adc_pulse_period), + .adc_pulse_num(adc_pulse_num), + + .dac_pulse_width(dac_pulse_width), + .dac_pulse_period(dac_pulse_period), + .dac_pulse_height(dac_pulse_height), + .dac_pulse_num(dac_pulse_num), + + .dac_start(dac_start), + .dac_rst(dac_rst), + + .m_axis_read_data(dma_read_data) + ); + +endmodule : tb_controller_wrapper_axil diff --git a/designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv b/designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv index b2408c0..e632e88 100644 --- a/designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv +++ b/designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv @@ -47,6 +47,7 @@ module reflectometer_and_dma_wrapper axi4l_if.slave s_axil, axi_if.master m_axi, + // todo axis_if.master m_axis_read_data, // DAC