baulin.fa/reflectometer_fpga_project
2
0
Fork 0
Code Issues 4 Pull Requests Actions Packages Projects Releases Wiki Activity

sampler fix: made it beauty

Browse Source
This commit is contained in:
otroubi
2026-06-17 19:54:19 +03:00
parent 29e1541ffb
commit 45a57d57e4
1 changed files with 65 additions and 69 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
rtl/sampler/src/sampler.sv
View File

@ -18,10 +18,10 @@ module sampler
output logic m_axis_tvalid,
output logic request
);
(* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
(* MARK_DEBUG="true" *) logic out_of_range_reg;
(* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
(* MARK_DEBUG="true" *) logic enable, enable_d;
logic [DATA_WIDTH-1:0] data_converted;
logic out_of_range_reg;
logic [31:0] smp_num_reg, cnt_smp_num;
logic enable;
generate
if (PROCESS_MODE) begin
@ -53,9 +53,8 @@ module sampler
end
endgenerate
(* MARK_DEBUG="true" *) logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
(* MARK_DEBUG="true" *) logic buffer_ready;
logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
logic buffer_ready;
logic [$clog2(PACK_FACTOR):0] cnt;
generate
@ -87,8 +86,7 @@ module sampler
if (!out_of_range_reg) begin
buffer <= data_converted;
end
end
else begin
end else begin
cnt_smp_num <= '0;
buffer_ready <= 0;
enable <= 0;
@ -101,14 +99,13 @@ module sampler
always @(posedge clk_in) begin
if (rst) begin
buffer <= '0;
cnt <= '0; //
cnt <= '0;
buffer_ready <= 0;
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
request <= 0;
end
else begin
end else begin
buffer_ready <= 0;
if (!enable) begin
if (request && done) begin
@ -133,8 +130,7 @@ module sampler
cnt <= cnt + 1;
end
end
end
else begin
end else begin
cnt_smp_num <= '0;
buffer_ready <= 0;
enable <= 0;