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rtl: sampler modified

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otroubi
2026-07-07 14:47:34 +03:00
parent 45a57d57e4
commit 287d855df4
1 changed files with 58 additions and 105 deletions
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157
rtl/sampler/src/sampler.sv
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@ -5,23 +5,23 @@ module sampler
parameter DATA_WIDTH = 12, parameter DATA_WIDTH = 12,
parameter PACK_FACTOR = 1, parameter PACK_FACTOR = 1,
parameter PROCESS_MODE = 0 parameter PROCESS_MODE = 0
) ) (
(
input clk_in, input clk_in,
input rst, input rst,
input [DATA_WIDTH-1:0] data_in, input [DATA_WIDTH-1:0] data_in,
input out_of_range, input out_of_range,
input [31:0] smp_num, input [31:0] smp_num,
input done, input request,
output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata, output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
output logic m_axis_tvalid, output logic m_axis_tvalid,
output logic request output logic done
); );
logic [DATA_WIDTH-1:0] data_converted; logic [DATA_WIDTH-1:0] data_converted;
logic out_of_range_reg;
logic [31:0] smp_num_reg, cnt_smp_num; logic [31:0] smp_num_reg, cnt_smp_num;
logic enable; logic synced;
logic [31:0] pack_cnt;
generate generate
if (PROCESS_MODE) begin if (PROCESS_MODE) begin
@ -29,120 +29,73 @@ module sampler
always @(posedge clk_in) begin always @(posedge clk_in) begin
if (rst) begin if (rst) begin
data_converted <= '0; data_converted <= '0;
out_of_range_reg <= 0;
end end
else begin else begin
out_of_range_reg <= out_of_range; if (out_of_range) begin
if (data_in == {1'b1, {(DATA_WIDTH-1){1'b0}}}) if (data_in[DATA_WIDTH-1]==1'b1) data_converted <= {1'b1, {(DATA_WIDTH-2){1'b0}}};
data_converted <= data_in; else if (data_in[DATA_WIDTH-1]==1'b0) data_converted <= {1'b0, {(DATA_WIDTH-2){1'b1}}};
else end else begin
data_converted <= data_in[DATA_WIDTH-1] ?{1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)}:data_in; if (data_in == {1'b1, {(DATA_WIDTH-1){1'b0}}})
data_converted <= data_in;
else
data_converted <= data_in[DATA_WIDTH-1] ?{1'b1, (~data_in[DATA_WIDTH-2:0] + 1'b1)}:data_in;
end
end end
end end
end else begin end else begin
always @(posedge clk_in) begin always @(posedge clk_in) begin
if (rst) begin if (rst) begin
data_converted <= '0; data_converted <= '0;
out_of_range_reg <= 0; end else begin
end if (out_of_range) begin
else begin if (data_in[DATA_WIDTH-1]==1'b1) data_converted <= '1;
out_of_range_reg <= out_of_range; else if (data_in[DATA_WIDTH-1]==1'b0) data_converted <= '0;
data_converted <= data_in; end else begin
data_converted <= data_in;
end
end end
end end
end end
endgenerate endgenerate
logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer; always @(posedge clk_in) begin
logic buffer_ready; if (rst) begin
logic [$clog2(PACK_FACTOR):0] cnt; m_axis_tdata <= '0;
m_axis_tvalid <= 0;
generate cnt_smp_num <= '0;
if (PACK_FACTOR == 1) begin smp_num_reg <= '0;
always @(posedge clk_in) begin pack_cnt <= '0;
if (rst) begin synced <= 0;
buffer <= '0; done <= 0;
buffer_ready <= 0;
cnt_smp_num <= '0;
smp_num_reg <= '0;
enable <= 0;
request <= 0;
end
else begin
buffer_ready <= 0;
if (!enable) begin
if (request && done) begin
enable <= 1;
request <= 0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end else begin
request <= 1;
end
end else begin
if (cnt_smp_num != smp_num_reg) begin
cnt_smp_num <= cnt_smp_num +1;
buffer_ready <= 1;
if (!out_of_range_reg) begin
buffer <= data_converted;
end
end else begin
cnt_smp_num <= '0;
buffer_ready <= 0;
enable <= 0;
buffer <= '0;
end
end
end
end
end else begin end else begin
always @(posedge clk_in) begin m_axis_tvalid <= 0;
if (rst) begin if (!synced) begin
buffer <= '0; if (done && request) begin
cnt <= '0; synced <= 1;
buffer_ready <= 0; done <= 0;
cnt_smp_num <= '0; cnt_smp_num <= 0;
smp_num_reg <= '0; smp_num_reg <= smp_num;
enable <= 0;
request <= 0;
end else begin end else begin
buffer_ready <= 0; done <= 1;
if (!enable) begin end
if (request && done) begin end else begin
enable <= 1; if (cnt_smp_num != smp_num_reg) begin
request <= 0; cnt_smp_num <= cnt_smp_num +1;
cnt_smp_num <= 0; m_axis_tdata[pack_cnt*DATA_WIDTH +: DATA_WIDTH] <= data_converted;
smp_num_reg <= smp_num; if (pack_cnt == PACK_FACTOR-1) begin
end else begin pack_cnt <= 0;
request <= 1; m_axis_tvalid <= 1;
end
end else begin end else begin
if (cnt_smp_num != smp_num_reg) begin pack_cnt <= pack_cnt + 1;
cnt_smp_num <= cnt_smp_num +1;
buffer_ready <= 1;
if (!out_of_range_reg) begin
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
if (cnt == PACK_FACTOR-1) begin
cnt <= 0;
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
end
else begin
cnt <= cnt + 1;
end
end
end else begin
cnt_smp_num <= '0;
buffer_ready <= 0;
enable <= 0;
cnt <= 0;
end
end end
end else begin
cnt_smp_num <= '0;
pack_cnt <= '0;
synced <= 0;
done <= 1;
end end
end end
end end
endgenerate end
assign m_axis_tdata = buffer;
assign m_axis_tvalid = buffer_ready;
endmodule endmodule