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tests: add tb to axis_mac project

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This commit is contained in:
Phil
2026-04-14 12:31:21 +03:00
parent c372dcd942
commit 1c654f4e8e
2 changed files with 25 additions and 12 deletions
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3
rtl/ethernet-udp/tests/eth_axis/Makefile
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@ -22,6 +22,9 @@ SYN_FILES += $(sort $(shell find ../../src -type f \( -name '*.v' -o -name '*.sv
XCI_FILES = $(sort $(shell find ../../src -type f -name '*.xci')) XCI_FILES = $(sort $(shell find ../../src -type f -name '*.xci'))
SIM_TOP = tb_mac_test
TB_FILES = test_axis_mac_rx.sv
program: $(PROJECT).bit program: $(PROJECT).bit
echo "open_hw_manager" > program.tcl echo "open_hw_manager" > program.tcl
echo "connect_hw_server" >> program.tcl echo "connect_hw_server" >> program.tcl

34
rtl/ethernet-udp/tests/test_axis_mac_rx.sv → rtl/ethernet-udp/tests/eth_axis/test_axis_mac_rx.sv
View File

@ -11,17 +11,27 @@ module tb_mac_test;
wire gmii_tx_en; wire gmii_tx_en;
wire [7:0] gmii_txd; wire [7:0] gmii_txd;
// rx axis
wire [7:0] m_axis_rx_tdata; wire [7:0] m_axis_rx_tdata;
wire m_axis_rx_tvalid; wire m_axis_rx_tvalid;
reg m_axis_rx_tready = 1'b0; reg m_axis_rx_tready = 1'b0;
wire m_axis_rx_tlast; wire m_axis_rx_tlast;
// tx axis
reg [7:0] s_axis_tx_tdata;
reg s_axis_tx_tvalid;
wire s_axis_tx_tready = 1'b0;
reg s_axis_tx_tlast;
reg send_req;
wire req_ready;
reg [15:0] udp_rec_data_length;
int cnt = 0; int cnt = 0;
// ============================================================
// DUT // DUT
// ============================================================
axis_mac dut ( axis_mac dut (
.rst_n(rst_n), .rst_n(rst_n),
.gmii_tx_clk(gmii_tx_clk), .gmii_tx_clk(gmii_tx_clk),
@ -33,18 +43,22 @@ module tb_mac_test;
.m_axis_rx_tdata(m_axis_rx_tdata), .m_axis_rx_tdata(m_axis_rx_tdata),
.m_axis_rx_tvalid(m_axis_rx_tvalid), .m_axis_rx_tvalid(m_axis_rx_tvalid),
.m_axis_rx_tready(m_axis_rx_tready), .m_axis_rx_tready(m_axis_rx_tready),
.m_axis_rx_tlast(m_axis_rx_tlast) .m_axis_rx_tlast(m_axis_rx_tlast),
.s_axis_tx_tdata(s_axis_tx_tdata),
.s_axis_tx_tvalid(s_axis_tx_tvalid),
.s_axis_tx_tready(s_axis_tx_tready),
.s_axis_tx_tlast(s_axis_tx_tlast),
.send_req(send_req),
.req_ready(req_ready),
.udp_rec_data_length(udp_rec_data_length)
); );
// ============================================================
// Clocks // Clocks
// ============================================================
always #4 gmii_rx_clk = ~gmii_rx_clk; always #4 gmii_rx_clk = ~gmii_rx_clk;
always #4 gmii_tx_clk = ~gmii_tx_clk; always #4 gmii_tx_clk = ~gmii_tx_clk;
// ============================================================
// Helpers // Helpers
// ============================================================
task automatic gmii_idle; task automatic gmii_idle;
input integer cycles; input integer cycles;
integer i; integer i;
@ -111,9 +125,7 @@ module tb_mac_test;
end end
endtask endtask
// ============================================================
// Monitor AXIS RX // Monitor AXIS RX
// ============================================================
always @(posedge gmii_rx_clk) begin always @(posedge gmii_rx_clk) begin
if (m_axis_rx_tvalid && m_axis_rx_tready) begin if (m_axis_rx_tvalid && m_axis_rx_tready) begin
$write("%02x ", m_axis_rx_tdata); $write("%02x ", m_axis_rx_tdata);
@ -126,9 +138,7 @@ module tb_mac_test;
end else m_axis_rx_tready = 1'b0; end else m_axis_rx_tready = 1'b0;
end end
// ============================================================
// Test sequence // Test sequence
// ============================================================
integer i; integer i;
initial begin initial begin
@ -242,7 +252,7 @@ module tb_mac_test;
send_gmii_frame_mem(66); send_gmii_frame_mem(66);
gmii_idle(200); gmii_idle(200);
$display("\nSimulation done"); $display("\nSimulation done OK");
$finish; $finish;
end end