diff --git a/rtl/ethernet-udp/tests/eth_axis/Makefile b/rtl/ethernet-udp/tests/eth_axis/Makefile
index 9fbcca1..64d963b 100644
--- a/rtl/ethernet-udp/tests/eth_axis/Makefile
+++ b/rtl/ethernet-udp/tests/eth_axis/Makefile
@@ -22,6 +22,9 @@ SYN_FILES += $(sort $(shell find ../../src -type f \( -name '*.v' -o -name '*.sv
 
 XCI_FILES = $(sort $(shell find ../../src -type f -name '*.xci'))
 
+SIM_TOP = tb_mac_test
+TB_FILES = test_axis_mac_rx.sv
+
 program: $(PROJECT).bit
 	echo "open_hw_manager" > program.tcl
 	echo "connect_hw_server" >> program.tcl
diff --git a/rtl/ethernet-udp/tests/test_axis_mac_rx.sv b/rtl/ethernet-udp/tests/eth_axis/test_axis_mac_rx.sv
similarity index 88%
rename from rtl/ethernet-udp/tests/test_axis_mac_rx.sv
rename to rtl/ethernet-udp/tests/eth_axis/test_axis_mac_rx.sv
index 27dd30a..2305530 100644
--- a/rtl/ethernet-udp/tests/test_axis_mac_rx.sv
+++ b/rtl/ethernet-udp/tests/eth_axis/test_axis_mac_rx.sv
@@ -11,17 +11,27 @@ module tb_mac_test;
     wire        gmii_tx_en;
     wire [7:0]  gmii_txd;
 
+    // rx axis
     wire [7:0]  m_axis_rx_tdata;
     wire        m_axis_rx_tvalid;
     reg         m_axis_rx_tready = 1'b0;
     wire        m_axis_rx_tlast;
+
+    // tx axis
+    reg  [7:0]  s_axis_tx_tdata;
+    reg         s_axis_tx_tvalid;
+    wire        s_axis_tx_tready = 1'b0;
+    reg         s_axis_tx_tlast;
+
+    reg send_req;
+    wire req_ready;
+
+    reg [15:0] udp_rec_data_length;
     
     int cnt = 0;
 
 
-    // ============================================================
     // DUT
-    // ============================================================
     axis_mac dut (
         .rst_n(rst_n),
         .gmii_tx_clk(gmii_tx_clk),
@@ -33,18 +43,22 @@ module tb_mac_test;
         .m_axis_rx_tdata(m_axis_rx_tdata),
         .m_axis_rx_tvalid(m_axis_rx_tvalid),
         .m_axis_rx_tready(m_axis_rx_tready),
-        .m_axis_rx_tlast(m_axis_rx_tlast)
+        .m_axis_rx_tlast(m_axis_rx_tlast),
+        .s_axis_tx_tdata(s_axis_tx_tdata),
+        .s_axis_tx_tvalid(s_axis_tx_tvalid),
+        .s_axis_tx_tready(s_axis_tx_tready),
+        .s_axis_tx_tlast(s_axis_tx_tlast),
+        .send_req(send_req),
+        .req_ready(req_ready),
+        .udp_rec_data_length(udp_rec_data_length)
+
     );
 
-    // ============================================================
     // Clocks
-    // ============================================================
     always #4 gmii_rx_clk = ~gmii_rx_clk;
     always #4 gmii_tx_clk = ~gmii_tx_clk;
 
-    // ============================================================
     // Helpers
-    // ============================================================
     task automatic gmii_idle;
         input integer cycles;
         integer i;
@@ -111,9 +125,7 @@ module tb_mac_test;
         end
     endtask
 
-    // ============================================================
     // Monitor AXIS RX
-    // ============================================================
     always @(posedge gmii_rx_clk) begin
         if (m_axis_rx_tvalid && m_axis_rx_tready) begin
             $write("%02x ", m_axis_rx_tdata);
@@ -126,9 +138,7 @@ module tb_mac_test;
         end else m_axis_rx_tready = 1'b0;
     end
 
-    // ============================================================
     // Test sequence
-    // ============================================================
     integer i;
 
     initial begin
@@ -242,7 +252,7 @@ module tb_mac_test;
         send_gmii_frame_mem(66);
         gmii_idle(200);
 
-        $display("\nSimulation done");
+        $display("\nSimulation done OK");
         $finish;
     end