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infra: update makefile

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Phil
2026-07-07 17:45:32 +03:00
parent 8e5b3929ac
commit 177c7d0bc2
1 changed files with 11 additions and 7 deletions
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18
rtl/accum/tests/Makefile
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@ -13,20 +13,24 @@ FPGA_ARCH = artix7
RTL_DIR = ../src RTL_DIR = ../src
# Simulation settings
SIM_TOP = tb_accumulator_top
SIM_RUNTIME ?= 10000 us
include ../../../scripts/vivado.mk # Design sources only
SYN_FILES += $(filter-out %_tb.sv,$(sort $(shell find $(RTL_DIR) -type f -name '*.v' -o -type f -name '*.sv')))
SYN_FILES += $(sort $(shell find ../src -type f \( -name '*.v' -o -name '*.sv' \))) # Testbench sources. Vivado puts these into "sim_1", Questa compiles them into "work".
TB_FILES += out_axis_fifo_tb.sv
TB_FILES += accum_full_tb.sv
XCI_FILES = $(sort $(shell find ../src -type f -name '*.xci')) XCI_FILES = $(sort $(shell find $(RTL_DIR) -type f -name '*.xci'))
XDC_FILES += ../../../constraints/ax7a035b.xdc XDC_FILES += ../../../constraints/ax7a035b.xdc
XDC_FILES += test_timing.xdc XDC_FILES += test_timing.xdc
SYN_FILES += out_axis_fifo_tb.sv include ../../../scripts/vivado.mk
SYN_FILES += accum_full_tb.sv include ../../../scripts/questa.mk
SIM_TOP = tb_accumulator_top
program: $(PROJECT).bit program: $(PROJECT).bit
echo "open_hw_manager" > program.tcl echo "open_hw_manager" > program.tcl