diff --git a/rtl/accum/tests/Makefile b/rtl/accum/tests/Makefile
index 45f5626..e6d2005 100644
--- a/rtl/accum/tests/Makefile
+++ b/rtl/accum/tests/Makefile
@@ -13,20 +13,24 @@ FPGA_ARCH = artix7
 
 RTL_DIR = ../src
 
+# Simulation settings
+SIM_TOP     = tb_accumulator_top
+SIM_RUNTIME ?= 10000 us
 
-include ../../../scripts/vivado.mk
+# Design sources only
+SYN_FILES += $(filter-out %_tb.sv,$(sort $(shell find $(RTL_DIR) -type f -name '*.v' -o -type f -name '*.sv')))
 
-SYN_FILES += $(sort $(shell find ../src -type f \( -name '*.v' -o -name '*.sv' \)))
+# Testbench sources. Vivado puts these into "sim_1", Questa compiles them into "work".
+TB_FILES += out_axis_fifo_tb.sv
+TB_FILES += accum_full_tb.sv
 
-XCI_FILES = $(sort $(shell find ../src -type f -name '*.xci'))
+XCI_FILES = $(sort $(shell find $(RTL_DIR) -type f -name '*.xci'))
 
 XDC_FILES += ../../../constraints/ax7a035b.xdc
 XDC_FILES += test_timing.xdc
 
-SYN_FILES += out_axis_fifo_tb.sv
-SYN_FILES += accum_full_tb.sv
-SIM_TOP = tb_accumulator_top
-
+include ../../../scripts/vivado.mk
+include ../../../scripts/questa.mk
 
 program: $(PROJECT).bit
 	echo "open_hw_manager" > program.tcl