baulin.fa/reflectometer_fpga_project
2
0
Fork 0
Code Issues 4 Pull Requests Actions Packages Projects Releases Wiki Activity

fix: port names in axi4l reg_map

Browse Source
This commit is contained in:
Phil
2026-07-10 17:51:30 +03:00
parent 1ba94690d5
commit 126b66e4f5
2 changed files with 9 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rtl/controller/src/axi4l_reg_map_controller.sv
View File

@ -35,7 +35,7 @@ module axi4l_reg_map_controller #(
input logic [7:0] busy_i,
input logic [7:0] error_code_i
);
import axi4l_reg_map_example_pkg::*;
import axi4l_reg_map_controller_pkg::*;
localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS;
logic [N_REGS-1:0][31:0] reg_i;

18
rtl/controller/src/axi4l_reg_map_controller_pkg.sv
View File

@ -42,17 +42,17 @@ AXI write descriptor input and AXI write descriptor status output configuration
localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{
// REG_CONTROL
'{
REG_BIT_W1S,
REG_BIT_W1S,
REG_BIT_W1S,
REG_BIT_W1S,
0 : REG_BIT_W1S,
1 : REG_BIT_W1S,
2 : REG_BIT_W1S,
3 : REG_BIT_W1S,
default: REG_BIT_RSVD
},
// REG_STATUS
'{
REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
0 : REG_BIT_RO, 1 : REG_BIT_RO, 2 : REG_BIT_RO, 3 : REG_BIT_RO,
4 : REG_BIT_RO, 5 : REG_BIT_RO, 6 : REG_BIT_RO, 7 : REG_BIT_RO,
default: REG_BIT_RSVD
},
@ -76,10 +76,8 @@ AXI write descriptor input and AXI write descriptor status output configuration
// REG_ERROR
'{
REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
default: REG_BIT_RSVD
}
default: REG_BIT_RO
},
// REG_DESC_READ_ADDR
'{default: REG_BIT_RW},