From 126b66e4f5797cb880a643b95592dcb50e45b909 Mon Sep 17 00:00:00 2001 From: Phil Date: Fri, 10 Jul 2026 17:51:30 +0300 Subject: [PATCH] fix: port names in axi4l reg_map --- rtl/controller/src/axi4l_reg_map_controller.sv | 2 +- .../src/axi4l_reg_map_controller_pkg.sv | 18 ++++++++---------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/rtl/controller/src/axi4l_reg_map_controller.sv b/rtl/controller/src/axi4l_reg_map_controller.sv index 35ab25b..9c8e270 100644 --- a/rtl/controller/src/axi4l_reg_map_controller.sv +++ b/rtl/controller/src/axi4l_reg_map_controller.sv @@ -35,7 +35,7 @@ module axi4l_reg_map_controller #( input logic [7:0] busy_i, input logic [7:0] error_code_i ); - import axi4l_reg_map_example_pkg::*; + import axi4l_reg_map_controller_pkg::*; localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS; logic [N_REGS-1:0][31:0] reg_i; diff --git a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv index cb4bd1d..0e6ffb1 100644 --- a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv +++ b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv @@ -42,17 +42,17 @@ AXI write descriptor input and AXI write descriptor status output configuration localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{ // REG_CONTROL '{ - REG_BIT_W1S, - REG_BIT_W1S, - REG_BIT_W1S, - REG_BIT_W1S, + 0 : REG_BIT_W1S, + 1 : REG_BIT_W1S, + 2 : REG_BIT_W1S, + 3 : REG_BIT_W1S, default: REG_BIT_RSVD }, // REG_STATUS '{ - REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, - REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, + 0 : REG_BIT_RO, 1 : REG_BIT_RO, 2 : REG_BIT_RO, 3 : REG_BIT_RO, + 4 : REG_BIT_RO, 5 : REG_BIT_RO, 6 : REG_BIT_RO, 7 : REG_BIT_RO, default: REG_BIT_RSVD }, @@ -76,10 +76,8 @@ AXI write descriptor input and AXI write descriptor status output configuration // REG_ERROR '{ - REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, - REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, - default: REG_BIT_RSVD - } + default: REG_BIT_RO + }, // REG_DESC_READ_ADDR '{default: REG_BIT_RW},