fix: port names in axi4l reg_map

2026-07-10 17:51:30 +03:00
parent 1ba94690d5
commit 126b66e4f5
2 changed files with 9 additions and 11 deletions
--- a/rtl/controller/src/axi4l_reg_map_controller.sv
+++ b/rtl/controller/src/axi4l_reg_map_controller.sv
@ -35,7 +35,7 @@ module axi4l_reg_map_controller #(
  input  logic [7:0]  busy_i,
  input  logic [7:0]  error_code_i
 );
-  import axi4l_reg_map_example_pkg::*;
+  import axi4l_reg_map_controller_pkg::*;
  localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS;

  logic [N_REGS-1:0][31:0] reg_i;