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add: vrtual DAC & ADC subsystem for TB

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fix: makefile
upd: clocking wiz IP
This commit is contained in:
babintsev.lv
2026-07-10 14:15:49 +03:00
parent 64f94a90e6
commit 0ba25a3541
6 changed files with 223 additions and 161 deletions
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45
designs/reflectometer_base/tb_reflectometer.sv
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@ -52,29 +52,41 @@ module tb_reflectometer;
logic s_axis_accumulator_tready = 1'b0;
wire s_axis_accumulator_tlast;
// DAC интерфейс
wire clk_dac;
wire dac_wrt;
wire [DAC_DATA_WIDTH-1:0] dac_data;
wire clk_dac;
wire dac_wrt;
wire [DAC_DATA_WIDTH-1:0] dac_data;
// ADC интерфейс
wire clk_adc;
logic adc_otr = 1'b0;
logic [ADC_DATA_WIDTH-1:0] adc_data = '0;
wire clk_adc;
wire adc_otr = 1'b0;
wire [ADC_DATA_WIDTH-1:0] adc_data = '0;
// Интерфейс хендшейка с MAC-PHY
wire send_request;
logic request_ready = 1'b0;
// Сигналы ЦАП и АЦП
real signal_voltage;
//------------------------------------------------------------
// Virtual DAC
//------------------------------------------------------------
virtual_dac_model #( // default voltage range is +/- 5V
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
) virtual_dac (
.clk_i(clk_dac),
.wrt_i(dac_wrt),
.data_i(dac_data),
.voltage_o(signal_voltage)
);
//------------------------------------------------------------
// Virtual ADC
//------------------------------------------------------------
//------------------------------------------------------------
// Virtual conductor
//------------------------------------------------------------
virtual_adc_model #( // default voltage range is +/- 5V
.ADC_DATA_WIDTH(ADC_DATA_WIDTH)
) virtual_adc (
.clk_i(clk_adc),
.voltage_i(signal_voltage),
.otr_o(adc_otr),
.data_o(adc_data)
);
//------------------------------------------------------------
// Statistics monitor
//------------------------------------------------------------
@ -82,7 +94,7 @@ module tb_reflectometer;
//------------------------------------------------------------
// Config handler
//------------------------------------------------------------
//------------------------------------------------------------
// DUT
//------------------------------------------------------------
@ -230,8 +242,13 @@ module tb_reflectometer;
initial begin
$display("[TB] Tests start");
// Инициализация
rst_n = 1;
wait(mmcm_locked === 1'b1);
#10000;
#100;
$display("[TB] ALL PASSED");
$finish;