257 lines
8.8 KiB
Systemverilog
257 lines
8.8 KiB
Systemverilog
`timescale 1ns / 1ps
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module tb_reflectometer;
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//------------------------------------------------------------
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// Параметры
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//------------------------------------------------------------
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localparam int unsigned DAC_DATA_WIDTH = 14;
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localparam int unsigned ADC_DATA_WIDTH = 12;
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localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero
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localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero
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localparam PACK_FACTOR = 1; // not used in TB
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localparam PROCESS_MODE = 0; // 0 - uint, 1 - int
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localparam ACCUM_WIDTH = 32; // accumulator number bit witdth
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localparam N_MAX = 4096; // max value of windows to average by experiments
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localparam WINDOW_SIZE = 65; // fixed subwindow size to average by time
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localparam PACKET_SIZE = 1024; // bytes per UDP packet
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localparam ZERO_LEVEL = LOGIC_ZERO_LEVEL; // "logic" VS "true"
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localparam CLK_ETH_PHY_PERIOD = 8.000; // 125 MHz
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localparam CLK_REF_PERIOD = 5.000; // 200 MHz
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//------------------------------------------------------------
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// Тактовые сигналы и сброс
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//------------------------------------------------------------
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logic clk_ref = 1'b0; // 200 MHz
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logic clk_eth_phy = 1'b0; // common for RX & TX
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logic rst_n = 1'b0;
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//------------------------------------------------------------
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// Управление и конфиг
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Входы
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Выходы
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//------------------------------------------------------------
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wire mmcm_locked;
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//------------------------------------------------------------
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// Внутренние сигналы тестбенча
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//------------------------------------------------------------
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// AXI-S интерфейс для управления
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logic [7:0] m_axis_control_tdata = 8'b0;
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logic m_axis_control_tvalid = 1'b0;
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wire m_axis_control_tready;
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logic m_axis_control_tlast = 1'b0;
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// AXI-S интерфейс для данных
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wire [7:0] s_axis_accumulator_tdata;
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wire s_axis_accumulator_tvalid;
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logic s_axis_accumulator_tready = 1'b0;
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wire s_axis_accumulator_tlast;
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// DAC интерфейс
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wire clk_dac;
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wire dac_wrt;
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wire [DAC_DATA_WIDTH-1:0] dac_data;
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// ADC интерфейс
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wire clk_adc;
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wire adc_otr = 1'b0;
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wire [ADC_DATA_WIDTH-1:0] adc_data = '0;
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// Интерфейс хендшейка с MAC-PHY
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wire send_request;
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logic request_ready = 1'b0;
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// Сигналы ЦАП и АЦП
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real signal_voltage;
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//------------------------------------------------------------
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// Virtual DAC
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//------------------------------------------------------------
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virtual_dac_model #( // default voltage range is +/- 5V
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
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) virtual_dac (
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.clk_i(clk_dac),
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.wrt_i(dac_wrt),
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.data_i(dac_data),
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.voltage_o(signal_voltage)
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);
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//------------------------------------------------------------
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// Virtual ADC
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//------------------------------------------------------------
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virtual_adc_model #( // default voltage range is +/- 5V
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.ADC_DATA_WIDTH(ADC_DATA_WIDTH)
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) virtual_adc (
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.clk_i(clk_adc),
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.voltage_i(signal_voltage),
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.otr_o(adc_otr),
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.data_o(adc_data)
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);
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//------------------------------------------------------------
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// Statistics monitor
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Config handler
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//------------------------------------------------------------
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//------------------------------------------------------------
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// DUT
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//------------------------------------------------------------
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reflectometer_top #(
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
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.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
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.PACK_FACTOR(PACK_FACTOR),
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.PROCESS_MODE(PROCESS_MODE),
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.ZERO_LEVEL(ZERO_LEVEL),
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.ACCUM_WIDTH(ACCUM_WIDTH),
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.N_MAX(N_MAX),
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.WINDOW_SIZE(WINDOW_SIZE),
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.PACKET_SIZE(PACKET_SIZE)
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) DUT (
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.clk_in(clk_ref),
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.rst_n(rst_n),
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.locked(mmcm_locked),
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// Accumulator AXI-S bus
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.clk_m_axis(clk_eth_phy), // GMII PHY RX clock
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.m_axis_tdata(s_axis_accumulator_tdata),
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.m_axis_tvalid(s_axis_accumulator_tvalid),
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.m_axis_tready(s_axis_accumulator_tready),
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.m_axis_tlast(s_axis_accumulator_tlast),
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// Control AXI-S bus
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.clk_s_axis(clk_eth_phy), // GMII PHY TX clock
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.s_axis__tdata(maxis_control_tdata),
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.s_axis_tvalid(maxis_control_tvalid),
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.s_axis_tlast(maxis_control_tlast),
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.s_axis_tready(maxis_control_tready),
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// RTL-MAC handshake
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.request_ready(request_ready),
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.send_request(send_request),
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// DAC
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.dac_clk_o(clk_dac),
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.dac_data(dac_data),
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.dac_wrt(dac_wrt),
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// ADC
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.adc_clk_o(clk_adc),
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.adc_data(adc_data),
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.adc_otr(adc_otr)
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);
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//------------------------------------------------------------
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// Тактовые сигналы
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//------------------------------------------------------------
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initial begin
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forever #(CLK_REF_PERIOD/2) clk_ref = ~clk_ref;
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end
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initial begin
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forever #(CLK_ETH_PHY_PERIOD/2) clk_eth_phy = ~clk_eth_phy;
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end
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//------------------------------------------------------------
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// Таски для тестирования
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//------------------------------------------------------------
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// task automatic axis_send_byte(
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// ref logic clk,
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// input logic [7:0] data,
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// input logic last,
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// ref logic tvalid,
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// ref logic [7:0] tdata,
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// ref logic tlast,
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// input logic tready
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// );
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// @(posedge clk);
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// tdata <= data;
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// tlast <= last;
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// tvalid <= 1'b1;
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// // Ждем готовности приемника
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// wait(tready === 1'b1);
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// @(posedge clk);
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// tvalid <= 1'b0;
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// tlast <= 1'b0;
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// endtask
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// task automatic dut_soft_reset();
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// axis_send_byte(
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// .clk(clk_eth_phy_rx),
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// .data(8'b00001111),
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// .last(1'b1),
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// .tvalid(m_axis_rx_tvalid),
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// .tdata(m_axis_rx_tdata),
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// .tlast(m_axis_rx_tlast),
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// .tready(m_axis_rx_tready)
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// );
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// endtask
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// task automatic dut_start();
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// axis_send_byte(
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// .clk(clk_eth_phy_rx),
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// .data(8'b11110000),
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// .last(1'b1),
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// .tvalid(m_axis_rx_tvalid),
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// .tdata(m_axis_rx_tdata),
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// .tlast(m_axis_rx_tlast),
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// .tready(m_axis_rx_tready)
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// );
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// endtask
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// task automatic dut_send_config(
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// input logic [127:0] ctrl_config
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// );
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// // команда set_data
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// axis_send_byte(
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// .clk(clk_eth_phy_rx),
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// .data(8'b10001000),
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// .last(1'b0),
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// .tvalid(m_axis_rx_tvalid),
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// .tdata(m_axis_rx_tdata),
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// .tlast(m_axis_rx_tlast),
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// .tready(m_axis_rx_tready)
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// );
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// // config burst
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// for (int i = 0; i < 16; i++) begin
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// logic [7:0] byte_to_send;
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// logic is_last;
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// // get byte
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// byte_to_send = ctrl_config[i*8 +: 8];
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// // tlast for last byte
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// is_last = (i == 15);
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// axis_send_byte(
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// .clk(clk_eth_phy_rx),
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// .data(byte_to_send),
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// .last(is_last),
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// .tvalid(m_axis_rx_tvalid),
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// .tdata(m_axis_rx_tdata),
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// .tlast(m_axis_rx_tlast),
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// .tready(m_axis_rx_tready)
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// );
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// end
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// endtask
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//------------------------------------------------------------
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// ОСНОВНОЙ ПРОЦЕСС ТЕСТИРОВАНИЯ
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//------------------------------------------------------------
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initial begin
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$display("[TB] Tests start");
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// Инициализация
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rst_n = 1;
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wait(mmcm_locked === 1'b1);
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#100;
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$display("[TB] ALL PASSED");
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$finish;
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end
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endmodule
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