rtl: add axis eth rx prototype

This commit is contained in:
Phil
2026-04-01 11:44:46 +03:00
parent a1386fc8a4
commit 0b9fb64193
4 changed files with 294 additions and 18 deletions

View File

@ -10,7 +10,7 @@ module mac_rx_top
input rst_n,
input rx_dv,
input [7:0] mac_rx_datain,
(* MARK_DEBUG="true" *)input [7:0] mac_rx_datain,
input [31:0] local_ip_addr,
input [47:0] local_mac_addr,
@ -21,14 +21,14 @@ module mac_rx_top
output [47:0] arp_rec_source_mac_addr,
output [7:0] udp_rec_ram_rdata ,
input [10:0] udp_rec_ram_read_addr,
output [15:0] udp_rec_data_length,
output udp_rec_data_valid,
(* MARK_DEBUG="true" *)output [7:0] udp_rec_ram_rdata ,
(* MARK_DEBUG="true" *)input [10:0] udp_rec_ram_read_addr,
(* MARK_DEBUG="true" *)output [15:0] udp_rec_data_length,
(* MARK_DEBUG="true" *)output udp_rec_data_valid,
output [7:0] mac_rx_dataout,
output [15:0] upper_layer_data_length ,
output [15:0] ip_total_data_length,
(* MARK_DEBUG="true" *)output [7:0] mac_rx_dataout,
(* MARK_DEBUG="true" *)output [15:0] upper_layer_data_length ,
(* MARK_DEBUG="true" *)output [15:0] ip_total_data_length,
output icmp_rx_req,
output icmp_rev_error,

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@ -24,13 +24,13 @@ module mac_tx_top
input arp_request_req,
input [7:0] ram_wr_data,
input ram_wr_en,
input udp_tx_req,
output udp_ram_data_req,
input [15:0] udp_send_data_length,
output udp_tx_end,
output almost_full,
(* MARK_DEBUG="true" *)input [7:0] ram_wr_data,
(* MARK_DEBUG="true" *)input ram_wr_en,
(* MARK_DEBUG="true" *)input udp_tx_req,
(* MARK_DEBUG="true" *)output udp_ram_data_req,
(* MARK_DEBUG="true" *)input [15:0] udp_send_data_length,
(* MARK_DEBUG="true" *)output udp_tx_end,
(* MARK_DEBUG="true" *)output almost_full,
output upper_data_req,
input icmp_tx_ready,
@ -40,9 +40,9 @@ module mac_tx_top
output icmp_tx_ack,
input [15:0] icmp_send_data_length,
output mac_data_valid,
output mac_send_end,
output [7:0] mac_tx_data
(* MARK_DEBUG="true" *)output mac_data_valid,
(* MARK_DEBUG="true" *)output mac_send_end,
(* MARK_DEBUG="true" *)output [7:0] mac_tx_data
) ;