rtl: add axis eth rx prototype
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@ -10,7 +10,7 @@ module mac_rx_top
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input rst_n,
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input rx_dv,
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input [7:0] mac_rx_datain,
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(* MARK_DEBUG="true" *)input [7:0] mac_rx_datain,
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input [31:0] local_ip_addr,
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input [47:0] local_mac_addr,
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@ -21,14 +21,14 @@ module mac_rx_top
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output [47:0] arp_rec_source_mac_addr,
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output [7:0] udp_rec_ram_rdata ,
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input [10:0] udp_rec_ram_read_addr,
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output [15:0] udp_rec_data_length,
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output udp_rec_data_valid,
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(* MARK_DEBUG="true" *)output [7:0] udp_rec_ram_rdata ,
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(* MARK_DEBUG="true" *)input [10:0] udp_rec_ram_read_addr,
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(* MARK_DEBUG="true" *)output [15:0] udp_rec_data_length,
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(* MARK_DEBUG="true" *)output udp_rec_data_valid,
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output [7:0] mac_rx_dataout,
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output [15:0] upper_layer_data_length ,
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output [15:0] ip_total_data_length,
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(* MARK_DEBUG="true" *)output [7:0] mac_rx_dataout,
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(* MARK_DEBUG="true" *)output [15:0] upper_layer_data_length ,
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(* MARK_DEBUG="true" *)output [15:0] ip_total_data_length,
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output icmp_rx_req,
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output icmp_rev_error,
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@ -24,13 +24,13 @@ module mac_tx_top
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input arp_request_req,
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input [7:0] ram_wr_data,
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input ram_wr_en,
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input udp_tx_req,
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output udp_ram_data_req,
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input [15:0] udp_send_data_length,
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output udp_tx_end,
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output almost_full,
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(* MARK_DEBUG="true" *)input [7:0] ram_wr_data,
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(* MARK_DEBUG="true" *)input ram_wr_en,
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(* MARK_DEBUG="true" *)input udp_tx_req,
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(* MARK_DEBUG="true" *)output udp_ram_data_req,
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(* MARK_DEBUG="true" *)input [15:0] udp_send_data_length,
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(* MARK_DEBUG="true" *)output udp_tx_end,
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(* MARK_DEBUG="true" *)output almost_full,
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output upper_data_req,
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input icmp_tx_ready,
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@ -40,9 +40,9 @@ module mac_tx_top
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output icmp_tx_ack,
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input [15:0] icmp_send_data_length,
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output mac_data_valid,
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output mac_send_end,
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output [7:0] mac_tx_data
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(* MARK_DEBUG="true" *)output mac_data_valid,
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(* MARK_DEBUG="true" *)output mac_send_end,
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(* MARK_DEBUG="true" *)output [7:0] mac_tx_data
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) ;
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