project for the test

designs/full_new_reflectometer/src/axi_ram_wrapper.sv

@@ -0,0 +1,67 @@
+module axi_ram_wrapper
+#(
+    parameter int unsigned DATA_WIDTH = 32,
+    parameter int unsigned ADDR_WIDTH = 16,
+    parameter int unsigned ID_WIDTH = 8,
+    parameter int unsigned PIPELINE_OUTPUT = 0
+)
+(
+    input  logic clk,
+    input  logic rst,
+    axi4_if.slave s_axi
+);
+
+logic [1:0] ram_bresp;
+logic [1:0] ram_rresp;
+
+
+assign s_axi.resp.b.resp = axi_pkg::axi_resp_t'(ram_bresp);
+assign s_axi.resp.r.resp = axi_pkg::axi_resp_t'(ram_rresp);
+
+axi_ram
+#(
+    .DATA_WIDTH(DATA_WIDTH),
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .ID_WIDTH(ID_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT)
+) axi_ram_inst
+(
+    .clk(clk),
+    .rst(rst),
+    .s_axi_awid(s_axi.req.aw.id),
+    .s_axi_awaddr(s_axi.req.aw.addr),
+    .s_axi_awlen(s_axi.req.aw.len),
+    .s_axi_awsize(s_axi.req.aw.size),
+    .s_axi_awburst(s_axi.req.aw.burst),
+    .s_axi_awlock(s_axi.req.aw.lock),
+    .s_axi_awcache(s_axi.req.aw.cache),
+    .s_axi_awprot(s_axi.req.aw.prot),
+    .s_axi_awvalid(s_axi.req.aw.valid),
+    .s_axi_awready(s_axi.resp.aw_ready),
+    .s_axi_wdata(s_axi.req.w.data),
+    .s_axi_wstrb(s_axi.req.w.strb),
+    .s_axi_wlast(s_axi.req.w.last),
+    .s_axi_wvalid(s_axi.req.w.valid),
+    .s_axi_wready(s_axi.resp.w_ready),
+    .s_axi_bid(s_axi.resp.b.id),
+    .s_axi_bresp(ram_bresp),
+    .s_axi_bvalid(s_axi.resp.b.valid),
+    .s_axi_bready(s_axi.req.b_ready),
+    .s_axi_arid(s_axi.req.ar.id),
+    .s_axi_araddr(s_axi.req.ar.addr),
+    .s_axi_arlen(s_axi.req.ar.len),
+    .s_axi_arsize(s_axi.req.ar.size),
+    .s_axi_arburst(s_axi.req.ar.burst),
+    .s_axi_arlock(s_axi.req.ar.lock),
+    .s_axi_arcache(s_axi.req.ar.cache),
+    .s_axi_arprot(s_axi.req.ar.prot),
+    .s_axi_arvalid(s_axi.req.ar.valid),
+    .s_axi_arready(s_axi.resp.ar_ready),
+    .s_axi_rid(s_axi.resp.r.id),
+    .s_axi_rdata(s_axi.resp.r.data),
+    .s_axi_rresp(ram_rresp),
+    .s_axi_rlast(s_axi.resp.r.last),
+    .s_axi_rvalid(s_axi.resp.r.valid),
+    .s_axi_rready(s_axi.req.r_ready)
+);
+endmodule

designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv

@@ -18,12 +18,9 @@ module reflectometer_and_dma_wrapper
     parameter int unsigned DATA_W             = 32,
     parameter int unsigned USER_W             = 1,
 
-    parameter int unsigned DAC_DATA_WIDTH     = 12,
-
     parameter int unsigned AXI_DATA_WIDTH     = 32,
 
     parameter int unsigned AXI_STRB_WIDTH     = AXI_DATA_WIDTH / 8,
-    parameter int unsigned AXI_ID_WIDTH       = 8,
     parameter int unsigned AXI_USER_WIDTH     = 1,
     parameter int unsigned AXI_MAX_BURST_LEN  = 16,
 
@@ -46,7 +43,7 @@ module reflectometer_and_dma_wrapper
     output  wire                       locked,
 
     axi4l_if.slave                     s_axil,
-    axi_if.master                      m_axi,
+    axi4_if.master                      m_axi,
     // todo
     axis_if.master                     m_axis_read_data,
 
@@ -167,7 +164,7 @@ module reflectometer_and_dma_wrapper
     ) axi_dma_wrapper_inst
     (
         .clk(ctrl_clk),
-        .rst(!ctrl_rst_n),
+        .rst(!rst_n),
         .s_axis_read_desc(m_axis_desc_read),
         .m_axis_read_desc_status(s_axis_status_read),
         .m_axis_read_data(m_axis_read_data),

designs/full_new_reflectometer/src/reflectometer_ip.sv

@@ -57,7 +57,7 @@ wire workflow_done, processing_done;
     // -------------------------------------------------------------------------
     wire clk_sampler, clk_generator, clk_locked;
 
-    clk_wiz_ctrl_inst clk_wiz_inst
+    clk_wiz_0 clk_wiz_inst
     (
         // Clock in ports
         .clk_200(ctrl_clk),
@@ -67,7 +67,7 @@ wire workflow_done, processing_done;
         .clk_dac_125(clk_generator),
         .clk_dac_125_180(dac_clk_o),
         // Status and control signals               
-        .resetn(rst_n), 
+        .reset(~rst_n), 
         .locked(clk_locked)
     );
 
@@ -221,20 +221,20 @@ wire workflow_done, processing_done;
     );
 
     accumulator_top #(
-        .DATA_WIDTH(DATA_WIDTH),
+        .DATA_WIDTH(ADC_DATA_WIDTH),
         .ACCUM_WIDTH(ACCUM_WIDTH),
         .N_MAX(N_MAX),
         .PACKET_SIZE(PACKET_SIZE),
         .RW_WIDTH(RD_FIFO_WIDTH)
     ) accumulator_top_inst (
         .clk_in(clk_sampler),
-        .rst(!ctrl_rst_n),
+        .rst(adc_rst),
         .s_axis_tdata(sampler_m_axis_tdata),
         .s_axis_tvalid(sampler_m_axis_tvalid),
-        .start(start),
+        .start(adc_start),
         .smp_num(adc_pulse_period),
         .seq_num(adc_pulse_num),
-        .window_size(window_size),
+        .window_size(adc_window_size),
         .dma_clk_in(ctrl_clk),
         .req_ready(1'b1),
         .m_axis_accum(m_axis_accum),

designs/full_new_reflectometer/tests/driver.py

@@ -1,202 +0,0 @@
-import cocotb
-from cocotb.clock import Clock
-from cocotb.triggers import RisingEdge
-from cocotbext.axi import AxiLiteBus, AxiLiteMaster
-from cocotbext.axi import AxiStreamBus, AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
-from cocotbext.axi import AxiBus, AxiRam
-
-from reg_map import *
-
-# Helpers
-
-def reg_addr(reg_index: int) -> int:
-    # AXI-Lite uses byte addresses, 32-bit registers are spaced by 4 bytes.
-    return reg_index * 4
-
-def u32(value: int) -> bytes:
-    return int(value & 0xFFFFFFFF).to_bytes(4, "little")
-
-# Drivers
-
-class Drivers:
-    def __init__(self, dut):
-        self.dut = dut
-
-        cocotb.start_soon(Clock(dut.ctrl_clk, 10, units="ns").start())
-
-        self.axil = AxiLiteMaster(
-            AxiLiteBus.from_prefix(dut, "s_axil"),
-            dut.ctrl_clk,
-            dut.rst
-        )
-
-        self.axis_source = AxiStreamSource(
-            AxiStreamBus.from_prefix(dut, "s_axis_write_data"),
-            dut.ctrl_clk,
-            dut.rst
-        )
-
-        self.axis_sink = AxiStreamSink(
-            AxiStreamBus.from_prefix(dut, "m_axis_read_data"),
-            dut.ctrl_clk,
-            dut.rst
-        )
-
-        self.memory = AxiRam(
-            AxiBus.from_prefix(dut, "m_axi"),
-            dut.ctrl_clk,
-            dut.rst
-        )
-
-    # Reset
-
-    async def reset(self):
-        self.dut.rst.value = 1
-        for _ in range(5):
-            await RisingEdge(self.dut.ctrl_clk)
-
-        self.dut.rst.value = 0
-        for _ in range(5):
-            await RisingEdge(self.dut.ctrl_clk)
-
-    # AxiLite Driver
-
-    async def write_reg(self, reg_index: int, value: int):
-        await self.axil.write(reg_addr(reg_index), u32(value))
-
-    async def read_reg(self, reg_index: int) -> int:
-        resp = await self.axil.read(reg_addr(reg_index), 4)
-        return int.from_bytes(bytes(resp.data), "little")
-    
-    async def pulse_control(self, mask):
-        await self.write_reg( REG_CONTROL, mask )
-
-    # Reflectometer Driver
-
-    async def configure_reflectometer (
-        self,
-        pulse_width,
-        pulse_period,
-        pulse_num,
-        pulse_height,
-        adc_period,
-        window_size
-    ):
-        await self.write_reg(REG_DAC_WIDTH, pulse_width)
-        await self.write_reg(REG_DAC_PERIOD, pulse_period)
-        await self.write_reg(REG_DAC_PULSE_NUM, pulse_num)
-        await self.write_reg(REG_DAC_PULSE_HEIGHT, pulse_height)
-        await self.write_reg(REG_ADC_PERIOD, adc_period)
-        await self.write_reg(REG_WINDOW_SIZE, window_size)
-
-        await self.pulse_control(CTRL_CFG_BUS_VALID)
-
-    async def send_start(self):
-        await self.pulse_control(CTRL_START)
-
-    async def soft_reset(self):
-        await self.pulse_control(CTRL_RST_SOFT)
-
-    async def get_status(self):
-        status = await self.read_reg(REG_STATUS)
-        return {
-        "busy": bool(status & STATUS_BUSY),
-        "processing_done": bool(status & STATUS_PROCESSING_DONE),
-        "desc_read_busy": bool(status & STATUS_DESC_READ_BUSY),
-        "desc_write_busy": bool(status & STATUS_DESC_WRITE_BUSY),
-        "status_read_busy": bool(status & STATUS_STATUS_READ_BUSY),
-        "status_write_busy": bool(status & STATUS_STATUS_WRITE_BUSY),
-        "desc_read_hs": bool(status & STATUS_DESC_READ_HS),
-        "desc_write_hs": bool(status & STATUS_DESC_WRITE_HS),
-        "status_read_hs": bool(status & STATUS_STATUS_READ_HS),
-        "status_write_hs": bool(status & STATUS_STATUS_WRITE_HS)
-        }
-
-    async def wait_status(self, field, value=True):
-
-        while True:
-
-            status = await self.get_status()
-
-            if status[field] == value:
-                return
-
-            await RisingEdge(self.dut.ctrl_clk)
-
-    async def wait_processing_done(self):
-        await self.wait_status("processing_done")
-
-
-    async def wait_finish(self):
-        await self.wait_status("busy", False)
-
-    # DMA Driver
-
-    async def send_desc_write(self, addr, length_tag):
-
-        await self.write_reg(REG_DESC_WRITE_ADDR, addr)
-        await self.write_reg(REG_DESC_WRITE_LEN_AND_TAG, length_tag)
-        await self.pulse_control(CTRL_SEND_DESC_WRITE)
-
-    async def send_desc_read(self, addr, length, config):
-
-        await self.write_reg(REG_DESC_READ_ADDR, addr)
-        await self.write_reg(REG_DESC_READ_LEN, length)
-        await self.write_reg(REG_DESC_READ_CONFIG, config)
-        await self.pulse_control( CTRL_SEND_DESC_READ)
-
-    async def take_status_write(self):
-        await self.pulse_control(CTRL_TAKE_STATUS_WRITE)
-
-        return (
-            await self.read_reg(REG_STATUS_WRITE_LEN),
-            await self.read_reg(REG_STATUS_WRITE_CONFIG) )
-    
-    async def take_read_status(self):
-
-        await self.pulse_control( CTRL_TAKE_STATUS_READ)
-        return await self.read_reg(REG_READ_STATUS)
-    
-    async def wait_dma_write_done(self):
-        await self.wait_status("desc_write_busy", False)
-
-    async def wait_dma_read_done(self):
-        await self.wait_status("desc_read_busy", False)
-
-    async def wait_status_read_handshake(self):
-        await self.wait_status("status_read_hs")
-
-    async def wait_status_write_handshake(self):
-        await self.wait_status("status_write_hs")
-
-    # AxiStream Driver
-
-    async def send_axis_data(self, data: bytes):
-
-        await self.axis_source.send(AxiStreamFrame(data) )
-
-    async def receive_axis_data(self):
-
-        frame = await self.axis_sink.recv()
-        return bytes(frame)
-
-    # Memory Driver
-
-    async def read_memory(self, addr, length):
-
-        return await self.memory.read(addr, length )
-
-    async def write_memory(self, addr, data ):
-
-        await self.memory.write( addr, data )
-
-    async def clear_memory( self, addr, length ):
-
-        await self.memory.write( addr, bytes(length) )
-    
-
-    
-
-
-
-

designs/full_new_reflectometer/tests/full_reflectometer_test/adc_model.sv

@@ -0,0 +1,59 @@
+// AN9238 virtual ADC model (1 port)
+
+module virtual_adc_model #(
+    parameter int unsigned ADC_DATA_WIDTH = 12,
+
+    // Bipolar input range: +/- VOLTAGE_RANGE
+    parameter real VOLTAGE_RANGE = 1.0,
+
+    // Analog input correction
+    parameter real VOLTAGE_GAIN  = 0.2,
+    parameter real GROUND_BIAS   = 0.0,
+
+    // ADC timing parameters
+    parameter time CONVERSION_DELAY = 250ps
+)(
+    input  logic                         clk_i,
+    input  real                          voltage_i,
+
+    output logic                         otr_o,
+    output logic [ADC_DATA_WIDTH-1:0]    data_o
+);
+
+    localparam int unsigned ZERO_CODE = (1 << (ADC_DATA_WIDTH - 1));
+    localparam real VOLTAGE_STEP = (2 * VOLTAGE_RANGE) / real'((1 << ADC_DATA_WIDTH) - 1);
+
+    real voltage_corrected;
+
+    //------------------------------------------------------------
+    // Convert analog voltage to ADC code
+    //------------------------------------------------------------
+    function automatic logic [ADC_DATA_WIDTH-1:0] voltage_to_code( input real voltage );
+        if (voltage <= -VOLTAGE_RANGE) return '0;
+        if (voltage >=  VOLTAGE_RANGE) return {ADC_DATA_WIDTH{1'b1}};
+        return $rtoi(voltage / VOLTAGE_STEP + real'((ZERO_CODE)) + 0.5);
+    endfunction
+
+    function automatic logic range_check( input real voltage );
+        real v_abs = (voltage < 0.0) ? -voltage : voltage;
+        return v_abs >= VOLTAGE_RANGE;
+    endfunction
+
+    //------------------------------------------------------------
+    // Initial state
+    //------------------------------------------------------------
+    initial begin
+        data_o = ZERO_CODE; // 0V
+        otr_o  = 0;
+    end
+
+    //------------------------------------------------------------
+    // Update analog output
+    //------------------------------------------------------------
+    always @(posedge clk_i) begin
+        voltage_corrected = (voltage_i - GROUND_BIAS) * VOLTAGE_GAIN;
+        data_o  <= #(CONVERSION_DELAY) voltage_to_code(voltage_corrected);
+        otr_o   <= #(CONVERSION_DELAY) range_check(voltage_corrected);
+    end
+
+endmodule

designs/full_new_reflectometer/tests/full_reflectometer_test/dac_model.sv

@@ -0,0 +1,58 @@
+// AN9767 model (1 port)
+
+module virtual_dac_model #(
+    parameter int unsigned DAC_DATA_WIDTH = 14,
+
+    // Bipolar output range: +/- VOLTAGE_RANGE
+    parameter real VOLTAGE_RANGE = 5.0,
+
+    // Analog output correction
+    parameter real VOLTAGE_GAIN  = 1.0,
+    parameter real GROUND_BIAS   = 0.0,
+
+    // DAC timing parameters
+    parameter time TRANSMISSION_DELAY = 150ps,
+    parameter time CONVERSION_DELAY   = 150ps
+)(
+    input  logic                      clk_i,
+    input  logic                      wrt_i,
+    input  logic [DAC_DATA_WIDTH-1:0] data_i,
+
+    output real                       voltage_o
+);
+
+    localparam int unsigned ZERO_CODE = (1 << (DAC_DATA_WIDTH - 1));
+    localparam real VOLTAGE_STEP = (2 * VOLTAGE_RANGE) / real'((1 << DAC_DATA_WIDTH) - 1);
+
+    logic [DAC_DATA_WIDTH-1:0] dac_code;
+
+    //------------------------------------------------------------
+    // Convert DAC code to analog voltage
+    //------------------------------------------------------------
+    function automatic real code_to_voltage( input logic [DAC_DATA_WIDTH-1:0] code);
+        return (int'(code) - int'(ZERO_CODE)) * VOLTAGE_STEP;
+    endfunction
+
+    //------------------------------------------------------------
+    // Initial state
+    //------------------------------------------------------------
+    initial begin
+        dac_code  = '0;
+        voltage_o = code_to_voltage('0) * VOLTAGE_GAIN + GROUND_BIAS;
+    end
+
+    //------------------------------------------------------------
+    // Latch new DAC code
+    //------------------------------------------------------------
+    always @(posedge wrt_i) begin
+        dac_code <= #(TRANSMISSION_DELAY) data_i;
+    end
+
+    //------------------------------------------------------------
+    // Update analog output
+    //------------------------------------------------------------
+    always @(posedge clk_i) begin
+        voltage_o <= #(CONVERSION_DELAY) code_to_voltage(dac_code) * VOLTAGE_GAIN + GROUND_BIAS;
+    end
+
+endmodule

designs/full_new_reflectometer/tests/full_reflectometer_test/tb_full_reflectometer.sv

@@ -0,0 +1,261 @@
+
+import dma_reg_pkg::*;
+
+module tb_full_reflectometer #(
+   // parameters for base reflectometer works
+    parameter int unsigned DAC_DATA_WIDTH = 14,
+    parameter int unsigned ADC_DATA_WIDTH = 12,
+    parameter int unsigned PACK_FACTOR = 1,
+    parameter int unsigned PROCESS_MODE = 0,
+    parameter int unsigned ZERO_LEVEL = 8192,
+    parameter int unsigned ACCUM_WIDTH = 32,
+    parameter int unsigned N_MAX = 4096,
+    parameter int unsigned PACKET_SIZE = 64,
+    parameter int unsigned RD_FIFO_WIDTH = 32,
+
+    // parameters for DMA and interfaces
+    parameter int unsigned ADDR_W             = 16,
+    parameter int unsigned DATA_W             = 32,
+    parameter int unsigned USER_W             = 1,
+
+    parameter int unsigned AXI_DATA_WIDTH     = 32,
+
+    parameter int unsigned AXI_STRB_WIDTH     = AXI_DATA_WIDTH / 8,
+    parameter int unsigned AXI_USER_WIDTH     = 1,
+    parameter int unsigned AXI_ID_WIDTH       = 8,
+    parameter int unsigned AXI_MAX_BURST_LEN  = 16,
+
+    parameter int unsigned AXIS_DATA_WIDTH    = AXI_DATA_WIDTH,
+    parameter int unsigned AXIS_KEEP_ENABLE   = AXIS_DATA_WIDTH > 8,
+    parameter int unsigned AXIS_KEEP_WIDTH    = AXIS_DATA_WIDTH / 8,
+    parameter int unsigned AXIS_LAST_ENABLE   = 1,
+    parameter int unsigned AXIS_ID_ENABLE     = 1,
+    parameter int unsigned AXIS_DEST_ENABLE   = 0,
+    parameter int unsigned AXIS_USER_ENABLE   = 1,
+
+    parameter int unsigned ENABLE_SG          = 0,
+    parameter int unsigned ENABLE_UNALIGNED   = 0,
+
+    parameter int unsigned PIPELINE_OUTPUT    = 0
+)(
+  input  logic                 ctrl_clk,
+  input  logic                 rst,
+  output  logic                locked,
+
+  input  logic [ADDR_W-1:0]   s_axil_awaddr,
+  input  logic [2:0]          s_axil_awprot,
+  input  logic                s_axil_awvalid,
+  output logic                s_axil_awready,
+
+  input  logic [DATA_W-1:0]   s_axil_wdata,
+  input  logic [DATA_W/8-1:0] s_axil_wstrb,
+  input  logic                s_axil_wvalid,
+  output logic                s_axil_wready,
+
+  output logic [1:0]          s_axil_bresp,
+  output logic                s_axil_bvalid,
+  input  logic                s_axil_bready,
+
+  input  logic [ADDR_W-1:0]   s_axil_araddr,
+  input  logic [2:0]          s_axil_arprot,
+  input  logic                s_axil_arvalid,
+  output logic                s_axil_arready,
+
+  output logic [DATA_W-1:0]   s_axil_rdata,
+  output logic [1:0]          s_axil_rresp,
+  output logic                s_axil_rvalid,
+  input  logic                s_axil_rready,
+
+    output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata,
+    output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep,
+    output wire                       m_axis_read_data_tvalid,
+    input  wire                       m_axis_read_data_tready,
+    output wire                       m_axis_read_data_tlast,
+    output wire [dma_reg_pkg::AXIS_ID_WIDTH-1:0]   m_axis_read_data_tid,
+    output wire [dma_reg_pkg::AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
+    output wire [dma_reg_pkg::AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser
+);
+
+logic rst_n;
+
+assign rst_n = ~rst;
+
+wire                       clk_adc;
+wire                       adc_otr;
+wire [ADC_DATA_WIDTH-1:0]  adc_data;
+
+wire                       clk_dac;
+wire                       dac_wrt;
+wire [DAC_DATA_WIDTH-1:0]  dac_data;
+
+real signal_voltage;
+
+virtual_dac_model #( // default voltage range is +/- 5V
+        .DAC_DATA_WIDTH(DAC_DATA_WIDTH)
+    ) virtual_dac (
+        .clk_i(clk_dac),
+        .wrt_i(dac_wrt),
+        .data_i(dac_data),
+        .voltage_o(signal_voltage)
+    );
+
+virtual_adc_model #( // default voltage range is +/- 5V
+        .ADC_DATA_WIDTH(ADC_DATA_WIDTH)
+    ) virtual_adc (
+        .clk_i(clk_adc),
+        .voltage_i(signal_voltage),
+        .otr_o(adc_otr),
+        .data_o(adc_data)
+    );
+
+  // ---------------------------------------------------------------------------
+  // AXI-Lite flat -> axi4l_if
+  // ---------------------------------------------------------------------------
+
+  axi4l_if #(
+    .ADDR_W(ADDR_W),
+    .DATA_W(DATA_W),
+    .USER_W(USER_W)
+  ) axil_bus (
+    .aclk(ctrl_clk),
+    .aresetn(rst_n)
+  );
+
+  axi4l_flat_to_if #(
+    .ADDR_W(ADDR_W),
+    .DATA_W(DATA_W),
+    .USER_W(USER_W)
+  ) u_axil_flat_to_if (
+    .s_axil_awaddr (s_axil_awaddr),
+    .s_axil_awprot (s_axil_awprot),
+    .s_axil_awvalid(s_axil_awvalid),
+    .s_axil_awready(s_axil_awready),
+
+    .s_axil_wdata  (s_axil_wdata),
+    .s_axil_wstrb  (s_axil_wstrb),
+    .s_axil_wvalid (s_axil_wvalid),
+    .s_axil_wready (s_axil_wready),
+
+    .s_axil_bresp  (s_axil_bresp),
+    .s_axil_bvalid (s_axil_bvalid),
+    .s_axil_bready (s_axil_bready),
+
+    .s_axil_araddr (s_axil_araddr),
+    .s_axil_arprot (s_axil_arprot),
+    .s_axil_arvalid(s_axil_arvalid),
+    .s_axil_arready(s_axil_arready),
+
+    .s_axil_rdata  (s_axil_rdata),
+    .s_axil_rresp  (s_axil_rresp),
+    .s_axil_rvalid (s_axil_rvalid),
+    .s_axil_rready (s_axil_rready),
+
+    .m_axil(axil_bus)
+  );
+
+  // ---------------------------------------------------------------------------
+  // AXIS interfaces for the updated controller_wrapper_axil
+  // ---------------------------------------------------------------------------
+
+// AXIS READ DMA MASTER output
+  axis_if #(
+    .DATA_W (AXIS_DATA_WIDTH),
+    .KEEP_W (AXIS_KEEP_WIDTH),
+    .ID_W   (AXIS_ID_WIDTH),
+    .DEST_W (dma_reg_pkg::AXIS_DEST_WIDTH),
+    .USER_W (dma_reg_pkg::AXIS_USER_WIDTH)
+  ) dma_read_data (
+    .aclk(ctrl_clk),
+    .aresetn(rst_n)
+  );
+
+logic [AXIS_KEEP_WIDTH-1:0] unused_read_tstrb;
+
+axis_if_to_flat #(
+    .DATA_W (AXIS_DATA_WIDTH),
+    .KEEP_W (AXIS_KEEP_WIDTH),
+    .ID_W   (AXIS_ID_WIDTH),
+    .DEST_W (dma_reg_pkg::AXIS_DEST_WIDTH),
+    .USER_W (dma_reg_pkg::AXIS_USER_WIDTH)
+) u_read_data_if_to_flat (
+    .s_axis(dma_read_data),
+
+    .m_axis_tdata (m_axis_read_data_tdata),
+    .m_axis_tkeep (m_axis_read_data_tkeep),
+    .m_axis_tstrb (unused_read_tstrb),
+    .m_axis_tlast (m_axis_read_data_tlast),
+    .m_axis_tid   (m_axis_read_data_tid),
+    .m_axis_tdest (m_axis_read_data_tdest),
+    .m_axis_tuser (m_axis_read_data_tuser),
+    .m_axis_tvalid(m_axis_read_data_tvalid),
+    .m_axis_tready(m_axis_read_data_tready)
+);
+
+axi4_if #(
+    .ADDR_W(dma_reg_pkg::AXI_ADDR_WIDTH),
+    .DATA_W(AXI_DATA_WIDTH),
+    .ID_W  (AXI_ID_WIDTH),
+    .USER_W(AXI_USER_WIDTH)
+    ) m_axi (
+    .aclk(ctrl_clk),
+    .aresetn(rst_n)
+  );
+
+  reflectometer_and_dma_wrapper #(
+    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+    .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+    .AXI_USER_WIDTH(AXI_USER_WIDTH),
+    .AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN),
+    .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
+    .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
+    .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
+    .AXIS_LAST_ENABLE(AXIS_LAST_ENABLE),
+    .AXIS_ID_ENABLE(AXIS_ID_ENABLE),
+    .AXIS_DEST_ENABLE(AXIS_DEST_ENABLE),
+    .AXIS_USER_ENABLE(AXIS_USER_ENABLE),
+    .ENABLE_SG(ENABLE_SG),
+    .ENABLE_UNALIGNED(ENABLE_UNALIGNED),
+
+    .DAC_DATA_WIDTH(DAC_DATA_WIDTH),
+    .ADC_DATA_WIDTH(ADC_DATA_WIDTH),
+    .PACK_FACTOR(PACK_FACTOR),
+    .PROCESS_MODE(PROCESS_MODE),
+    .ZERO_LEVEL(ZERO_LEVEL),
+    .ACCUM_WIDTH(ACCUM_WIDTH),
+    .N_MAX(N_MAX),
+    .PACKET_SIZE(PACKET_SIZE),
+    .RD_FIFO_WIDTH(RD_FIFO_WIDTH)
+  ) dut (
+    .ctrl_clk(ctrl_clk),
+    .rst_n(rst_n),
+    .locked(locked),
+    .s_axil(axil_bus),
+
+    .m_axi(m_axi),
+
+    .m_axis_read_data(dma_read_data),
+
+    .dac_clk_o(clk_dac),
+    .dac_data(dac_data),
+    .dac_wrt(dac_wrt),
+    .adc_clk_o(clk_adc),
+    .adc_data(adc_data),
+    .adc_otr(adc_otr)
+  );
+
+  axi_ram_wrapper
+#(
+    .DATA_WIDTH(AXI_DATA_WIDTH),
+    .ADDR_WIDTH(dma_reg_pkg::AXI_ADDR_WIDTH),
+    .ID_WIDTH(dma_reg_pkg::AXIS_ID_WIDTH),
+    .PIPELINE_OUTPUT(PIPELINE_OUTPUT)
+) axi_ram_wrapper_inst
+(
+  .clk(ctrl_clk),
+  .rst(!rst_n),
+  .s_axi(m_axi)
+);
+
+
+
+endmodule : tb_full_reflectometer

designs/full_new_reflectometer/tests/reference_model.py

@@ -1,173 +0,0 @@
-from reg_map import *
-
-class Reference_model:
-    def __init__(
-        self,
-        dut,
-        pulse_width,
-        pulse_period,
-        pulse_num,
-        pulse_height,
-        adc_period,
-        window_size,
-        DAC_DATA_WIDTH,
-        ADC_DATA_WIDTH,
-        PACK_FACTOR,
-        PROCESS_MODE,
-        ZERO_LEVEL,
-        ACCUM_WIDTH,
-        N_MAX,
-        PACKET_SIZE,
-        RD_FIFO_WIDTH
-    ):
-
-        self.dut = dut
-
-        # configuration
-        self.pulse_width = pulse_width
-        self.pulse_period = pulse_period
-        self.pulse_num = pulse_num
-        self.pulse_height = pulse_height
-        self.adc_period = adc_period
-        self.window_size = window_size
-
-        # parameters
-        self.DAC_DATA_WIDTH = DAC_DATA_WIDTH
-        self.ADC_DATA_WIDTH = ADC_DATA_WIDTH
-        self.PACK_FACTOR = PACK_FACTOR
-        self.PROCESS_MODE = PROCESS_MODE
-        self.ZERO_LEVEL = ZERO_LEVEL
-        self.ACCUM_WIDTH = ACCUM_WIDTH
-        self.N_MAX = N_MAX
-        self.PACKET_SIZE = PACKET_SIZE
-        self.RD_FIFO_WIDTH = RD_FIFO_WIDTH
-
-        # intermediate data
-        self.samples = []
-        self.window_data = []
-        self.accum_data = []
-
-
-    def gen_input_samples (self):
-        self.samples = []
-        DAC_ZERO = self.ZERO_LEVEL
-        ADC_ZERO = 1 << (self.ADC_DATA_WIDTH - 1)
-
-        DAC_RANGE = 5.0
-        ADC_RANGE = 1.0
-
-        GROUND_BIAS = 0.0
-        ADC_GAIN = 0.2
-
-        DAC_STEP = (2 * DAC_RANGE) / ((1 << self.DAC_DATA_WIDTH) - 1)
-        ADC_STEP = (2 * ADC_RANGE) / ((1 << self.ADC_DATA_WIDTH) - 1)
-
-        ADC_MAX = (1 << self.ADC_DATA_WIDTH) - 1
-
-        for _ in range(self.pulse_num):
-            sample_time = 0
-
-            while sample_time < self.pulse_period:
-                if sample_time < self.pulse_width:
-                    dac_code = self.pulse_height
-                else:
-                    dac_code = DAC_ZERO
-
-                voltage = (dac_code - DAC_ZERO) * DAC_STEP
-                voltage = (voltage - GROUND_BIAS) * ADC_GAIN
-
-                if voltage <= -ADC_RANGE:
-                    adc_code = 0
-                elif voltage >= ADC_RANGE:
-                    adc_code = ADC_MAX
-                else:
-                    adc_code = int(round(voltage / ADC_STEP + ADC_ZERO))
-
-                out_of_range = abs(voltage) >= ADC_RANGE #(adc_code == 0 or adc_code == ADC_MAX)
-
-                if self.PROCESS_MODE:
-                    msb = (adc_code >> (self.ADC_DATA_WIDTH - 1)) & 1
-
-                    if out_of_range:
-                        if msb:
-                            sample = (1 << self.ADC_DATA_WIDTH) - 1
-                        else:
-                            sample = 0
-
-                    else:
-                        sample = (((~msb) & 1) << (self.ADC_DATA_WIDTH - 1)) | (adc_code & ((1 << (self.ADC_DATA_WIDTH - 1)) - 1))
-
-                else:
-                    if out_of_range:
-
-                        if adc_code & (1 << (self.ADC_DATA_WIDTH - 1)):
-                            sample = (1 << self.ADC_DATA_WIDTH) - 1
-                        else:
-                            sample = 0
-
-                    else:
-                        sample = adc_code
-
-                self.samples.append(sample)
-                sample_time += self.adc_period
-
-
-        
-    def apply_window (self):
-        self.window_data = []
-        if self.window_size < 1:
-            raise ValueError(f"window_size must be >= 1, got {self.window_size}" )
-
-        if len(self.samples) == 0:
-            raise ValueError( "samples[] is empty. Call gen_input_samples() first." )
-
-        if len(self.samples) % self.window_size != 0:
-            raise ValueError( f"Number of samples ({len(self.samples)}) " f"is not divisible by window_size ({self.window_size})" )
-        
-        accum = 0
-        cnt = 0
-
-        for sample in self.samples:
-            accum += sample
-            cnt += 1
-            if cnt == self.window_size:
-                self.window_data.append(accum)
-                accum = 0
-                cnt = 0
-
-
-
-    def accumulate (self):
-        self.accum_data = []
-        windows_per_pulse = len(self.window_data) // self.pulse_num
-
-        if windows_per_pulse == 0:
-            raise ValueError("No windows were generated.")
-
-        if len(self.window_data) == 0:
-            raise ValueError( "window_data is empty. Call apply_window() first.")
-
-        if len(self.window_data) % self.pulse_num != 0:
-            raise ValueError( "window_data length is not divisible by pulse_num")
-        
-        for window in range(windows_per_pulse):
-            accum = 0
-
-            for pulse in range(self.pulse_num):
-
-                index = pulse * windows_per_pulse + window
-                accum += self.window_data[index]
-
-            self.accum_data.append(accum)
-            if len(self.accum_data) == windows_per_pulse:
-                print( f"[ReferenceModel] Accumulation complete: "
-            f"{self.pulse_num} pulses -> "
-            f"{windows_per_pulse} windows per pulse -> "
-            f"{len(self.accum_data)} output values.")
-    
-
-    def run(self):
-        self.gen_input_samples()
-        self.apply_window()
-        self.accumulate()
-        return self.accum_data

designs/full_new_reflectometer/tests/reg_map.py

@@ -1,54 +0,0 @@
-# Register indexes from axi4l_reg_map_controller_pkg.sv
-REG_CONTROL = 0
-REG_STATUS = 1
-REG_DAC_WIDTH = 2
-REG_DAC_PERIOD = 3
-REG_DAC_PULSE_NUM = 4
-REG_DAC_PULSE_HEIGHT = 5
-REG_ADC_PERIOD = 6
-REG_WINDOW_SIZE = 7
-REG_ERROR = 8
-REG_DESC_READ_ADDR = 9
-REG_DESC_READ_LEN = 10
-REG_DESC_READ_CONFIG = 11
-REG_READ_STATUS = 12
-REG_DESC_WRITE_ADDR = 13
-REG_DESC_WRITE_LEN_AND_TAG = 14
-REG_STATUS_WRITE_LEN = 15
-REG_STATUS_WRITE_CONFIG = 16
-
-
-# REG_CONTROL pulse bits
-CTRL_START = 1 << 0
-CTRL_RST_SOFT = 1 << 1
-CTRL_CFG_BUS_VALID = 1 << 2
-CTRL_SEND_DESC_READ = 1 << 3
-CTRL_SEND_DESC_WRITE = 1 << 4
-CTRL_TAKE_STATUS_READ = 1 << 5
-CTRL_TAKE_STATUS_WRITE = 1 << 6
-
-# REG_STATUS bits
-STATUS_BUSY                 = 1 << 0
-STATUS_PROCESSING_DONE      = 1 << 1
-
-STATUS_DESC_READ_BUSY       = 1 << 2
-STATUS_DESC_WRITE_BUSY      = 1 << 3
-STATUS_STATUS_READ_BUSY     = 1 << 4
-STATUS_STATUS_WRITE_BUSY    = 1 << 5
-
-STATUS_DESC_READ_HS         = 1 << 6
-STATUS_DESC_WRITE_HS        = 1 << 7
-STATUS_STATUS_READ_HS       = 1 << 8
-STATUS_STATUS_WRITE_HS      = 1 << 9
-
-# PARAMETERS for accumulator reference model
-
-DAC_DATA_WIDTH = 14
-ADC_DATA_WIDTH = 12
-PACK_FACTOR = 1
-PROCESS_MODE = 0
-ZERO_LEVEL = 8192
-ACCUM_WIDTH = 32
-N_MAX = 4096
-PACKET_SIZE = 1024
-RD_FIFO_WIDTH = 32

designs/full_new_reflectometer/tests/scoreboard.py

@@ -1,24 +0,0 @@
-from designs.full_new_reflectometer.tests.reg_map import *
-from designs.full_new_reflectometer.tests.driver import *
-from designs.full_new_reflectometer.tests.reference_model import *
-
-class Scoreboard:
-    def __init__(self, dut, drivers, reference):
-        self.dut = dut
-        self.drivers = drivers
-        self.reference = reference
-
-        self.expected = []
-        self.received_bytes = []
-        self.received = []
-
-        self.test_passed = False
-
-    async def read_dut_result (self, addr, length):
-        return
-    
-    def unpack_result(self):
-        return
-    
-    def compare(self):
-        return