From 08ea864c56f3c18848aef00c2faf70d1fcf9af7a Mon Sep 17 00:00:00 2001 From: otroubi Date: Thu, 3 Sep 2026 15:45:53 +0300 Subject: [PATCH] project for the test --- .../src/axi_ram_wrapper.sv | 67 + .../src/reflectometer_and_dma_wrapper.sv | 7 +- .../src/reflectometer_ip.sv | 12 +- .../full_new_reflectometer/tests/driver.py | 202 --- .../full_reflectometer_test/adc_model.sv | 59 + .../full_reflectometer_test/dac_model.sv | 58 + .../tb_full_reflectometer.sv | 261 +++ .../tests/reference_model.py | 173 -- .../full_new_reflectometer/tests/reg_map.py | 54 - .../tests/scoreboard.py | 24 - .../ip/clk_wiz_ctrl_inst.xci | 1519 +++++++++-------- 11 files changed, 1244 insertions(+), 1192 deletions(-) create mode 100644 designs/full_new_reflectometer/src/axi_ram_wrapper.sv delete mode 100644 designs/full_new_reflectometer/tests/driver.py create mode 100644 designs/full_new_reflectometer/tests/full_reflectometer_test/adc_model.sv create mode 100644 designs/full_new_reflectometer/tests/full_reflectometer_test/dac_model.sv create mode 100644 designs/full_new_reflectometer/tests/full_reflectometer_test/tb_full_reflectometer.sv delete mode 100644 designs/full_new_reflectometer/tests/reference_model.py delete mode 100644 designs/full_new_reflectometer/tests/reg_map.py delete mode 100644 designs/full_new_reflectometer/tests/scoreboard.py diff --git a/designs/full_new_reflectometer/src/axi_ram_wrapper.sv b/designs/full_new_reflectometer/src/axi_ram_wrapper.sv new file mode 100644 index 0000000..ca840a1 --- /dev/null +++ b/designs/full_new_reflectometer/src/axi_ram_wrapper.sv @@ -0,0 +1,67 @@ +module axi_ram_wrapper +#( + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned ADDR_WIDTH = 16, + parameter int unsigned ID_WIDTH = 8, + parameter int unsigned PIPELINE_OUTPUT = 0 +) +( + input logic clk, + input logic rst, + axi4_if.slave s_axi +); + +logic [1:0] ram_bresp; +logic [1:0] ram_rresp; + + +assign s_axi.resp.b.resp = axi_pkg::axi_resp_t'(ram_bresp); +assign s_axi.resp.r.resp = axi_pkg::axi_resp_t'(ram_rresp); + +axi_ram +#( + .DATA_WIDTH(DATA_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .ID_WIDTH(ID_WIDTH), + .PIPELINE_OUTPUT(PIPELINE_OUTPUT) +) axi_ram_inst +( + .clk(clk), + .rst(rst), + .s_axi_awid(s_axi.req.aw.id), + .s_axi_awaddr(s_axi.req.aw.addr), + .s_axi_awlen(s_axi.req.aw.len), + .s_axi_awsize(s_axi.req.aw.size), + .s_axi_awburst(s_axi.req.aw.burst), + .s_axi_awlock(s_axi.req.aw.lock), + .s_axi_awcache(s_axi.req.aw.cache), + .s_axi_awprot(s_axi.req.aw.prot), + .s_axi_awvalid(s_axi.req.aw.valid), + .s_axi_awready(s_axi.resp.aw_ready), + .s_axi_wdata(s_axi.req.w.data), + .s_axi_wstrb(s_axi.req.w.strb), + .s_axi_wlast(s_axi.req.w.last), + .s_axi_wvalid(s_axi.req.w.valid), + .s_axi_wready(s_axi.resp.w_ready), + .s_axi_bid(s_axi.resp.b.id), + .s_axi_bresp(ram_bresp), + .s_axi_bvalid(s_axi.resp.b.valid), + .s_axi_bready(s_axi.req.b_ready), + .s_axi_arid(s_axi.req.ar.id), + .s_axi_araddr(s_axi.req.ar.addr), + .s_axi_arlen(s_axi.req.ar.len), + .s_axi_arsize(s_axi.req.ar.size), + .s_axi_arburst(s_axi.req.ar.burst), + .s_axi_arlock(s_axi.req.ar.lock), + .s_axi_arcache(s_axi.req.ar.cache), + .s_axi_arprot(s_axi.req.ar.prot), + .s_axi_arvalid(s_axi.req.ar.valid), + .s_axi_arready(s_axi.resp.ar_ready), + .s_axi_rid(s_axi.resp.r.id), + .s_axi_rdata(s_axi.resp.r.data), + .s_axi_rresp(ram_rresp), + .s_axi_rlast(s_axi.resp.r.last), + .s_axi_rvalid(s_axi.resp.r.valid), + .s_axi_rready(s_axi.req.r_ready) +); +endmodule \ No newline at end of file diff --git a/designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv b/designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv index e632e88..f42ed3a 100644 --- a/designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv +++ b/designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv @@ -18,12 +18,9 @@ module reflectometer_and_dma_wrapper parameter int unsigned DATA_W = 32, parameter int unsigned USER_W = 1, - parameter int unsigned DAC_DATA_WIDTH = 12, - parameter int unsigned AXI_DATA_WIDTH = 32, parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8, - parameter int unsigned AXI_ID_WIDTH = 8, parameter int unsigned AXI_USER_WIDTH = 1, parameter int unsigned AXI_MAX_BURST_LEN = 16, @@ -46,7 +43,7 @@ module reflectometer_and_dma_wrapper output wire locked, axi4l_if.slave s_axil, - axi_if.master m_axi, + axi4_if.master m_axi, // todo axis_if.master m_axis_read_data, @@ -167,7 +164,7 @@ module reflectometer_and_dma_wrapper ) axi_dma_wrapper_inst ( .clk(ctrl_clk), - .rst(!ctrl_rst_n), + .rst(!rst_n), .s_axis_read_desc(m_axis_desc_read), .m_axis_read_desc_status(s_axis_status_read), .m_axis_read_data(m_axis_read_data), diff --git a/designs/full_new_reflectometer/src/reflectometer_ip.sv b/designs/full_new_reflectometer/src/reflectometer_ip.sv index e837a8b..76530d5 100644 --- a/designs/full_new_reflectometer/src/reflectometer_ip.sv +++ b/designs/full_new_reflectometer/src/reflectometer_ip.sv @@ -57,7 +57,7 @@ wire workflow_done, processing_done; // ------------------------------------------------------------------------- wire clk_sampler, clk_generator, clk_locked; - clk_wiz_ctrl_inst clk_wiz_inst + clk_wiz_0 clk_wiz_inst ( // Clock in ports .clk_200(ctrl_clk), @@ -67,7 +67,7 @@ wire workflow_done, processing_done; .clk_dac_125(clk_generator), .clk_dac_125_180(dac_clk_o), // Status and control signals - .resetn(rst_n), + .reset(~rst_n), .locked(clk_locked) ); @@ -221,20 +221,20 @@ wire workflow_done, processing_done; ); accumulator_top #( - .DATA_WIDTH(DATA_WIDTH), + .DATA_WIDTH(ADC_DATA_WIDTH), .ACCUM_WIDTH(ACCUM_WIDTH), .N_MAX(N_MAX), .PACKET_SIZE(PACKET_SIZE), .RW_WIDTH(RD_FIFO_WIDTH) ) accumulator_top_inst ( .clk_in(clk_sampler), - .rst(!ctrl_rst_n), + .rst(adc_rst), .s_axis_tdata(sampler_m_axis_tdata), .s_axis_tvalid(sampler_m_axis_tvalid), - .start(start), + .start(adc_start), .smp_num(adc_pulse_period), .seq_num(adc_pulse_num), - .window_size(window_size), + .window_size(adc_window_size), .dma_clk_in(ctrl_clk), .req_ready(1'b1), .m_axis_accum(m_axis_accum), diff --git a/designs/full_new_reflectometer/tests/driver.py b/designs/full_new_reflectometer/tests/driver.py deleted file mode 100644 index e7ab67b..0000000 --- a/designs/full_new_reflectometer/tests/driver.py +++ /dev/null @@ -1,202 +0,0 @@ -import cocotb -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge -from cocotbext.axi import AxiLiteBus, AxiLiteMaster -from cocotbext.axi import AxiStreamBus, AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame -from cocotbext.axi import AxiBus, AxiRam - -from reg_map import * - -# Helpers - -def reg_addr(reg_index: int) -> int: - # AXI-Lite uses byte addresses, 32-bit registers are spaced by 4 bytes. - return reg_index * 4 - -def u32(value: int) -> bytes: - return int(value & 0xFFFFFFFF).to_bytes(4, "little") - -# Drivers - -class Drivers: - def __init__(self, dut): - self.dut = dut - - cocotb.start_soon(Clock(dut.ctrl_clk, 10, units="ns").start()) - - self.axil = AxiLiteMaster( - AxiLiteBus.from_prefix(dut, "s_axil"), - dut.ctrl_clk, - dut.rst - ) - - self.axis_source = AxiStreamSource( - AxiStreamBus.from_prefix(dut, "s_axis_write_data"), - dut.ctrl_clk, - dut.rst - ) - - self.axis_sink = AxiStreamSink( - AxiStreamBus.from_prefix(dut, "m_axis_read_data"), - dut.ctrl_clk, - dut.rst - ) - - self.memory = AxiRam( - AxiBus.from_prefix(dut, "m_axi"), - dut.ctrl_clk, - dut.rst - ) - - # Reset - - async def reset(self): - self.dut.rst.value = 1 - for _ in range(5): - await RisingEdge(self.dut.ctrl_clk) - - self.dut.rst.value = 0 - for _ in range(5): - await RisingEdge(self.dut.ctrl_clk) - - # AxiLite Driver - - async def write_reg(self, reg_index: int, value: int): - await self.axil.write(reg_addr(reg_index), u32(value)) - - async def read_reg(self, reg_index: int) -> int: - resp = await self.axil.read(reg_addr(reg_index), 4) - return int.from_bytes(bytes(resp.data), "little") - - async def pulse_control(self, mask): - await self.write_reg( REG_CONTROL, mask ) - - # Reflectometer Driver - - async def configure_reflectometer ( - self, - pulse_width, - pulse_period, - pulse_num, - pulse_height, - adc_period, - window_size - ): - await self.write_reg(REG_DAC_WIDTH, pulse_width) - await self.write_reg(REG_DAC_PERIOD, pulse_period) - await self.write_reg(REG_DAC_PULSE_NUM, pulse_num) - await self.write_reg(REG_DAC_PULSE_HEIGHT, pulse_height) - await self.write_reg(REG_ADC_PERIOD, adc_period) - await self.write_reg(REG_WINDOW_SIZE, window_size) - - await self.pulse_control(CTRL_CFG_BUS_VALID) - - async def send_start(self): - await self.pulse_control(CTRL_START) - - async def soft_reset(self): - await self.pulse_control(CTRL_RST_SOFT) - - async def get_status(self): - status = await self.read_reg(REG_STATUS) - return { - "busy": bool(status & STATUS_BUSY), - "processing_done": bool(status & STATUS_PROCESSING_DONE), - "desc_read_busy": bool(status & STATUS_DESC_READ_BUSY), - "desc_write_busy": bool(status & STATUS_DESC_WRITE_BUSY), - "status_read_busy": bool(status & STATUS_STATUS_READ_BUSY), - "status_write_busy": bool(status & STATUS_STATUS_WRITE_BUSY), - "desc_read_hs": bool(status & STATUS_DESC_READ_HS), - "desc_write_hs": bool(status & STATUS_DESC_WRITE_HS), - "status_read_hs": bool(status & STATUS_STATUS_READ_HS), - "status_write_hs": bool(status & STATUS_STATUS_WRITE_HS) - } - - async def wait_status(self, field, value=True): - - while True: - - status = await self.get_status() - - if status[field] == value: - return - - await RisingEdge(self.dut.ctrl_clk) - - async def wait_processing_done(self): - await self.wait_status("processing_done") - - - async def wait_finish(self): - await self.wait_status("busy", False) - - # DMA Driver - - async def send_desc_write(self, addr, length_tag): - - await self.write_reg(REG_DESC_WRITE_ADDR, addr) - await self.write_reg(REG_DESC_WRITE_LEN_AND_TAG, length_tag) - await self.pulse_control(CTRL_SEND_DESC_WRITE) - - async def send_desc_read(self, addr, length, config): - - await self.write_reg(REG_DESC_READ_ADDR, addr) - await self.write_reg(REG_DESC_READ_LEN, length) - await self.write_reg(REG_DESC_READ_CONFIG, config) - await self.pulse_control( CTRL_SEND_DESC_READ) - - async def take_status_write(self): - await self.pulse_control(CTRL_TAKE_STATUS_WRITE) - - return ( - await self.read_reg(REG_STATUS_WRITE_LEN), - await self.read_reg(REG_STATUS_WRITE_CONFIG) ) - - async def take_read_status(self): - - await self.pulse_control( CTRL_TAKE_STATUS_READ) - return await self.read_reg(REG_READ_STATUS) - - async def wait_dma_write_done(self): - await self.wait_status("desc_write_busy", False) - - async def wait_dma_read_done(self): - await self.wait_status("desc_read_busy", False) - - async def wait_status_read_handshake(self): - await self.wait_status("status_read_hs") - - async def wait_status_write_handshake(self): - await self.wait_status("status_write_hs") - - # AxiStream Driver - - async def send_axis_data(self, data: bytes): - - await self.axis_source.send(AxiStreamFrame(data) ) - - async def receive_axis_data(self): - - frame = await self.axis_sink.recv() - return bytes(frame) - - # Memory Driver - - async def read_memory(self, addr, length): - - return await self.memory.read(addr, length ) - - async def write_memory(self, addr, data ): - - await self.memory.write( addr, data ) - - async def clear_memory( self, addr, length ): - - await self.memory.write( addr, bytes(length) ) - - - - - - - diff --git a/designs/full_new_reflectometer/tests/full_reflectometer_test/adc_model.sv b/designs/full_new_reflectometer/tests/full_reflectometer_test/adc_model.sv new file mode 100644 index 0000000..dee6ef3 --- /dev/null +++ b/designs/full_new_reflectometer/tests/full_reflectometer_test/adc_model.sv @@ -0,0 +1,59 @@ +// AN9238 virtual ADC model (1 port) + +module virtual_adc_model #( + parameter int unsigned ADC_DATA_WIDTH = 12, + + // Bipolar input range: +/- VOLTAGE_RANGE + parameter real VOLTAGE_RANGE = 1.0, + + // Analog input correction + parameter real VOLTAGE_GAIN = 0.2, + parameter real GROUND_BIAS = 0.0, + + // ADC timing parameters + parameter time CONVERSION_DELAY = 250ps +)( + input logic clk_i, + input real voltage_i, + + output logic otr_o, + output logic [ADC_DATA_WIDTH-1:0] data_o +); + + localparam int unsigned ZERO_CODE = (1 << (ADC_DATA_WIDTH - 1)); + localparam real VOLTAGE_STEP = (2 * VOLTAGE_RANGE) / real'((1 << ADC_DATA_WIDTH) - 1); + + real voltage_corrected; + + //------------------------------------------------------------ + // Convert analog voltage to ADC code + //------------------------------------------------------------ + function automatic logic [ADC_DATA_WIDTH-1:0] voltage_to_code( input real voltage ); + if (voltage <= -VOLTAGE_RANGE) return '0; + if (voltage >= VOLTAGE_RANGE) return {ADC_DATA_WIDTH{1'b1}}; + return $rtoi(voltage / VOLTAGE_STEP + real'((ZERO_CODE)) + 0.5); + endfunction + + function automatic logic range_check( input real voltage ); + real v_abs = (voltage < 0.0) ? -voltage : voltage; + return v_abs >= VOLTAGE_RANGE; + endfunction + + //------------------------------------------------------------ + // Initial state + //------------------------------------------------------------ + initial begin + data_o = ZERO_CODE; // 0V + otr_o = 0; + end + + //------------------------------------------------------------ + // Update analog output + //------------------------------------------------------------ + always @(posedge clk_i) begin + voltage_corrected = (voltage_i - GROUND_BIAS) * VOLTAGE_GAIN; + data_o <= #(CONVERSION_DELAY) voltage_to_code(voltage_corrected); + otr_o <= #(CONVERSION_DELAY) range_check(voltage_corrected); + end + +endmodule diff --git a/designs/full_new_reflectometer/tests/full_reflectometer_test/dac_model.sv b/designs/full_new_reflectometer/tests/full_reflectometer_test/dac_model.sv new file mode 100644 index 0000000..f830117 --- /dev/null +++ b/designs/full_new_reflectometer/tests/full_reflectometer_test/dac_model.sv @@ -0,0 +1,58 @@ +// AN9767 model (1 port) + +module virtual_dac_model #( + parameter int unsigned DAC_DATA_WIDTH = 14, + + // Bipolar output range: +/- VOLTAGE_RANGE + parameter real VOLTAGE_RANGE = 5.0, + + // Analog output correction + parameter real VOLTAGE_GAIN = 1.0, + parameter real GROUND_BIAS = 0.0, + + // DAC timing parameters + parameter time TRANSMISSION_DELAY = 150ps, + parameter time CONVERSION_DELAY = 150ps +)( + input logic clk_i, + input logic wrt_i, + input logic [DAC_DATA_WIDTH-1:0] data_i, + + output real voltage_o +); + + localparam int unsigned ZERO_CODE = (1 << (DAC_DATA_WIDTH - 1)); + localparam real VOLTAGE_STEP = (2 * VOLTAGE_RANGE) / real'((1 << DAC_DATA_WIDTH) - 1); + + logic [DAC_DATA_WIDTH-1:0] dac_code; + + //------------------------------------------------------------ + // Convert DAC code to analog voltage + //------------------------------------------------------------ + function automatic real code_to_voltage( input logic [DAC_DATA_WIDTH-1:0] code); + return (int'(code) - int'(ZERO_CODE)) * VOLTAGE_STEP; + endfunction + + //------------------------------------------------------------ + // Initial state + //------------------------------------------------------------ + initial begin + dac_code = '0; + voltage_o = code_to_voltage('0) * VOLTAGE_GAIN + GROUND_BIAS; + end + + //------------------------------------------------------------ + // Latch new DAC code + //------------------------------------------------------------ + always @(posedge wrt_i) begin + dac_code <= #(TRANSMISSION_DELAY) data_i; + end + + //------------------------------------------------------------ + // Update analog output + //------------------------------------------------------------ + always @(posedge clk_i) begin + voltage_o <= #(CONVERSION_DELAY) code_to_voltage(dac_code) * VOLTAGE_GAIN + GROUND_BIAS; + end + +endmodule diff --git a/designs/full_new_reflectometer/tests/full_reflectometer_test/tb_full_reflectometer.sv b/designs/full_new_reflectometer/tests/full_reflectometer_test/tb_full_reflectometer.sv new file mode 100644 index 0000000..50c6992 --- /dev/null +++ b/designs/full_new_reflectometer/tests/full_reflectometer_test/tb_full_reflectometer.sv @@ -0,0 +1,261 @@ + +import dma_reg_pkg::*; + +module tb_full_reflectometer #( + // parameters for base reflectometer works + parameter int unsigned DAC_DATA_WIDTH = 14, + parameter int unsigned ADC_DATA_WIDTH = 12, + parameter int unsigned PACK_FACTOR = 1, + parameter int unsigned PROCESS_MODE = 0, + parameter int unsigned ZERO_LEVEL = 8192, + parameter int unsigned ACCUM_WIDTH = 32, + parameter int unsigned N_MAX = 4096, + parameter int unsigned PACKET_SIZE = 64, + parameter int unsigned RD_FIFO_WIDTH = 32, + + // parameters for DMA and interfaces + parameter int unsigned ADDR_W = 16, + parameter int unsigned DATA_W = 32, + parameter int unsigned USER_W = 1, + + parameter int unsigned AXI_DATA_WIDTH = 32, + + parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8, + parameter int unsigned AXI_USER_WIDTH = 1, + parameter int unsigned AXI_ID_WIDTH = 8, + parameter int unsigned AXI_MAX_BURST_LEN = 16, + + parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH, + parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8, + parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8, + parameter int unsigned AXIS_LAST_ENABLE = 1, + parameter int unsigned AXIS_ID_ENABLE = 1, + parameter int unsigned AXIS_DEST_ENABLE = 0, + parameter int unsigned AXIS_USER_ENABLE = 1, + + parameter int unsigned ENABLE_SG = 0, + parameter int unsigned ENABLE_UNALIGNED = 0, + + parameter int unsigned PIPELINE_OUTPUT = 0 +)( + input logic ctrl_clk, + input logic rst, + output logic locked, + + input logic [ADDR_W-1:0] s_axil_awaddr, + input logic [2:0] s_axil_awprot, + input logic s_axil_awvalid, + output logic s_axil_awready, + + input logic [DATA_W-1:0] s_axil_wdata, + input logic [DATA_W/8-1:0] s_axil_wstrb, + input logic s_axil_wvalid, + output logic s_axil_wready, + + output logic [1:0] s_axil_bresp, + output logic s_axil_bvalid, + input logic s_axil_bready, + + input logic [ADDR_W-1:0] s_axil_araddr, + input logic [2:0] s_axil_arprot, + input logic s_axil_arvalid, + output logic s_axil_arready, + + output logic [DATA_W-1:0] s_axil_rdata, + output logic [1:0] s_axil_rresp, + output logic s_axil_rvalid, + input logic s_axil_rready, + + output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep, + output wire m_axis_read_data_tvalid, + input wire m_axis_read_data_tready, + output wire m_axis_read_data_tlast, + output wire [dma_reg_pkg::AXIS_ID_WIDTH-1:0] m_axis_read_data_tid, + output wire [dma_reg_pkg::AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest, + output wire [dma_reg_pkg::AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser +); + +logic rst_n; + +assign rst_n = ~rst; + +wire clk_adc; +wire adc_otr; +wire [ADC_DATA_WIDTH-1:0] adc_data; + +wire clk_dac; +wire dac_wrt; +wire [DAC_DATA_WIDTH-1:0] dac_data; + +real signal_voltage; + +virtual_dac_model #( // default voltage range is +/- 5V + .DAC_DATA_WIDTH(DAC_DATA_WIDTH) + ) virtual_dac ( + .clk_i(clk_dac), + .wrt_i(dac_wrt), + .data_i(dac_data), + .voltage_o(signal_voltage) + ); + +virtual_adc_model #( // default voltage range is +/- 5V + .ADC_DATA_WIDTH(ADC_DATA_WIDTH) + ) virtual_adc ( + .clk_i(clk_adc), + .voltage_i(signal_voltage), + .otr_o(adc_otr), + .data_o(adc_data) + ); + + // --------------------------------------------------------------------------- + // AXI-Lite flat -> axi4l_if + // --------------------------------------------------------------------------- + + axi4l_if #( + .ADDR_W(ADDR_W), + .DATA_W(DATA_W), + .USER_W(USER_W) + ) axil_bus ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + + axi4l_flat_to_if #( + .ADDR_W(ADDR_W), + .DATA_W(DATA_W), + .USER_W(USER_W) + ) u_axil_flat_to_if ( + .s_axil_awaddr (s_axil_awaddr), + .s_axil_awprot (s_axil_awprot), + .s_axil_awvalid(s_axil_awvalid), + .s_axil_awready(s_axil_awready), + + .s_axil_wdata (s_axil_wdata), + .s_axil_wstrb (s_axil_wstrb), + .s_axil_wvalid (s_axil_wvalid), + .s_axil_wready (s_axil_wready), + + .s_axil_bresp (s_axil_bresp), + .s_axil_bvalid (s_axil_bvalid), + .s_axil_bready (s_axil_bready), + + .s_axil_araddr (s_axil_araddr), + .s_axil_arprot (s_axil_arprot), + .s_axil_arvalid(s_axil_arvalid), + .s_axil_arready(s_axil_arready), + + .s_axil_rdata (s_axil_rdata), + .s_axil_rresp (s_axil_rresp), + .s_axil_rvalid (s_axil_rvalid), + .s_axil_rready (s_axil_rready), + + .m_axil(axil_bus) + ); + + // --------------------------------------------------------------------------- + // AXIS interfaces for the updated controller_wrapper_axil + // --------------------------------------------------------------------------- + +// AXIS READ DMA MASTER output + axis_if #( + .DATA_W (AXIS_DATA_WIDTH), + .KEEP_W (AXIS_KEEP_WIDTH), + .ID_W (AXIS_ID_WIDTH), + .DEST_W (dma_reg_pkg::AXIS_DEST_WIDTH), + .USER_W (dma_reg_pkg::AXIS_USER_WIDTH) + ) dma_read_data ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + +logic [AXIS_KEEP_WIDTH-1:0] unused_read_tstrb; + +axis_if_to_flat #( + .DATA_W (AXIS_DATA_WIDTH), + .KEEP_W (AXIS_KEEP_WIDTH), + .ID_W (AXIS_ID_WIDTH), + .DEST_W (dma_reg_pkg::AXIS_DEST_WIDTH), + .USER_W (dma_reg_pkg::AXIS_USER_WIDTH) +) u_read_data_if_to_flat ( + .s_axis(dma_read_data), + + .m_axis_tdata (m_axis_read_data_tdata), + .m_axis_tkeep (m_axis_read_data_tkeep), + .m_axis_tstrb (unused_read_tstrb), + .m_axis_tlast (m_axis_read_data_tlast), + .m_axis_tid (m_axis_read_data_tid), + .m_axis_tdest (m_axis_read_data_tdest), + .m_axis_tuser (m_axis_read_data_tuser), + .m_axis_tvalid(m_axis_read_data_tvalid), + .m_axis_tready(m_axis_read_data_tready) +); + +axi4_if #( + .ADDR_W(dma_reg_pkg::AXI_ADDR_WIDTH), + .DATA_W(AXI_DATA_WIDTH), + .ID_W (AXI_ID_WIDTH), + .USER_W(AXI_USER_WIDTH) + ) m_axi ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + + reflectometer_and_dma_wrapper #( + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_STRB_WIDTH(AXI_STRB_WIDTH), + .AXI_USER_WIDTH(AXI_USER_WIDTH), + .AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .AXIS_LAST_ENABLE(AXIS_LAST_ENABLE), + .AXIS_ID_ENABLE(AXIS_ID_ENABLE), + .AXIS_DEST_ENABLE(AXIS_DEST_ENABLE), + .AXIS_USER_ENABLE(AXIS_USER_ENABLE), + .ENABLE_SG(ENABLE_SG), + .ENABLE_UNALIGNED(ENABLE_UNALIGNED), + + .DAC_DATA_WIDTH(DAC_DATA_WIDTH), + .ADC_DATA_WIDTH(ADC_DATA_WIDTH), + .PACK_FACTOR(PACK_FACTOR), + .PROCESS_MODE(PROCESS_MODE), + .ZERO_LEVEL(ZERO_LEVEL), + .ACCUM_WIDTH(ACCUM_WIDTH), + .N_MAX(N_MAX), + .PACKET_SIZE(PACKET_SIZE), + .RD_FIFO_WIDTH(RD_FIFO_WIDTH) + ) dut ( + .ctrl_clk(ctrl_clk), + .rst_n(rst_n), + .locked(locked), + .s_axil(axil_bus), + + .m_axi(m_axi), + + .m_axis_read_data(dma_read_data), + + .dac_clk_o(clk_dac), + .dac_data(dac_data), + .dac_wrt(dac_wrt), + .adc_clk_o(clk_adc), + .adc_data(adc_data), + .adc_otr(adc_otr) + ); + + axi_ram_wrapper +#( + .DATA_WIDTH(AXI_DATA_WIDTH), + .ADDR_WIDTH(dma_reg_pkg::AXI_ADDR_WIDTH), + .ID_WIDTH(dma_reg_pkg::AXIS_ID_WIDTH), + .PIPELINE_OUTPUT(PIPELINE_OUTPUT) +) axi_ram_wrapper_inst +( + .clk(ctrl_clk), + .rst(!rst_n), + .s_axi(m_axi) +); + + + +endmodule : tb_full_reflectometer diff --git a/designs/full_new_reflectometer/tests/reference_model.py b/designs/full_new_reflectometer/tests/reference_model.py deleted file mode 100644 index c51de3a..0000000 --- a/designs/full_new_reflectometer/tests/reference_model.py +++ /dev/null @@ -1,173 +0,0 @@ -from reg_map import * - -class Reference_model: - def __init__( - self, - dut, - pulse_width, - pulse_period, - pulse_num, - pulse_height, - adc_period, - window_size, - DAC_DATA_WIDTH, - ADC_DATA_WIDTH, - PACK_FACTOR, - PROCESS_MODE, - ZERO_LEVEL, - ACCUM_WIDTH, - N_MAX, - PACKET_SIZE, - RD_FIFO_WIDTH - ): - - self.dut = dut - - # configuration - self.pulse_width = pulse_width - self.pulse_period = pulse_period - self.pulse_num = pulse_num - self.pulse_height = pulse_height - self.adc_period = adc_period - self.window_size = window_size - - # parameters - self.DAC_DATA_WIDTH = DAC_DATA_WIDTH - self.ADC_DATA_WIDTH = ADC_DATA_WIDTH - self.PACK_FACTOR = PACK_FACTOR - self.PROCESS_MODE = PROCESS_MODE - self.ZERO_LEVEL = ZERO_LEVEL - self.ACCUM_WIDTH = ACCUM_WIDTH - self.N_MAX = N_MAX - self.PACKET_SIZE = PACKET_SIZE - self.RD_FIFO_WIDTH = RD_FIFO_WIDTH - - # intermediate data - self.samples = [] - self.window_data = [] - self.accum_data = [] - - - def gen_input_samples (self): - self.samples = [] - DAC_ZERO = self.ZERO_LEVEL - ADC_ZERO = 1 << (self.ADC_DATA_WIDTH - 1) - - DAC_RANGE = 5.0 - ADC_RANGE = 1.0 - - GROUND_BIAS = 0.0 - ADC_GAIN = 0.2 - - DAC_STEP = (2 * DAC_RANGE) / ((1 << self.DAC_DATA_WIDTH) - 1) - ADC_STEP = (2 * ADC_RANGE) / ((1 << self.ADC_DATA_WIDTH) - 1) - - ADC_MAX = (1 << self.ADC_DATA_WIDTH) - 1 - - for _ in range(self.pulse_num): - sample_time = 0 - - while sample_time < self.pulse_period: - if sample_time < self.pulse_width: - dac_code = self.pulse_height - else: - dac_code = DAC_ZERO - - voltage = (dac_code - DAC_ZERO) * DAC_STEP - voltage = (voltage - GROUND_BIAS) * ADC_GAIN - - if voltage <= -ADC_RANGE: - adc_code = 0 - elif voltage >= ADC_RANGE: - adc_code = ADC_MAX - else: - adc_code = int(round(voltage / ADC_STEP + ADC_ZERO)) - - out_of_range = abs(voltage) >= ADC_RANGE #(adc_code == 0 or adc_code == ADC_MAX) - - if self.PROCESS_MODE: - msb = (adc_code >> (self.ADC_DATA_WIDTH - 1)) & 1 - - if out_of_range: - if msb: - sample = (1 << self.ADC_DATA_WIDTH) - 1 - else: - sample = 0 - - else: - sample = (((~msb) & 1) << (self.ADC_DATA_WIDTH - 1)) | (adc_code & ((1 << (self.ADC_DATA_WIDTH - 1)) - 1)) - - else: - if out_of_range: - - if adc_code & (1 << (self.ADC_DATA_WIDTH - 1)): - sample = (1 << self.ADC_DATA_WIDTH) - 1 - else: - sample = 0 - - else: - sample = adc_code - - self.samples.append(sample) - sample_time += self.adc_period - - - - def apply_window (self): - self.window_data = [] - if self.window_size < 1: - raise ValueError(f"window_size must be >= 1, got {self.window_size}" ) - - if len(self.samples) == 0: - raise ValueError( "samples[] is empty. Call gen_input_samples() first." ) - - if len(self.samples) % self.window_size != 0: - raise ValueError( f"Number of samples ({len(self.samples)}) " f"is not divisible by window_size ({self.window_size})" ) - - accum = 0 - cnt = 0 - - for sample in self.samples: - accum += sample - cnt += 1 - if cnt == self.window_size: - self.window_data.append(accum) - accum = 0 - cnt = 0 - - - - def accumulate (self): - self.accum_data = [] - windows_per_pulse = len(self.window_data) // self.pulse_num - - if windows_per_pulse == 0: - raise ValueError("No windows were generated.") - - if len(self.window_data) == 0: - raise ValueError( "window_data is empty. Call apply_window() first.") - - if len(self.window_data) % self.pulse_num != 0: - raise ValueError( "window_data length is not divisible by pulse_num") - - for window in range(windows_per_pulse): - accum = 0 - - for pulse in range(self.pulse_num): - - index = pulse * windows_per_pulse + window - accum += self.window_data[index] - - self.accum_data.append(accum) - if len(self.accum_data) == windows_per_pulse: - print( f"[ReferenceModel] Accumulation complete: " - f"{self.pulse_num} pulses -> " - f"{windows_per_pulse} windows per pulse -> " - f"{len(self.accum_data)} output values.") - - - def run(self): - self.gen_input_samples() - self.apply_window() - self.accumulate() - return self.accum_data \ No newline at end of file diff --git a/designs/full_new_reflectometer/tests/reg_map.py b/designs/full_new_reflectometer/tests/reg_map.py deleted file mode 100644 index 349a119..0000000 --- a/designs/full_new_reflectometer/tests/reg_map.py +++ /dev/null @@ -1,54 +0,0 @@ -# Register indexes from axi4l_reg_map_controller_pkg.sv -REG_CONTROL = 0 -REG_STATUS = 1 -REG_DAC_WIDTH = 2 -REG_DAC_PERIOD = 3 -REG_DAC_PULSE_NUM = 4 -REG_DAC_PULSE_HEIGHT = 5 -REG_ADC_PERIOD = 6 -REG_WINDOW_SIZE = 7 -REG_ERROR = 8 -REG_DESC_READ_ADDR = 9 -REG_DESC_READ_LEN = 10 -REG_DESC_READ_CONFIG = 11 -REG_READ_STATUS = 12 -REG_DESC_WRITE_ADDR = 13 -REG_DESC_WRITE_LEN_AND_TAG = 14 -REG_STATUS_WRITE_LEN = 15 -REG_STATUS_WRITE_CONFIG = 16 - - -# REG_CONTROL pulse bits -CTRL_START = 1 << 0 -CTRL_RST_SOFT = 1 << 1 -CTRL_CFG_BUS_VALID = 1 << 2 -CTRL_SEND_DESC_READ = 1 << 3 -CTRL_SEND_DESC_WRITE = 1 << 4 -CTRL_TAKE_STATUS_READ = 1 << 5 -CTRL_TAKE_STATUS_WRITE = 1 << 6 - -# REG_STATUS bits -STATUS_BUSY = 1 << 0 -STATUS_PROCESSING_DONE = 1 << 1 - -STATUS_DESC_READ_BUSY = 1 << 2 -STATUS_DESC_WRITE_BUSY = 1 << 3 -STATUS_STATUS_READ_BUSY = 1 << 4 -STATUS_STATUS_WRITE_BUSY = 1 << 5 - -STATUS_DESC_READ_HS = 1 << 6 -STATUS_DESC_WRITE_HS = 1 << 7 -STATUS_STATUS_READ_HS = 1 << 8 -STATUS_STATUS_WRITE_HS = 1 << 9 - -# PARAMETERS for accumulator reference model - -DAC_DATA_WIDTH = 14 -ADC_DATA_WIDTH = 12 -PACK_FACTOR = 1 -PROCESS_MODE = 0 -ZERO_LEVEL = 8192 -ACCUM_WIDTH = 32 -N_MAX = 4096 -PACKET_SIZE = 1024 -RD_FIFO_WIDTH = 32 \ No newline at end of file diff --git a/designs/full_new_reflectometer/tests/scoreboard.py b/designs/full_new_reflectometer/tests/scoreboard.py deleted file mode 100644 index 26dfa52..0000000 --- a/designs/full_new_reflectometer/tests/scoreboard.py +++ /dev/null @@ -1,24 +0,0 @@ -from designs.full_new_reflectometer.tests.reg_map import * -from designs.full_new_reflectometer.tests.driver import * -from designs.full_new_reflectometer.tests.reference_model import * - -class Scoreboard: - def __init__(self, dut, drivers, reference): - self.dut = dut - self.drivers = drivers - self.reference = reference - - self.expected = [] - self.received_bytes = [] - self.received = [] - - self.test_passed = False - - async def read_dut_result (self, addr, length): - return - - def unpack_result(self): - return - - def compare(self): - return diff --git a/designs/reflectometer_base/ip/clk_wiz_ctrl_inst.xci b/designs/reflectometer_base/ip/clk_wiz_ctrl_inst.xci index 62206e7..f861947 100644 --- a/designs/reflectometer_base/ip/clk_wiz_ctrl_inst.xci +++ b/designs/reflectometer_base/ip/clk_wiz_ctrl_inst.xci @@ -1,728 +1,791 @@ -{ - "schema": "xilinx.com:schema:json_instance:1.0", - "ip_inst": { - "xci_name": "clk_wiz_ctrl_inst", - "component_reference": "xilinx.com:ip:clk_wiz:6.0", - "ip_revision": "17", - "gen_directory": "../../../../reflectometer_top.gen/sources_1/ip/clk_wiz_ctrl_inst", - "parameters": { - "component_parameters": { - "Component_Name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "user", "usage": "all" } ], - "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], - "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], - "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], - "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "JITTER_SEL": [ { "value": "Min_O_Jitter", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], - "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ], - "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ], - "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ], - "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ], - "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], - "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ], - "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], - "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT4_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "NUM_OUT_CLKS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "PRIMARY_PORT": [ { "value": "clk_200", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "CLK_OUT1_PORT": [ { "value": "clk_adc_65", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "CLK_OUT2_PORT": [ { "value": "clk_adc_65_180", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "CLK_OUT3_PORT": [ { "value": "clk_dac_125", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "CLK_OUT4_PORT": [ { "value": "clk_dac_125_180", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], - "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], - "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], - "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], - "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], - "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], - "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], - "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], - "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], - "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], - "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], - "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], - "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], - "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], - "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "65", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_REQUESTED_PHASE": [ { "value": "180", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT4_REQUESTED_PHASE": [ { "value": "180", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], - "CLKOUT1_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "CLKOUT2_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "CLKOUT3_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "CLKOUT4_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "CLKOUT5_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "CLKOUT6_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "CLKOUT7_DRIVES": [ { "value": "BUFGCE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], - "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], - "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], - "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], - "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], - "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], - "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], - "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], - "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], - "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], - "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "RESET_PORT": [ { "value": "resetn", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], - "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], - "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], - "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], - "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], - "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], - "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], - "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], - "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], - "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], - "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], - "MMCM_DIVCLK_DIVIDE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "MMCM_BANDWIDTH": [ { "value": "HIGH", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "MMCM_CLKFBOUT_MULT_F": [ { "value": "34.125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], - "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "21.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT1_DIVIDE": [ { "value": "21", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT1_PHASE": [ { "value": "180.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT2_DIVIDE": [ { "value": "11", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT3_DIVIDE": [ { "value": "11", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT3_PHASE": [ { "value": "180.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], - "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], - "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], - "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], - "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], - "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "RESET_TYPE": [ { "value": "ACTIVE_LOW", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "USE_SAFE_CLOCK_STARTUP": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], - "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], - "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], - "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], - "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], - "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], - "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], - "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ], - "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ], - "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT1_JITTER": [ { "value": "137.256", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT1_PHASE_ERROR": [ { "value": "148.044", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_JITTER": [ { "value": "137.256", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_PHASE_ERROR": [ { "value": "148.044", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT3_JITTER": [ { "value": "123.850", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT3_PHASE_ERROR": [ { "value": "148.044", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT4_JITTER": [ { "value": "123.850", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT4_PHASE_ERROR": [ { "value": "148.044", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], - "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ], - "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ], - "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ] - }, - "model_parameters": { - "C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ], - "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT3_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT4_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "c_component_name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "generated", "usage": "all" } ], - "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ], - "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_JITTER_SEL": [ { "value": "Min_O_Jitter", "resolve_type": "generated", "usage": "all" } ], - "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_MIN_O_JITTER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ], - "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PRIM_IN_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ], - "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ], - "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ], - "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ], - "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ], - "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ], - "C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_RESET_LOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_NUM_OUT_CLKS": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT1_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT2_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT3_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT4_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT5_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT6_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT7_DRIVES": [ { "value": "BUFGCE", "resolve_type": "generated", "usage": "all" } ], - "C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ], - "C_INCLK_SUM_ROW1": [ { "value": "__primary_________200.000____________0.010", "resolve_type": "generated", "usage": "all" } ], - "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW1": [ { "value": "clk_adc_65__65.00000______0.000______50.0______137.256____148.044", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW2": [ { "value": "clk_adc_65_180__65.00000____180.000______50.0______137.256____148.044", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW3": [ { "value": "clk_dac_125__124.09091______0.000______50.0______123.850____148.044", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW4": [ { "value": "clk_dac_125_180__124.09091____180.000______50.0______123.850____148.044", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "65", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "125", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "125", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "180", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "180", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT1_OUT_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_OUT_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT3_OUT_FREQ": [ { "value": "124.09091", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT4_OUT_FREQ": [ { "value": "124.09091", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_PHASE": [ { "value": "180.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT4_PHASE": [ { "value": "180.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_BANDWIDTH": [ { "value": "HIGH", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "34.125", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ], - "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ], - "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_DIVCLK_DIVIDE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "21.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "21", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT1_PHASE": [ { "value": "180.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT3_PHASE": [ { "value": "180.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ], - "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ], - "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ], - "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ], - "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ], - "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_PRIMARY_PORT": [ { "value": "clk_200", "resolve_type": "generated", "usage": "all" } ], - "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_OUT1_PORT": [ { "value": "clk_adc_65", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_OUT2_PORT": [ { "value": "clk_adc_65_180", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_OUT3_PORT": [ { "value": "clk_dac_125", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_OUT4_PORT": [ { "value": "clk_dac_125_180", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ], - "C_RESET_PORT": [ { "value": "resetn", "resolve_type": "generated", "usage": "all" } ], - "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ], - "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ], - "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ], - "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ], - "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ], - "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ], - "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ], - "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ], - "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ], - "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ], - "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ], - "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ], - "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ], - "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ], - "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ], - "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ], - "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ], - "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ], - "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ], - "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ], - "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ], - "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ], - "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ], - "C_CLKIN1_JITTER_PS": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ], - "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ], - "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ], - "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ], - "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE2_AUTO": [ { "value": "1.0", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE3_AUTO": [ { "value": "0.5238095238095238", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE4_AUTO": [ { "value": "0.5238095238095238", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE5_AUTO": [ { "value": "0.047619047619047616", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE6_AUTO": [ { "value": "0.047619047619047616", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE7_AUTO": [ { "value": "0.047619047619047616", "resolve_type": "generated", "usage": "all" } ], - "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "124.09091", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "124.09091", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], - "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ] - }, - "project_parameters": { - "ARCHITECTURE": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ], - "BASE_BOARD_PART": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], - "BOARD_CONNECTIONS": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], - "DEVICE": [ { "value": "xc7a100t", "resolve_type": "generated", "usage": "all" } ], - "PACKAGE": [ { "value": "fgg484", "resolve_type": "generated", "usage": "all" } ], - "PREFHDL": [ { "value": "VERILOG", "resolve_type": "generated", "usage": "all" } ], - "SILICON_REVISION": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], - "SIMULATOR_LANGUAGE": [ { "value": "MIXED", "resolve_type": "generated", "usage": "all" } ], - "SPEEDGRADE": [ { "value": "-2", "resolve_type": "generated", "usage": "all" } ], - "STATIC_POWER": [ { "value": "", "resolve_type": "generated", "usage": "all" } ], - "TEMPERATURE_GRADE": [ { "value": "", "resolve_type": "generated", "usage": "all" } ] - }, - "runtime_parameters": { - "IPCONTEXT": [ { "value": "IP_Flow" } ], - "IPREVISION": [ { "value": "17" } ], - "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../../reflectometer_top.gen/sources_1/ip/clk_wiz_ctrl_inst" } ], - "SELECTEDSIMMODEL": [ { "value": "" } ], - "SHAREDDIR": [ { "value": "." } ], - "SWVERSION": [ { "value": "2025.2" } ], - "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] - } - }, - "boundary": { - "ports": { - "resetn": [ { "direction": "in", "driver_value": "0" } ], - "clk_200": [ { "direction": "in" } ], - "clk_adc_65": [ { "direction": "out" } ], - "clk_adc_65_180": [ { "direction": "out" } ], - "clk_dac_125": [ { "direction": "out" } ], - "clk_dac_125_180": [ { "direction": "out" } ], - "locked": [ { "direction": "out" } ] - }, - "interfaces": { - "resetn": { - "vlnv": "xilinx.com:signal:reset:1.0", - "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", - "mode": "slave", - "parameters": { - "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], - "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "RST": [ { "physical_name": "resetn" } ] - } - }, - "clock_CLK_IN1": { - "vlnv": "xilinx.com:signal:clock:1.0", - "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", - "mode": "slave", - "parameters": { - "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], - "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ] - }, - "port_maps": { - "CLK_IN1": [ { "physical_name": "clk_200" } ] - } - }, - "clock_CLK_OUT1": { - "vlnv": "xilinx.com:signal:clock:1.0", - "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", - "mode": "master", - "parameters": { - "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "CLK_OUT1": [ { "physical_name": "clk_adc_65" } ] - } - }, - "clock_CLK_OUT2": { - "vlnv": "xilinx.com:signal:clock:1.0", - "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", - "mode": "master", - "parameters": { - "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "CLK_OUT2": [ { "physical_name": "clk_adc_65_180" } ] - } - }, - "clock_CLK_OUT3": { - "vlnv": "xilinx.com:signal:clock:1.0", - "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", - "mode": "master", - "parameters": { - "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "CLK_OUT3": [ { "physical_name": "clk_dac_125" } ] - } - }, - "clock_CLK_OUT4": { - "vlnv": "xilinx.com:signal:clock:1.0", - "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", - "mode": "master", - "parameters": { - "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "CLK_OUT4": [ { "physical_name": "clk_dac_125_180" } ] - } - } - } - } - }, - "checksum": "3ec15bbf" -} \ No newline at end of file + + + xilinx.com + xci + unknown + 1.0 + + + clk_wiz_ctrl_inst + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + + + + + 100000000 + 0 + 0 + 0.0 + 1 + LEVEL_HIGH + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 100.0 + 0000 + 0000 + 65.00000 + 0000 + 0000 + 65.00000 + BUFGCE + 50.0 + false + 65.00000 + 0.000 + 50.000 + 65 + 0.000 + 1 + 0000 + 0000 + 124.09091 + BUFGCE + 50.0 + false + 65.00000 + 180.000 + 50.000 + 65 + 180 + 1 + 1 + 0000 + 0000 + 124.09091 + BUFGCE + 50.0 + false + 124.09091 + 0.000 + 50.000 + 125 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFGCE + 50.0 + false + 124.09091 + 180.000 + 50.000 + 125 + 180 + 1 + 1 + 0000 + 0000 + 100.000 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_adc_65 + clk_adc_65_180 + clk_dac_125 + clk_dac_125_180 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 1.0 + 0.5238095238095238 + 0.5238095238095238 + 0.047619047619047616 + 0.047619047619047616 + 0.047619047619047616 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________200.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + Min_O_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + HIGH + 34.125 + 0.000 + FALSE + 5.000 + 10.000 + 21.000 + 0.500 + 0.000 + FALSE + 21 + 0.500 + 180.000 + FALSE + 11 + 0.500 + 0.000 + FALSE + 11 + 0.500 + 180.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 5 + None + 0.010 + 0.010 + FALSE + 64.000 + 2.000 + 4 + 0 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_adc_65__65.00000______0.000______50.0______137.256____148.044 + clk_adc_65_180__65.00000____180.000______50.0______137.256____148.044 + clk_dac_125__124.09091______0.000______50.0______123.850____148.044 + clk_dac_125_180__124.09091____180.000______50.0______123.850____148.044 + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + 128.000 + 1.000 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_200 + MMCM + AUTO + 200.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 1 + resetn + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1440.000 + 600.000 + clk_wiz_ctrl_inst + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 50.0 + 0.010 + 100.0 + 0.010 + BUFGCE + 137.256 + false + 148.044 + 50.000 + 65 + 0.000 + 1 + true + BUFGCE + 137.256 + false + 148.044 + 50.000 + 65 + 180 + 1 + true + BUFGCE + 123.850 + false + 148.044 + 50.000 + 125 + 0.000 + 1 + true + BUFGCE + 123.850 + false + 148.044 + 50.000 + 125 + 180 + 1 + true + BUFGCE + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFGCE + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFGCE + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_adc_65 + false + clk_adc_65_180 + false + clk_dac_125 + false + clk_dac_125_180 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clk_wiz_ctrl_inst + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + Min_O_Jitter + locked + HIGH + 34.125 + 0.000 + false + 5.000 + 10.000 + 21.000 + 0.500 + 0.000 + false + 21 + 0.500 + 180.000 + false + 11 + 0.500 + 0.000 + false + 11 + 0.500 + 180.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 5 + None + 0.010 + 0.010 + false + 4 + false + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_200 + MMCM + mmcm_adv + 200.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + resetn + ACTIVE_LOW + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + true + false + false + artix7 + + + xc7a100t + fgg484 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 9 + TRUE + ../../../../reflectometer_top.gen/sources_1/ip/clk_wiz_ctrl_inst + + . + 2021.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +