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project for the test

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otroubi
2026-09-03 15:45:53 +03:00
parent 1f5ef3eab0
commit 08ea864c56
11 changed files with 1244 additions and 1192 deletions
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designs/full_new_reflectometer/src/axi_ram_wrapper.sv
+67
View File
@@ -0,0 +1,67 @@
module axi_ram_wrapper
#(
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned ADDR_WIDTH = 16,
parameter int unsigned ID_WIDTH = 8,
parameter int unsigned PIPELINE_OUTPUT = 0
)
(
input logic clk,
input logic rst,
axi4_if.slave s_axi
);
logic [1:0] ram_bresp;
logic [1:0] ram_rresp;
assign s_axi.resp.b.resp = axi_pkg::axi_resp_t'(ram_bresp);
assign s_axi.resp.r.resp = axi_pkg::axi_resp_t'(ram_rresp);
axi_ram
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.ID_WIDTH(ID_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
) axi_ram_inst
(
.clk(clk),
.rst(rst),
.s_axi_awid(s_axi.req.aw.id),
.s_axi_awaddr(s_axi.req.aw.addr),
.s_axi_awlen(s_axi.req.aw.len),
.s_axi_awsize(s_axi.req.aw.size),
.s_axi_awburst(s_axi.req.aw.burst),
.s_axi_awlock(s_axi.req.aw.lock),
.s_axi_awcache(s_axi.req.aw.cache),
.s_axi_awprot(s_axi.req.aw.prot),
.s_axi_awvalid(s_axi.req.aw.valid),
.s_axi_awready(s_axi.resp.aw_ready),
.s_axi_wdata(s_axi.req.w.data),
.s_axi_wstrb(s_axi.req.w.strb),
.s_axi_wlast(s_axi.req.w.last),
.s_axi_wvalid(s_axi.req.w.valid),
.s_axi_wready(s_axi.resp.w_ready),
.s_axi_bid(s_axi.resp.b.id),
.s_axi_bresp(ram_bresp),
.s_axi_bvalid(s_axi.resp.b.valid),
.s_axi_bready(s_axi.req.b_ready),
.s_axi_arid(s_axi.req.ar.id),
.s_axi_araddr(s_axi.req.ar.addr),
.s_axi_arlen(s_axi.req.ar.len),
.s_axi_arsize(s_axi.req.ar.size),
.s_axi_arburst(s_axi.req.ar.burst),
.s_axi_arlock(s_axi.req.ar.lock),
.s_axi_arcache(s_axi.req.ar.cache),
.s_axi_arprot(s_axi.req.ar.prot),
.s_axi_arvalid(s_axi.req.ar.valid),
.s_axi_arready(s_axi.resp.ar_ready),
.s_axi_rid(s_axi.resp.r.id),
.s_axi_rdata(s_axi.resp.r.data),
.s_axi_rresp(ram_rresp),
.s_axi_rlast(s_axi.resp.r.last),
.s_axi_rvalid(s_axi.resp.r.valid),
.s_axi_rready(s_axi.req.r_ready)
);
endmodule
designs/full_new_reflectometer/src/reflectometer_and_dma_wrapper.sv
+2 -5
View File
@@ -18,12 +18,9 @@ module reflectometer_and_dma_wrapper
parameter int unsigned DATA_W = 32,
parameter int unsigned USER_W = 1,
parameter int unsigned DAC_DATA_WIDTH = 12,
parameter int unsigned AXI_DATA_WIDTH = 32,
parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
parameter int unsigned AXI_ID_WIDTH = 8,
parameter int unsigned AXI_USER_WIDTH = 1,
parameter int unsigned AXI_MAX_BURST_LEN = 16,
@@ -46,7 +43,7 @@ module reflectometer_and_dma_wrapper
output wire locked,
axi4l_if.slave s_axil,
axi_if.master m_axi,
axi4_if.master m_axi,
// todo
axis_if.master m_axis_read_data,
@@ -167,7 +164,7 @@ module reflectometer_and_dma_wrapper
) axi_dma_wrapper_inst
(
.clk(ctrl_clk),
.rst(!ctrl_rst_n),
.rst(!rst_n),
.s_axis_read_desc(m_axis_desc_read),
.m_axis_read_desc_status(s_axis_status_read),
.m_axis_read_data(m_axis_read_data),
designs/full_new_reflectometer/src/reflectometer_ip.sv
+6 -6
View File
@@ -57,7 +57,7 @@ wire workflow_done, processing_done;
// -------------------------------------------------------------------------
wire clk_sampler, clk_generator, clk_locked;
clk_wiz_ctrl_inst clk_wiz_inst
clk_wiz_0 clk_wiz_inst
(
// Clock in ports
.clk_200(ctrl_clk),
@@ -67,7 +67,7 @@ wire workflow_done, processing_done;
.clk_dac_125(clk_generator),
.clk_dac_125_180(dac_clk_o),
// Status and control signals
.resetn(rst_n),
.reset(~rst_n),
.locked(clk_locked)
);
@@ -221,20 +221,20 @@ wire workflow_done, processing_done;
);
accumulator_top #(
.DATA_WIDTH(DATA_WIDTH),
.DATA_WIDTH(ADC_DATA_WIDTH),
.ACCUM_WIDTH(ACCUM_WIDTH),
.N_MAX(N_MAX),
.PACKET_SIZE(PACKET_SIZE),
.RW_WIDTH(RD_FIFO_WIDTH)
) accumulator_top_inst (
.clk_in(clk_sampler),
.rst(!ctrl_rst_n),
.rst(adc_rst),
.s_axis_tdata(sampler_m_axis_tdata),
.s_axis_tvalid(sampler_m_axis_tvalid),
.start(start),
.start(adc_start),
.smp_num(adc_pulse_period),
.seq_num(adc_pulse_num),
.window_size(window_size),
.window_size(adc_window_size),
.dma_clk_in(ctrl_clk),
.req_ready(1'b1),
.m_axis_accum(m_axis_accum),