added librevna firmware reproduce kit
Полное дерево LibreVNA v1.6.5 с доработками master/slave, эталонные битстримы и прошивки STM32, упаковщик .vnafw. Проверено: build.sh пересобирает обе прошивки побайтово идентично лежащим рядом .vnafw. Мастер-битстрим (top_master.bin / extracted/master_fpga.bin) больше нигде не существует — place&route в ISE недетерминирован, из исходников он не восстанавливается. Положено в multi_libreVNA_firmware/reproduce, а не в device_firmware/reproduce как сказано в README комплекта: SHA256SUMS и build.sh ссылаются на ../combined.vnafw, а .vnafw лежат здесь. Корневые правила .gitignore build*/build/ выбрасывали 482 файла, включая сам build.sh и эталонные прошивки STM32 из SHA256SUMS — дописано разыгноривание. Оставшиеся 7 файлов перебивал вложенный апстримный .gitignore (более глубокий имеет приоритет), они добавлены force-add'ом. Промежуточные .o/.d/.su из build-каталогов убраны, .bin/.elf/.hex/.map оставлены. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
This commit is contained in:
Ayzen
+9
-1
@@ -239,4 +239,12 @@ device_firmware/cart_firmware/captures/
|
||||
device_firmware/cart_firmware/.vscode/c_cpp_properties.json
|
||||
device_firmware/cart_firmware/.vscode/launch.json
|
||||
device_firmware/cart_firmware/.vscode/ipch/
|
||||
device_firmware/cart_firmware/.vscode/.browse.c_cpp.db*
|
||||
device_firmware/cart_firmware/.vscode/.browse.c_cpp.db*
|
||||
# --- device_firmware: комплект воспроизведения прошивок LibreVNA ---
|
||||
# Корневые `build*` / `build/` иначе молча выбрасывают сам build.sh и эталонные
|
||||
# прошивки STM32, на которые ссылается reproduce/SHA256SUMS. Каталог сборки
|
||||
# приходится разыгнорить целиком: git не умеет возвращать файл, у которого
|
||||
# исключён родительский каталог.
|
||||
!device_firmware/multi_libreVNA_firmware/reproduce/build.sh
|
||||
!device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/VNA_embedded/build/
|
||||
!device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/VNA_embedded/build_external_lo_slave/
|
||||
|
||||
@@ -0,0 +1,15 @@
|
||||
*.s#*
|
||||
*.b#*
|
||||
*.log
|
||||
*.net
|
||||
*.op.raw
|
||||
*.raw
|
||||
*.vnafw
|
||||
*.aux
|
||||
*.log
|
||||
*.synctex.gz
|
||||
*.xcf
|
||||
*.out
|
||||
*.toc
|
||||
*.pyc
|
||||
Hardware/Renderings
|
||||
+118
@@ -0,0 +1,118 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import argparse
|
||||
import binascii
|
||||
from pathlib import Path
|
||||
|
||||
|
||||
DEFAULT_FPGA_BITSTREAM = "FPGA/VNA/top.bin"
|
||||
DEFAULT_OUTPUT = "combined.vnafw"
|
||||
DEFAULT_MCU_CANDIDATES = [
|
||||
"Software/VNA_embedded/Debug/VNA_embedded.bin",
|
||||
"Software/VNA_embedded/Release/VNA_embedded.bin",
|
||||
"Software/VNA_embedded/build/VNA_embedded.bin",
|
||||
]
|
||||
|
||||
HEADER_SIZE = 24
|
||||
|
||||
|
||||
def parse_args() -> argparse.Namespace:
|
||||
parser = argparse.ArgumentParser(
|
||||
description="Assemble a combined LibreVNA firmware image.",
|
||||
)
|
||||
parser.add_argument(
|
||||
"--bitstream",
|
||||
default=DEFAULT_FPGA_BITSTREAM,
|
||||
help=f"FPGA bitstream to package (default: {DEFAULT_FPGA_BITSTREAM})",
|
||||
)
|
||||
parser.add_argument(
|
||||
"--output",
|
||||
default=DEFAULT_OUTPUT,
|
||||
help=f"Output firmware image path (default: {DEFAULT_OUTPUT})",
|
||||
)
|
||||
parser.add_argument(
|
||||
"--mcu",
|
||||
help="Explicit MCU firmware .bin path. If omitted, the newest known build is used.",
|
||||
)
|
||||
return parser.parse_args()
|
||||
|
||||
|
||||
def select_mcu_firmware(explicit_path: str | None) -> Path:
|
||||
if explicit_path is not None:
|
||||
path = Path(explicit_path)
|
||||
if not path.is_file():
|
||||
raise FileNotFoundError(f"MCU firmware not found: {path}")
|
||||
return path
|
||||
|
||||
latest_modification = 0.0
|
||||
newest_mcu: Path | None = None
|
||||
for candidate in DEFAULT_MCU_CANDIDATES:
|
||||
path = Path(candidate)
|
||||
if not path.is_file():
|
||||
continue
|
||||
modified_time = path.stat().st_mtime
|
||||
if modified_time >= latest_modification:
|
||||
latest_modification = modified_time
|
||||
newest_mcu = path
|
||||
|
||||
if newest_mcu is None:
|
||||
raise FileNotFoundError("Couldn't find MCU firmware file")
|
||||
return newest_mcu
|
||||
|
||||
|
||||
def crc32_from_file(filename: Path, initial_crc: int) -> int:
|
||||
buffer = filename.read_bytes()
|
||||
return binascii.crc32(buffer, initial_crc) & 0xFFFFFFFF
|
||||
|
||||
|
||||
def main() -> int:
|
||||
args = parse_args()
|
||||
|
||||
bitstream_path = Path(args.bitstream)
|
||||
if not bitstream_path.is_file():
|
||||
raise FileNotFoundError(f"FPGA bitstream not found: {bitstream_path}")
|
||||
|
||||
mcu_firmware_path = select_mcu_firmware(args.mcu)
|
||||
output_path = Path(args.output)
|
||||
|
||||
print(f"Using {mcu_firmware_path} as MCU firmware")
|
||||
|
||||
size_fpga = bitstream_path.stat().st_size
|
||||
size_mcu = mcu_firmware_path.stat().st_size
|
||||
print(f"Got FPGA bitstream of size {size_fpga}")
|
||||
print(f"Got MCU firmware of size {size_mcu}")
|
||||
|
||||
crc = crc32_from_file(bitstream_path, 0xFFFFFFFF)
|
||||
crc = crc32_from_file(mcu_firmware_path, crc)
|
||||
print(f"Calculating CRC...:{hex(crc)}")
|
||||
|
||||
output_path.parent.mkdir(parents=True, exist_ok=True)
|
||||
with output_path.open("wb") as firmware_image:
|
||||
firmware_image.write(b"VNA!")
|
||||
firmware_image.write((HEADER_SIZE).to_bytes(4, byteorder="little"))
|
||||
firmware_image.write(size_fpga.to_bytes(4, byteorder="little"))
|
||||
firmware_image.write((HEADER_SIZE + size_fpga).to_bytes(4, byteorder="little"))
|
||||
firmware_image.write(size_mcu.to_bytes(4, byteorder="little"))
|
||||
firmware_image.write(crc.to_bytes(4, byteorder="little"))
|
||||
|
||||
if firmware_image.tell() != HEADER_SIZE:
|
||||
raise RuntimeError(
|
||||
"Incorrect header size "
|
||||
f"(defined as {HEADER_SIZE} but actual header is {firmware_image.tell()})"
|
||||
)
|
||||
|
||||
firmware_image.write(bitstream_path.read_bytes())
|
||||
firmware_image.write(mcu_firmware_path.read_bytes())
|
||||
|
||||
if firmware_image.tell() % 256 != 0:
|
||||
padding = 256 - firmware_image.tell() % 256
|
||||
firmware_image.write(bytearray(padding))
|
||||
|
||||
final_size = firmware_image.tell()
|
||||
|
||||
print(f"Created combined firmware file at {output_path} with size {final_size}")
|
||||
return 0
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
raise SystemExit(main())
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,12 @@
|
||||
*
|
||||
!.gitignore
|
||||
!*/
|
||||
!*.vhd
|
||||
!*.ucf
|
||||
!*.ipf
|
||||
!*.gise
|
||||
!*.xise
|
||||
!*.py
|
||||
!*.bin
|
||||
!VNA/*.dat
|
||||
|
||||
Executable
+45
@@ -0,0 +1,45 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import math
|
||||
|
||||
# Adapt these constants to the step attenuator
|
||||
BITS_OF_ATTENUATION = 7
|
||||
LSB_ATTENUATOR_DB = 0.25
|
||||
NUMBER_LINEAR_ATTENUATION_STEPS = 128
|
||||
|
||||
file = open("AMdepth.dat", "w")
|
||||
|
||||
def bindigits(n, bits):
|
||||
s = bin(n & int("1"*bits, 2))[2:]
|
||||
return ("{0:0>%s}" % (bits)).format(s)
|
||||
|
||||
for i in range(NUMBER_LINEAR_ATTENUATION_STEPS):
|
||||
# calculate percentage of attenuation
|
||||
percent = float(i) / (NUMBER_LINEAR_ATTENUATION_STEPS - 1)
|
||||
# calculate attenuation in dB
|
||||
if percent < 1:
|
||||
required_dB = -20*math.log10(1 - percent)
|
||||
else:
|
||||
required_dB = 999
|
||||
# round to attenuator steps
|
||||
attenuator_dB = round(required_dB / LSB_ATTENUATOR_DB) * LSB_ATTENUATOR_DB
|
||||
# convert to digital attenuator value
|
||||
attenuator_step = int(attenuator_dB / LSB_ATTENUATOR_DB)
|
||||
# constrain
|
||||
if attenuator_step < 0:
|
||||
attenuator_step = 0
|
||||
elif attenuator_step >= pow(2, BITS_OF_ATTENUATION):
|
||||
attenuator_step = pow(2, BITS_OF_ATTENUATION) - 1
|
||||
output = bindigits(attenuator_step, BITS_OF_ATTENUATION)
|
||||
file.write(output+"\n")
|
||||
|
||||
# Calculate actual attenuation
|
||||
actual_dB = attenuator_step * LSB_ATTENUATOR_DB
|
||||
actual_percent = 1 - pow(10, -actual_dB/20)
|
||||
|
||||
percent_desired = round(percent*100, 2)
|
||||
percent_actual = round(actual_percent*100, 2)
|
||||
|
||||
print(f'Target modulation: {percent_desired:.2f}, target dB: {required_dB:.2f}, attenuator setting: {attenuator_step}, achieved dB: {actual_dB}, achieved modulation: {percent_actual:.2f}')
|
||||
|
||||
file.close()
|
||||
+53
@@ -0,0 +1,53 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="AMMult.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="AMMult.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="AMMult.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="AMMult.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1654646662" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1654646662">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4873039598653988690" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1388655879939993469" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8697384035118631440" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
+102
@@ -0,0 +1,102 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2022 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file AMMult.vhd when simulating
|
||||
-- the core, AMMult. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
LIBRARY XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY AMMult IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
b : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||
ce : IN STD_LOGIC;
|
||||
p : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
|
||||
);
|
||||
END AMMult;
|
||||
|
||||
ARCHITECTURE AMMult_a OF AMMult IS
|
||||
-- synthesis translate_off
|
||||
COMPONENT wrapped_AMMult
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
b : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||
ce : IN STD_LOGIC;
|
||||
p : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_AMMult USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
|
||||
GENERIC MAP (
|
||||
c_a_type => 1,
|
||||
c_a_width => 8,
|
||||
c_b_type => 1,
|
||||
c_b_value => "10000001",
|
||||
c_b_width => 7,
|
||||
c_ccm_imp => 0,
|
||||
c_ce_overrides_sclr => 0,
|
||||
c_has_ce => 1,
|
||||
c_has_sclr => 0,
|
||||
c_has_zero_detect => 0,
|
||||
c_latency => 1,
|
||||
c_model_type => 0,
|
||||
c_mult_type => 1,
|
||||
c_optimize_goal => 1,
|
||||
c_out_high => 14,
|
||||
c_out_low => 0,
|
||||
c_round_output => 0,
|
||||
c_round_pt => 0,
|
||||
c_verbosity => 0,
|
||||
c_xdevicefamily => "spartan6"
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_AMMult
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
a => a,
|
||||
b => b,
|
||||
ce => ce,
|
||||
p => p
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END AMMult_a;
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="DFT_CLK.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="DFT_CLK.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="DFT_CLK.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
+59
@@ -0,0 +1,59 @@
|
||||
# file: DFT_CLK.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps;
|
||||
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "RESET" TIG;
|
||||
|
||||
+169
@@ -0,0 +1,169 @@
|
||||
-- file: DFT_CLK.vhd
|
||||
--
|
||||
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- User entered comments
|
||||
------------------------------------------------------------------------------
|
||||
-- None
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
------------------------------------------------------------------------------
|
||||
-- CLK_OUT1___160.000______0.000______50.0______336.927____150.000
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
------------------------------------------------------------------------------
|
||||
-- __primary______________16____________0.010
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
entity DFT_CLK is
|
||||
port
|
||||
(-- Clock in ports
|
||||
CLK_IN1 : in std_logic;
|
||||
-- Clock out ports
|
||||
CLK_OUT1 : out std_logic;
|
||||
-- Status and control signals
|
||||
RESET : in std_logic;
|
||||
LOCKED : out std_logic
|
||||
);
|
||||
end DFT_CLK;
|
||||
|
||||
architecture xilinx of DFT_CLK is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of xilinx : architecture is "DFT_CLK,clk_wiz_v3_6,{component_name=DFT_CLK,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=62.5,clkin2_period=62.5,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
|
||||
-- Input clock buffering / unused connectors
|
||||
signal clkin1 : std_logic;
|
||||
-- Output clock buffering
|
||||
signal clkfb : std_logic;
|
||||
signal clk0 : std_logic;
|
||||
signal clkfx : std_logic;
|
||||
signal clkfbout : std_logic;
|
||||
signal locked_internal : std_logic;
|
||||
signal status_internal : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
|
||||
|
||||
-- Input buffering
|
||||
--------------------------------------
|
||||
clkin1 <= CLK_IN1;
|
||||
|
||||
|
||||
-- Clocking primitive
|
||||
--------------------------------------
|
||||
|
||||
-- Instantiation of the DCM primitive
|
||||
-- * Unused inputs are tied off
|
||||
-- * Unused outputs are labeled unused
|
||||
dcm_sp_inst: DCM_SP
|
||||
generic map
|
||||
(CLKDV_DIVIDE => 2.000,
|
||||
CLKFX_DIVIDE => 1,
|
||||
CLKFX_MULTIPLY => 10,
|
||||
CLKIN_DIVIDE_BY_2 => FALSE,
|
||||
CLKIN_PERIOD => 62.5,
|
||||
CLKOUT_PHASE_SHIFT => "NONE",
|
||||
CLK_FEEDBACK => "1X",
|
||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
|
||||
PHASE_SHIFT => 0,
|
||||
STARTUP_WAIT => FALSE)
|
||||
port map
|
||||
-- Input clock
|
||||
(CLKIN => clkin1,
|
||||
CLKFB => clkfb,
|
||||
-- Output clocks
|
||||
CLK0 => clk0,
|
||||
CLK90 => open,
|
||||
CLK180 => open,
|
||||
CLK270 => open,
|
||||
CLK2X => open,
|
||||
CLK2X180 => open,
|
||||
CLKFX => clkfx,
|
||||
CLKFX180 => open,
|
||||
CLKDV => open,
|
||||
-- Ports for dynamic phase shift
|
||||
PSCLK => '0',
|
||||
PSEN => '0',
|
||||
PSINCDEC => '0',
|
||||
PSDONE => open,
|
||||
-- Other control and status signals
|
||||
LOCKED => locked_internal,
|
||||
STATUS => status_internal,
|
||||
RST => RESET,
|
||||
-- Unused pin, tie low
|
||||
DSSEN => '0');
|
||||
|
||||
LOCKED <= locked_internal;
|
||||
|
||||
|
||||
|
||||
-- Output buffering
|
||||
-------------------------------------
|
||||
clkf_buf : BUFG
|
||||
port map
|
||||
(O => clkfb,
|
||||
I => clk0);
|
||||
|
||||
|
||||
clkout1_buf : BUFG
|
||||
port map
|
||||
(O => CLK_OUT1,
|
||||
I => clkfx);
|
||||
|
||||
|
||||
|
||||
end xilinx;
|
||||
+60
@@ -0,0 +1,60 @@
|
||||
# file: DFT_CLK_exdes.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps;
|
||||
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "COUNTER_RESET" TIG;
|
||||
PIN "RESET" TIG;
|
||||
|
||||
+192
@@ -0,0 +1,192 @@
|
||||
-- file: DFT_CLK_exdes.vhd
|
||||
--
|
||||
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Clocking wizard example design
|
||||
------------------------------------------------------------------------------
|
||||
-- This example design instantiates the created clocking network, where each
|
||||
-- output clock drives a counter. The high bit of each counter is ported.
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
entity DFT_CLK_exdes is
|
||||
generic (
|
||||
TCQ : in time := 100 ps);
|
||||
port
|
||||
(-- Clock in ports
|
||||
CLK_IN1 : in std_logic;
|
||||
-- Reset that only drives logic in example design
|
||||
COUNTER_RESET : in std_logic;
|
||||
CLK_OUT : out std_logic_vector(1 downto 1) ;
|
||||
-- High bits of counters driven by clocks
|
||||
COUNT : out std_logic;
|
||||
-- Status and control signals
|
||||
RESET : in std_logic;
|
||||
LOCKED : out std_logic
|
||||
);
|
||||
end DFT_CLK_exdes;
|
||||
|
||||
architecture xilinx of DFT_CLK_exdes is
|
||||
|
||||
-- Parameters for the counters
|
||||
---------------------------------
|
||||
-- Counter width
|
||||
constant C_W : integer := 16;
|
||||
|
||||
|
||||
-- When the clock goes out of lock, reset the counters
|
||||
signal locked_int : std_logic;
|
||||
signal reset_int : std_logic := '0';
|
||||
|
||||
-- Declare the clocks and counter
|
||||
signal clk : std_logic;
|
||||
signal clk_int : std_logic;
|
||||
signal clk_n : std_logic;
|
||||
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
|
||||
|
||||
-- Need to buffer input clocks that aren't already buffered
|
||||
signal clk_in1_buf : std_logic;
|
||||
signal rst_sync : std_logic;
|
||||
signal rst_sync_int : std_logic;
|
||||
signal rst_sync_int1 : std_logic;
|
||||
signal rst_sync_int2 : std_logic;
|
||||
|
||||
|
||||
component DFT_CLK is
|
||||
port
|
||||
(-- Clock in ports
|
||||
CLK_IN1 : in std_logic;
|
||||
-- Clock out ports
|
||||
CLK_OUT1 : out std_logic;
|
||||
-- Status and control signals
|
||||
RESET : in std_logic;
|
||||
LOCKED : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
-- Alias output to internally used signal
|
||||
LOCKED <= locked_int;
|
||||
|
||||
-- When the clock goes out of lock, reset the counters
|
||||
reset_int <= (not locked_int) or RESET or COUNTER_RESET;
|
||||
|
||||
|
||||
process (clk, reset_int) begin
|
||||
if (reset_int = '1') then
|
||||
rst_sync <= '1';
|
||||
rst_sync_int <= '1';
|
||||
rst_sync_int1 <= '1';
|
||||
rst_sync_int2 <= '1';
|
||||
elsif (clk 'event and clk='1') then
|
||||
rst_sync <= '0';
|
||||
rst_sync_int <= rst_sync;
|
||||
rst_sync_int1 <= rst_sync_int;
|
||||
rst_sync_int2 <= rst_sync_int1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Insert BUFGs on all input clocks that don't already have them
|
||||
----------------------------------------------------------------
|
||||
clkin1_buf : BUFG
|
||||
port map
|
||||
(O => clk_in1_buf,
|
||||
I => CLK_IN1);
|
||||
|
||||
-- Instantiation of the clocking network
|
||||
----------------------------------------
|
||||
clknetwork : DFT_CLK
|
||||
port map
|
||||
(-- Clock in ports
|
||||
CLK_IN1 => clk_in1_buf,
|
||||
-- Clock out ports
|
||||
CLK_OUT1 => clk_int,
|
||||
-- Status and control signals
|
||||
RESET => RESET,
|
||||
LOCKED => locked_int);
|
||||
|
||||
clk_n <= not clk;
|
||||
clkout_oddr : ODDR2
|
||||
port map
|
||||
(Q => CLK_OUT(1),
|
||||
C0 => clk,
|
||||
C1 => clk_n,
|
||||
CE => '1',
|
||||
D0 => '1',
|
||||
D1 => '0',
|
||||
R => '0',
|
||||
S => '0');
|
||||
|
||||
-- Connect the output clocks to the design
|
||||
-------------------------------------------
|
||||
clk <= clk_int;
|
||||
|
||||
-- Output clock sampling
|
||||
-------------------------------------
|
||||
process (clk, rst_sync_int2) begin
|
||||
if (rst_sync_int2 = '1') then
|
||||
counter <= (others => '0') after TCQ;
|
||||
elsif (rising_edge(clk)) then
|
||||
counter <= counter + 1 after TCQ;
|
||||
end if;
|
||||
end process;
|
||||
-- alias the high bit to the output
|
||||
COUNT <= counter(C_W-1);
|
||||
|
||||
|
||||
end xilinx;
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
-- file: DFT_CLK_tb.vhd
|
||||
--
|
||||
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Clocking wizard demonstration testbench
|
||||
------------------------------------------------------------------------------
|
||||
-- This demonstration testbench instantiates the example design for the
|
||||
-- clocking wizard. Input clocks are toggled, which cause the clocking
|
||||
-- network to lock and the counters to increment.
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
|
||||
library std;
|
||||
use std.textio.all;
|
||||
|
||||
library work;
|
||||
use work.all;
|
||||
|
||||
entity DFT_CLK_tb is
|
||||
end DFT_CLK_tb;
|
||||
|
||||
architecture test of DFT_CLK_tb is
|
||||
|
||||
-- Clock to Q delay of 100 ps
|
||||
constant TCQ : time := 100 ps;
|
||||
-- timescale is 1ps
|
||||
constant ONE_NS : time := 1 ns;
|
||||
-- how many cycles to run
|
||||
constant COUNT_PHASE : integer := 1024 + 1;
|
||||
|
||||
|
||||
-- we'll be using the period in many locations
|
||||
constant PER1 : time := 62.5 ns;
|
||||
|
||||
|
||||
-- Declare the input clock signals
|
||||
signal CLK_IN1 : std_logic := '1';
|
||||
-- The high bit of the sampling counter
|
||||
signal COUNT : std_logic;
|
||||
-- Status and control signals
|
||||
signal RESET : std_logic := '0';
|
||||
signal LOCKED : std_logic;
|
||||
signal COUNTER_RESET : std_logic := '0';
|
||||
-- signal defined to stop mti simulation without severity failure in the report
|
||||
signal end_of_sim : std_logic := '0';
|
||||
signal CLK_OUT : std_logic_vector(1 downto 1);
|
||||
--Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
component DFT_CLK_exdes
|
||||
generic (
|
||||
TCQ : in time := 100 ps);
|
||||
port
|
||||
(-- Clock in ports
|
||||
CLK_IN1 : in std_logic;
|
||||
-- Reset that only drives logic in example design
|
||||
COUNTER_RESET : in std_logic;
|
||||
CLK_OUT : out std_logic_vector(1 downto 1) ;
|
||||
-- High bits of counters driven by clocks
|
||||
COUNT : out std_logic;
|
||||
-- Status and control signals
|
||||
RESET : in std_logic;
|
||||
LOCKED : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
|
||||
-- Input clock generation
|
||||
--------------------------------------
|
||||
process begin
|
||||
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
|
||||
end process;
|
||||
|
||||
-- Test sequence
|
||||
process
|
||||
|
||||
procedure simtimeprint is
|
||||
variable outline : line;
|
||||
begin
|
||||
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
|
||||
write(outline, NOW/PER1);
|
||||
write(outline, string'(" ns"));
|
||||
writeline(output,outline);
|
||||
end simtimeprint;
|
||||
|
||||
procedure simfreqprint (period : time; clk_num : integer) is
|
||||
variable outputline : LINE;
|
||||
variable str1 : string(1 to 16);
|
||||
variable str2 : integer;
|
||||
variable str3 : string(1 to 2);
|
||||
variable str4 : integer;
|
||||
variable str5 : string(1 to 4);
|
||||
begin
|
||||
str1 := "Freq of CLK_OUT(";
|
||||
str2 := clk_num;
|
||||
str3 := ") ";
|
||||
str4 := 1000000 ps/period ;
|
||||
str5 := " MHz" ;
|
||||
write(outputline, str1 );
|
||||
write(outputline, str2);
|
||||
write(outputline, str3);
|
||||
write(outputline, str4);
|
||||
write(outputline, str5);
|
||||
writeline(output, outputline);
|
||||
end simfreqprint;
|
||||
|
||||
begin
|
||||
RESET <= '1';
|
||||
wait for (PER1*6);
|
||||
RESET <= '0';
|
||||
wait until LOCKED = '1';
|
||||
COUNTER_RESET <= '1';
|
||||
wait for (PER1*20);
|
||||
COUNTER_RESET <= '0';
|
||||
wait for (PER1*COUNT_PHASE);
|
||||
|
||||
|
||||
simtimeprint;
|
||||
end_of_sim <= '1';
|
||||
wait for 1 ps;
|
||||
report "Simulation Stopped." severity failure;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
-- Instantiation of the example design containing the clock
|
||||
-- network and sampling counters
|
||||
-----------------------------------------------------------
|
||||
dut : DFT_CLK_exdes
|
||||
generic map (
|
||||
TCQ => TCQ)
|
||||
port map
|
||||
(-- Clock in ports
|
||||
CLK_IN1 => CLK_IN1,
|
||||
-- Reset for logic in example design
|
||||
COUNTER_RESET => COUNTER_RESET,
|
||||
CLK_OUT => CLK_OUT,
|
||||
-- High bits of the counters
|
||||
COUNT => COUNT,
|
||||
-- Status and control signals
|
||||
RESET => RESET,
|
||||
LOCKED => LOCKED);
|
||||
|
||||
-- Freq Check
|
||||
|
||||
end test;
|
||||
+220
@@ -0,0 +1,220 @@
|
||||
-- file: DFT_CLK_tb.vhd
|
||||
--
|
||||
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Clocking wizard demonstration testbench
|
||||
------------------------------------------------------------------------------
|
||||
-- This demonstration testbench instantiates the example design for the
|
||||
-- clocking wizard. Input clocks are toggled, which cause the clocking
|
||||
-- network to lock and the counters to increment.
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
|
||||
library std;
|
||||
use std.textio.all;
|
||||
|
||||
library work;
|
||||
use work.all;
|
||||
|
||||
entity DFT_CLK_tb is
|
||||
end DFT_CLK_tb;
|
||||
|
||||
architecture test of DFT_CLK_tb is
|
||||
|
||||
-- Clock to Q delay of 100 ps
|
||||
constant TCQ : time := 100 ps;
|
||||
-- timescale is 1ps
|
||||
constant ONE_NS : time := 1 ns;
|
||||
-- how many cycles to run
|
||||
constant COUNT_PHASE : integer := 1024 + 1;
|
||||
|
||||
|
||||
-- we'll be using the period in many locations
|
||||
constant PER1 : time := 62.5 ns;
|
||||
|
||||
|
||||
-- Declare the input clock signals
|
||||
signal CLK_IN1 : std_logic := '1';
|
||||
-- The high bit of the sampling counter
|
||||
signal COUNT : std_logic;
|
||||
-- Status and control signals
|
||||
signal RESET : std_logic := '0';
|
||||
signal LOCKED : std_logic;
|
||||
signal COUNTER_RESET : std_logic := '0';
|
||||
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
|
||||
-- signal defined to stop mti simulation without severity failure in the report
|
||||
signal end_of_sim : std_logic := '0';
|
||||
signal CLK_OUT : std_logic_vector(1 downto 1);
|
||||
--Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
component DFT_CLK_exdes
|
||||
port
|
||||
(-- Clock in ports
|
||||
CLK_IN1 : in std_logic;
|
||||
-- Reset that only drives logic in example design
|
||||
COUNTER_RESET : in std_logic;
|
||||
CLK_OUT : out std_logic_vector(1 downto 1) ;
|
||||
-- High bits of counters driven by clocks
|
||||
COUNT : out std_logic;
|
||||
-- Status and control signals
|
||||
RESET : in std_logic;
|
||||
LOCKED : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
|
||||
-- Input clock generation
|
||||
--------------------------------------
|
||||
process begin
|
||||
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
|
||||
end process;
|
||||
|
||||
-- Test sequence
|
||||
process
|
||||
|
||||
procedure simtimeprint is
|
||||
variable outline : line;
|
||||
begin
|
||||
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
|
||||
write(outline, NOW/PER1);
|
||||
write(outline, string'(" ns"));
|
||||
writeline(output,outline);
|
||||
end simtimeprint;
|
||||
|
||||
procedure simfreqprint (period : time; clk_num : integer) is
|
||||
variable outputline : LINE;
|
||||
variable str1 : string(1 to 16);
|
||||
variable str2 : integer;
|
||||
variable str3 : string(1 to 2);
|
||||
variable str4 : integer;
|
||||
variable str5 : string(1 to 4);
|
||||
begin
|
||||
str1 := "Freq of CLK_OUT(";
|
||||
str2 := clk_num;
|
||||
str3 := ") ";
|
||||
str4 := 1000000 ps/period ;
|
||||
str5 := " MHz" ;
|
||||
write(outputline, str1 );
|
||||
write(outputline, str2);
|
||||
write(outputline, str3);
|
||||
write(outputline, str4);
|
||||
write(outputline, str5);
|
||||
writeline(output, outputline);
|
||||
end simfreqprint;
|
||||
|
||||
begin
|
||||
report "Timing checks are not valid" severity note;
|
||||
RESET <= '1';
|
||||
wait for (PER1*6);
|
||||
RESET <= '0';
|
||||
wait until LOCKED = '1';
|
||||
wait for (PER1*20);
|
||||
COUNTER_RESET <= '1';
|
||||
wait for (PER1*19.5);
|
||||
COUNTER_RESET <= '0';
|
||||
wait for (PER1*1);
|
||||
report "Timing checks are valid" severity note;
|
||||
wait for (PER1*COUNT_PHASE);
|
||||
|
||||
|
||||
simtimeprint;
|
||||
end_of_sim <= '1';
|
||||
wait for 1 ps;
|
||||
report "Simulation Stopped." severity failure;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
process (CLK_IN1)
|
||||
procedure simtimeprint is
|
||||
variable outline : line;
|
||||
begin
|
||||
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
|
||||
write(outline, NOW/PER1);
|
||||
write(outline, string'(" ns"));
|
||||
writeline(output,outline);
|
||||
end simtimeprint;
|
||||
begin
|
||||
if (CLK_IN1'event and CLK_IN1='1') then
|
||||
timeout_counter <= timeout_counter + '1';
|
||||
if (timeout_counter = "10000000000000") then
|
||||
if (LOCKED /= '1') then
|
||||
simtimeprint;
|
||||
report "NO LOCK signal" severity failure;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Instantiation of the example design containing the clock
|
||||
-- network and sampling counters
|
||||
-----------------------------------------------------------
|
||||
dut : DFT_CLK_exdes
|
||||
port map
|
||||
(-- Clock in ports
|
||||
CLK_IN1 => CLK_IN1,
|
||||
-- Reset for logic in example design
|
||||
COUNTER_RESET => COUNTER_RESET,
|
||||
CLK_OUT => CLK_OUT,
|
||||
-- High bits of the counters
|
||||
COUNT => COUNT,
|
||||
-- Status and control signals
|
||||
RESET => RESET,
|
||||
LOCKED => LOCKED);
|
||||
|
||||
-- Freq Check
|
||||
|
||||
end test;
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="DSP48.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="DSP48.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="DSP48.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="DSP48.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
+139
@@ -0,0 +1,139 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2020 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file DSP48.vhd when simulating
|
||||
-- the core, DSP48. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
LIBRARY XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY DSP48 IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
ce : IN STD_LOGIC;
|
||||
sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||
p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
|
||||
);
|
||||
END DSP48;
|
||||
|
||||
ARCHITECTURE DSP48_a OF DSP48 IS
|
||||
-- synthesis translate_off
|
||||
COMPONENT wrapped_DSP48
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
ce : IN STD_LOGIC;
|
||||
sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||
p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_DSP48 USE ENTITY XilinxCoreLib.xbip_dsp48_macro_v2_1(behavioral)
|
||||
GENERIC MAP (
|
||||
c_a_width => 18,
|
||||
c_b_width => 18,
|
||||
c_c_width => 48,
|
||||
c_concat_width => 48,
|
||||
c_constant_1 => 1,
|
||||
c_d_width => 18,
|
||||
c_has_a => 1,
|
||||
c_has_acin => 0,
|
||||
c_has_acout => 0,
|
||||
c_has_b => 1,
|
||||
c_has_bcin => 0,
|
||||
c_has_bcout => 0,
|
||||
c_has_c => 1,
|
||||
c_has_carrycascin => 0,
|
||||
c_has_carrycascout => 0,
|
||||
c_has_carryin => 0,
|
||||
c_has_carryout => 0,
|
||||
c_has_ce => 1,
|
||||
c_has_cea => 0,
|
||||
c_has_ceb => 0,
|
||||
c_has_cec => 0,
|
||||
c_has_ceconcat => 0,
|
||||
c_has_ced => 0,
|
||||
c_has_cem => 0,
|
||||
c_has_cep => 0,
|
||||
c_has_cesel => 0,
|
||||
c_has_concat => 0,
|
||||
c_has_d => 0,
|
||||
c_has_indep_ce => 0,
|
||||
c_has_indep_sclr => 0,
|
||||
c_has_pcin => 0,
|
||||
c_has_pcout => 0,
|
||||
c_has_sclr => 0,
|
||||
c_has_sclra => 0,
|
||||
c_has_sclrb => 0,
|
||||
c_has_sclrc => 0,
|
||||
c_has_sclrconcat => 0,
|
||||
c_has_sclrd => 0,
|
||||
c_has_sclrm => 0,
|
||||
c_has_sclrp => 0,
|
||||
c_has_sclrsel => 0,
|
||||
c_latency => -1,
|
||||
c_model_type => 0,
|
||||
c_opmodes => "0000000000010000000,0000001100010000000",
|
||||
c_p_lsb => 0,
|
||||
c_p_msb => 47,
|
||||
c_reg_config => "00000000000011100111100111100100",
|
||||
c_sel_width => 1,
|
||||
c_test_core => 0,
|
||||
c_verbosity => 0,
|
||||
c_xdevicefamily => "spartan6"
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_DSP48
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
sel => sel,
|
||||
a => a,
|
||||
b => b,
|
||||
c => c,
|
||||
p => p
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END DSP48_a;
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="DSP_SLICE.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="DSP_SLICE.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="DSP_SLICE.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="DSP_SLICE.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
+139
@@ -0,0 +1,139 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2020 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file DSP_SLICE.vhd when simulating
|
||||
-- the core, DSP_SLICE. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
LIBRARY XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY DSP_SLICE IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
ce : IN STD_LOGIC;
|
||||
sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||
p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
|
||||
);
|
||||
END DSP_SLICE;
|
||||
|
||||
ARCHITECTURE DSP_SLICE_a OF DSP_SLICE IS
|
||||
-- synthesis translate_off
|
||||
COMPONENT wrapped_DSP_SLICE
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
ce : IN STD_LOGIC;
|
||||
sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||
p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_DSP_SLICE USE ENTITY XilinxCoreLib.xbip_dsp48_macro_v2_1(behavioral)
|
||||
GENERIC MAP (
|
||||
c_a_width => 18,
|
||||
c_b_width => 18,
|
||||
c_c_width => 48,
|
||||
c_concat_width => 48,
|
||||
c_constant_1 => 1,
|
||||
c_d_width => 18,
|
||||
c_has_a => 1,
|
||||
c_has_acin => 0,
|
||||
c_has_acout => 0,
|
||||
c_has_b => 1,
|
||||
c_has_bcin => 0,
|
||||
c_has_bcout => 0,
|
||||
c_has_c => 1,
|
||||
c_has_carrycascin => 0,
|
||||
c_has_carrycascout => 0,
|
||||
c_has_carryin => 0,
|
||||
c_has_carryout => 0,
|
||||
c_has_ce => 1,
|
||||
c_has_cea => 0,
|
||||
c_has_ceb => 0,
|
||||
c_has_cec => 0,
|
||||
c_has_ceconcat => 0,
|
||||
c_has_ced => 0,
|
||||
c_has_cem => 0,
|
||||
c_has_cep => 0,
|
||||
c_has_cesel => 0,
|
||||
c_has_concat => 0,
|
||||
c_has_d => 0,
|
||||
c_has_indep_ce => 0,
|
||||
c_has_indep_sclr => 0,
|
||||
c_has_pcin => 0,
|
||||
c_has_pcout => 0,
|
||||
c_has_sclr => 0,
|
||||
c_has_sclra => 0,
|
||||
c_has_sclrb => 0,
|
||||
c_has_sclrc => 0,
|
||||
c_has_sclrconcat => 0,
|
||||
c_has_sclrd => 0,
|
||||
c_has_sclrm => 0,
|
||||
c_has_sclrp => 0,
|
||||
c_has_sclrsel => 0,
|
||||
c_latency => -1,
|
||||
c_model_type => 0,
|
||||
c_opmodes => "0000000000010000000,0000001100010000000",
|
||||
c_p_lsb => 0,
|
||||
c_p_msb => 47,
|
||||
c_reg_config => "00000000000011100111100111100100",
|
||||
c_sel_width => 1,
|
||||
c_test_core => 0,
|
||||
c_verbosity => 0,
|
||||
c_xdevicefamily => "spartan6"
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_DSP_SLICE
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
sel => sel,
|
||||
a => a,
|
||||
b => b,
|
||||
c => c,
|
||||
p => p
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END DSP_SLICE_a;
|
||||
+53
@@ -0,0 +1,53 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ModulationMemory.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="ModulationMemory.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ModulationMemory.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="ModulationMemory.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1122694780993201560" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5643155787033519143" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8675282148687179814" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
+149
@@ -0,0 +1,149 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2022 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file ModulationMemory.vhd when simulating
|
||||
-- the core, ModulationMemory. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
LIBRARY XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY ModulationMemory IS
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(143 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(143 DOWNTO 0)
|
||||
);
|
||||
END ModulationMemory;
|
||||
|
||||
ARCHITECTURE ModulationMemory_a OF ModulationMemory IS
|
||||
-- synthesis translate_off
|
||||
COMPONENT wrapped_ModulationMemory
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(143 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(143 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_ModulationMemory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
|
||||
GENERIC MAP (
|
||||
c_addra_width => 8,
|
||||
c_addrb_width => 8,
|
||||
c_algorithm => 1,
|
||||
c_axi_id_width => 4,
|
||||
c_axi_slave_type => 0,
|
||||
c_axi_type => 1,
|
||||
c_byte_size => 9,
|
||||
c_common_clk => 0,
|
||||
c_default_data => "0",
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_enable_32bit_address => 0,
|
||||
c_family => "spartan6",
|
||||
c_has_axi_id => 0,
|
||||
c_has_ena => 0,
|
||||
c_has_enb => 0,
|
||||
c_has_injecterr => 0,
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_has_regcea => 0,
|
||||
c_has_regceb => 0,
|
||||
c_has_rsta => 0,
|
||||
c_has_rstb => 0,
|
||||
c_has_softecc_input_regs_a => 0,
|
||||
c_has_softecc_output_regs_b => 0,
|
||||
c_init_file => "BlankString",
|
||||
c_init_file_name => "no_coe_file_loaded",
|
||||
c_inita_val => "0",
|
||||
c_initb_val => "0",
|
||||
c_interface_type => 0,
|
||||
c_load_init_file => 0,
|
||||
c_mem_type => 1,
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_prim_type => 1,
|
||||
c_read_depth_a => 256,
|
||||
c_read_depth_b => 256,
|
||||
c_read_width_a => 144,
|
||||
c_read_width_b => 144,
|
||||
c_rst_priority_a => "CE",
|
||||
c_rst_priority_b => "CE",
|
||||
c_rst_type => "SYNC",
|
||||
c_rstram_a => 0,
|
||||
c_rstram_b => 0,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_use_bram_block => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_use_byte_web => 0,
|
||||
c_use_default_data => 0,
|
||||
c_use_ecc => 0,
|
||||
c_use_softecc => 0,
|
||||
c_wea_width => 1,
|
||||
c_web_width => 1,
|
||||
c_write_depth_a => 256,
|
||||
c_write_depth_b => 256,
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_write_width_a => 144,
|
||||
c_write_width_b => 144,
|
||||
c_xdevicefamily => "spartan6"
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_ModulationMemory
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
wea => wea,
|
||||
addra => addra,
|
||||
dina => dina,
|
||||
clkb => clkb,
|
||||
addrb => addrb,
|
||||
doutb => doutb
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END ModulationMemory_a;
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="PLL.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="PLL.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="PLL.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1588801396" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1588801396">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-7485999881756126958" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5187593455580750305" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8519729393005554412" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
+59
@@ -0,0 +1,59 @@
|
||||
# file: PLL.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps;
|
||||
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "RESET" TIG;
|
||||
|
||||
+172
@@ -0,0 +1,172 @@
|
||||
-- file: PLL.vhd
|
||||
--
|
||||
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- User entered comments
|
||||
------------------------------------------------------------------------------
|
||||
-- None
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
------------------------------------------------------------------------------
|
||||
-- CLK_OUT1___102.400______0.000______50.0_____1274.405____150.000
|
||||
--
|
||||
------------------------------------------------------------------------------
|
||||
-- "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
------------------------------------------------------------------------------
|
||||
-- __primary______________16____________0.010
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
entity PLL is
|
||||
port
|
||||
(-- Clock in ports
|
||||
CLK_IN1 : in std_logic;
|
||||
-- Clock out ports
|
||||
CLK_OUT1 : out std_logic;
|
||||
-- Status and control signals
|
||||
RESET : in std_logic;
|
||||
LOCKED : out std_logic
|
||||
);
|
||||
end PLL;
|
||||
|
||||
architecture xilinx of PLL is
|
||||
attribute CORE_GENERATION_INFO : string;
|
||||
attribute CORE_GENERATION_INFO of xilinx : architecture is "PLL,clk_wiz_v3_6,{component_name=PLL,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=62.5,clkin2_period=62.5,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
|
||||
-- Input clock buffering / unused connectors
|
||||
signal clkin1 : std_logic;
|
||||
-- Output clock buffering
|
||||
signal clkfb : std_logic;
|
||||
signal clk0 : std_logic;
|
||||
signal clkfx : std_logic;
|
||||
signal clkfbout : std_logic;
|
||||
signal locked_internal : std_logic;
|
||||
signal status_internal : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
|
||||
|
||||
-- Input buffering
|
||||
--------------------------------------
|
||||
clkin1_buf : IBUFG
|
||||
port map
|
||||
(O => clkin1,
|
||||
I => CLK_IN1);
|
||||
|
||||
|
||||
-- Clocking primitive
|
||||
--------------------------------------
|
||||
|
||||
-- Instantiation of the DCM primitive
|
||||
-- * Unused inputs are tied off
|
||||
-- * Unused outputs are labeled unused
|
||||
dcm_sp_inst: DCM_SP
|
||||
generic map
|
||||
(CLKDV_DIVIDE => 2.000,
|
||||
CLKFX_DIVIDE => 5,
|
||||
CLKFX_MULTIPLY => 32,
|
||||
CLKIN_DIVIDE_BY_2 => FALSE,
|
||||
CLKIN_PERIOD => 62.5,
|
||||
CLKOUT_PHASE_SHIFT => "NONE",
|
||||
CLK_FEEDBACK => "1X",
|
||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
|
||||
PHASE_SHIFT => 0,
|
||||
STARTUP_WAIT => FALSE)
|
||||
port map
|
||||
-- Input clock
|
||||
(CLKIN => clkin1,
|
||||
CLKFB => clkfb,
|
||||
-- Output clocks
|
||||
CLK0 => clk0,
|
||||
CLK90 => open,
|
||||
CLK180 => open,
|
||||
CLK270 => open,
|
||||
CLK2X => open,
|
||||
CLK2X180 => open,
|
||||
CLKFX => clkfx,
|
||||
CLKFX180 => open,
|
||||
CLKDV => open,
|
||||
-- Ports for dynamic phase shift
|
||||
PSCLK => '0',
|
||||
PSEN => '0',
|
||||
PSINCDEC => '0',
|
||||
PSDONE => open,
|
||||
-- Other control and status signals
|
||||
LOCKED => locked_internal,
|
||||
STATUS => status_internal,
|
||||
RST => RESET,
|
||||
-- Unused pin, tie low
|
||||
DSSEN => '0');
|
||||
|
||||
LOCKED <= locked_internal;
|
||||
|
||||
|
||||
|
||||
-- Output buffering
|
||||
-------------------------------------
|
||||
clkf_buf : BUFG
|
||||
port map
|
||||
(O => clkfb,
|
||||
I => clk0);
|
||||
|
||||
|
||||
clkout1_buf : BUFG
|
||||
port map
|
||||
(O => CLK_OUT1,
|
||||
I => clkfx);
|
||||
|
||||
|
||||
|
||||
end xilinx;
|
||||
+60
@@ -0,0 +1,60 @@
|
||||
# file: PLL_exdes.ucf
|
||||
#
|
||||
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system
|
||||
#----------------------------------------------------------------
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps;
|
||||
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "COUNTER_RESET" TIG;
|
||||
PIN "RESET" TIG;
|
||||
|
||||
+182
@@ -0,0 +1,182 @@
|
||||
-- file: PLL_exdes.vhd
|
||||
--
|
||||
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Clocking wizard example design
|
||||
------------------------------------------------------------------------------
|
||||
-- This example design instantiates the created clocking network, where each
|
||||
-- output clock drives a counter. The high bit of each counter is ported.
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
entity PLL_exdes is
|
||||
generic (
|
||||
TCQ : in time := 100 ps);
|
||||
port
|
||||
(-- Clock in ports
|
||||
CLK_IN1 : in std_logic;
|
||||
-- Reset that only drives logic in example design
|
||||
COUNTER_RESET : in std_logic;
|
||||
CLK_OUT : out std_logic_vector(1 downto 1) ;
|
||||
-- High bits of counters driven by clocks
|
||||
COUNT : out std_logic;
|
||||
-- Status and control signals
|
||||
RESET : in std_logic;
|
||||
LOCKED : out std_logic
|
||||
);
|
||||
end PLL_exdes;
|
||||
|
||||
architecture xilinx of PLL_exdes is
|
||||
|
||||
-- Parameters for the counters
|
||||
---------------------------------
|
||||
-- Counter width
|
||||
constant C_W : integer := 16;
|
||||
|
||||
|
||||
-- When the clock goes out of lock, reset the counters
|
||||
signal locked_int : std_logic;
|
||||
signal reset_int : std_logic := '0';
|
||||
|
||||
-- Declare the clocks and counter
|
||||
signal clk : std_logic;
|
||||
signal clk_int : std_logic;
|
||||
signal clk_n : std_logic;
|
||||
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
|
||||
signal rst_sync : std_logic;
|
||||
signal rst_sync_int : std_logic;
|
||||
signal rst_sync_int1 : std_logic;
|
||||
signal rst_sync_int2 : std_logic;
|
||||
|
||||
|
||||
component PLL is
|
||||
port
|
||||
(-- Clock in ports
|
||||
CLK_IN1 : in std_logic;
|
||||
-- Clock out ports
|
||||
CLK_OUT1 : out std_logic;
|
||||
-- Status and control signals
|
||||
RESET : in std_logic;
|
||||
LOCKED : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
-- Alias output to internally used signal
|
||||
LOCKED <= locked_int;
|
||||
|
||||
-- When the clock goes out of lock, reset the counters
|
||||
reset_int <= (not locked_int) or RESET or COUNTER_RESET;
|
||||
|
||||
|
||||
process (clk, reset_int) begin
|
||||
if (reset_int = '1') then
|
||||
rst_sync <= '1';
|
||||
rst_sync_int <= '1';
|
||||
rst_sync_int1 <= '1';
|
||||
rst_sync_int2 <= '1';
|
||||
elsif (clk 'event and clk='1') then
|
||||
rst_sync <= '0';
|
||||
rst_sync_int <= rst_sync;
|
||||
rst_sync_int1 <= rst_sync_int;
|
||||
rst_sync_int2 <= rst_sync_int1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Instantiation of the clocking network
|
||||
----------------------------------------
|
||||
clknetwork : PLL
|
||||
port map
|
||||
(-- Clock in ports
|
||||
CLK_IN1 => CLK_IN1,
|
||||
-- Clock out ports
|
||||
CLK_OUT1 => clk_int,
|
||||
-- Status and control signals
|
||||
RESET => RESET,
|
||||
LOCKED => locked_int);
|
||||
|
||||
clk_n <= not clk;
|
||||
clkout_oddr : ODDR2
|
||||
port map
|
||||
(Q => CLK_OUT(1),
|
||||
C0 => clk,
|
||||
C1 => clk_n,
|
||||
CE => '1',
|
||||
D0 => '1',
|
||||
D1 => '0',
|
||||
R => '0',
|
||||
S => '0');
|
||||
|
||||
-- Connect the output clocks to the design
|
||||
-------------------------------------------
|
||||
clk <= clk_int;
|
||||
|
||||
-- Output clock sampling
|
||||
-------------------------------------
|
||||
process (clk, rst_sync_int2) begin
|
||||
if (rst_sync_int2 = '1') then
|
||||
counter <= (others => '0') after TCQ;
|
||||
elsif (rising_edge(clk)) then
|
||||
counter <= counter + 1 after TCQ;
|
||||
end if;
|
||||
end process;
|
||||
-- alias the high bit to the output
|
||||
COUNT <= counter(C_W-1);
|
||||
|
||||
|
||||
end xilinx;
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
-- file: PLL_tb.vhd
|
||||
--
|
||||
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Clocking wizard demonstration testbench
|
||||
------------------------------------------------------------------------------
|
||||
-- This demonstration testbench instantiates the example design for the
|
||||
-- clocking wizard. Input clocks are toggled, which cause the clocking
|
||||
-- network to lock and the counters to increment.
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
|
||||
library std;
|
||||
use std.textio.all;
|
||||
|
||||
library work;
|
||||
use work.all;
|
||||
|
||||
entity PLL_tb is
|
||||
end PLL_tb;
|
||||
|
||||
architecture test of PLL_tb is
|
||||
|
||||
-- Clock to Q delay of 100 ps
|
||||
constant TCQ : time := 100 ps;
|
||||
-- timescale is 1ps
|
||||
constant ONE_NS : time := 1 ns;
|
||||
-- how many cycles to run
|
||||
constant COUNT_PHASE : integer := 1024 + 1;
|
||||
|
||||
|
||||
-- we'll be using the period in many locations
|
||||
constant PER1 : time := 62.5 ns;
|
||||
|
||||
|
||||
-- Declare the input clock signals
|
||||
signal CLK_IN1 : std_logic := '1';
|
||||
-- The high bit of the sampling counter
|
||||
signal COUNT : std_logic;
|
||||
-- Status and control signals
|
||||
signal RESET : std_logic := '0';
|
||||
signal LOCKED : std_logic;
|
||||
signal COUNTER_RESET : std_logic := '0';
|
||||
-- signal defined to stop mti simulation without severity failure in the report
|
||||
signal end_of_sim : std_logic := '0';
|
||||
signal CLK_OUT : std_logic_vector(1 downto 1);
|
||||
--Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
component PLL_exdes
|
||||
generic (
|
||||
TCQ : in time := 100 ps);
|
||||
port
|
||||
(-- Clock in ports
|
||||
CLK_IN1 : in std_logic;
|
||||
-- Reset that only drives logic in example design
|
||||
COUNTER_RESET : in std_logic;
|
||||
CLK_OUT : out std_logic_vector(1 downto 1) ;
|
||||
-- High bits of counters driven by clocks
|
||||
COUNT : out std_logic;
|
||||
-- Status and control signals
|
||||
RESET : in std_logic;
|
||||
LOCKED : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
|
||||
-- Input clock generation
|
||||
--------------------------------------
|
||||
process begin
|
||||
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
|
||||
end process;
|
||||
|
||||
-- Test sequence
|
||||
process
|
||||
|
||||
procedure simtimeprint is
|
||||
variable outline : line;
|
||||
begin
|
||||
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
|
||||
write(outline, NOW/PER1);
|
||||
write(outline, string'(" ns"));
|
||||
writeline(output,outline);
|
||||
end simtimeprint;
|
||||
|
||||
procedure simfreqprint (period : time; clk_num : integer) is
|
||||
variable outputline : LINE;
|
||||
variable str1 : string(1 to 16);
|
||||
variable str2 : integer;
|
||||
variable str3 : string(1 to 2);
|
||||
variable str4 : integer;
|
||||
variable str5 : string(1 to 4);
|
||||
begin
|
||||
str1 := "Freq of CLK_OUT(";
|
||||
str2 := clk_num;
|
||||
str3 := ") ";
|
||||
str4 := 1000000 ps/period ;
|
||||
str5 := " MHz" ;
|
||||
write(outputline, str1 );
|
||||
write(outputline, str2);
|
||||
write(outputline, str3);
|
||||
write(outputline, str4);
|
||||
write(outputline, str5);
|
||||
writeline(output, outputline);
|
||||
end simfreqprint;
|
||||
|
||||
begin
|
||||
RESET <= '1';
|
||||
wait for (PER1*6);
|
||||
RESET <= '0';
|
||||
wait until LOCKED = '1';
|
||||
COUNTER_RESET <= '1';
|
||||
wait for (PER1*20);
|
||||
COUNTER_RESET <= '0';
|
||||
wait for (PER1*COUNT_PHASE);
|
||||
|
||||
|
||||
simtimeprint;
|
||||
end_of_sim <= '1';
|
||||
wait for 1 ps;
|
||||
report "Simulation Stopped." severity failure;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
-- Instantiation of the example design containing the clock
|
||||
-- network and sampling counters
|
||||
-----------------------------------------------------------
|
||||
dut : PLL_exdes
|
||||
generic map (
|
||||
TCQ => TCQ)
|
||||
port map
|
||||
(-- Clock in ports
|
||||
CLK_IN1 => CLK_IN1,
|
||||
-- Reset for logic in example design
|
||||
COUNTER_RESET => COUNTER_RESET,
|
||||
CLK_OUT => CLK_OUT,
|
||||
-- High bits of the counters
|
||||
COUNT => COUNT,
|
||||
-- Status and control signals
|
||||
RESET => RESET,
|
||||
LOCKED => LOCKED);
|
||||
|
||||
-- Freq Check
|
||||
|
||||
end test;
|
||||
+220
@@ -0,0 +1,220 @@
|
||||
-- file: PLL_tb.vhd
|
||||
--
|
||||
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Clocking wizard demonstration testbench
|
||||
------------------------------------------------------------------------------
|
||||
-- This demonstration testbench instantiates the example design for the
|
||||
-- clocking wizard. Input clocks are toggled, which cause the clocking
|
||||
-- network to lock and the counters to increment.
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
|
||||
library std;
|
||||
use std.textio.all;
|
||||
|
||||
library work;
|
||||
use work.all;
|
||||
|
||||
entity PLL_tb is
|
||||
end PLL_tb;
|
||||
|
||||
architecture test of PLL_tb is
|
||||
|
||||
-- Clock to Q delay of 100 ps
|
||||
constant TCQ : time := 100 ps;
|
||||
-- timescale is 1ps
|
||||
constant ONE_NS : time := 1 ns;
|
||||
-- how many cycles to run
|
||||
constant COUNT_PHASE : integer := 1024 + 1;
|
||||
|
||||
|
||||
-- we'll be using the period in many locations
|
||||
constant PER1 : time := 62.5 ns;
|
||||
|
||||
|
||||
-- Declare the input clock signals
|
||||
signal CLK_IN1 : std_logic := '1';
|
||||
-- The high bit of the sampling counter
|
||||
signal COUNT : std_logic;
|
||||
-- Status and control signals
|
||||
signal RESET : std_logic := '0';
|
||||
signal LOCKED : std_logic;
|
||||
signal COUNTER_RESET : std_logic := '0';
|
||||
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
|
||||
-- signal defined to stop mti simulation without severity failure in the report
|
||||
signal end_of_sim : std_logic := '0';
|
||||
signal CLK_OUT : std_logic_vector(1 downto 1);
|
||||
--Freq Check using the M & D values setting and actual Frequency generated
|
||||
|
||||
component PLL_exdes
|
||||
port
|
||||
(-- Clock in ports
|
||||
CLK_IN1 : in std_logic;
|
||||
-- Reset that only drives logic in example design
|
||||
COUNTER_RESET : in std_logic;
|
||||
CLK_OUT : out std_logic_vector(1 downto 1) ;
|
||||
-- High bits of counters driven by clocks
|
||||
COUNT : out std_logic;
|
||||
-- Status and control signals
|
||||
RESET : in std_logic;
|
||||
LOCKED : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
|
||||
-- Input clock generation
|
||||
--------------------------------------
|
||||
process begin
|
||||
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
|
||||
end process;
|
||||
|
||||
-- Test sequence
|
||||
process
|
||||
|
||||
procedure simtimeprint is
|
||||
variable outline : line;
|
||||
begin
|
||||
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
|
||||
write(outline, NOW/PER1);
|
||||
write(outline, string'(" ns"));
|
||||
writeline(output,outline);
|
||||
end simtimeprint;
|
||||
|
||||
procedure simfreqprint (period : time; clk_num : integer) is
|
||||
variable outputline : LINE;
|
||||
variable str1 : string(1 to 16);
|
||||
variable str2 : integer;
|
||||
variable str3 : string(1 to 2);
|
||||
variable str4 : integer;
|
||||
variable str5 : string(1 to 4);
|
||||
begin
|
||||
str1 := "Freq of CLK_OUT(";
|
||||
str2 := clk_num;
|
||||
str3 := ") ";
|
||||
str4 := 1000000 ps/period ;
|
||||
str5 := " MHz" ;
|
||||
write(outputline, str1 );
|
||||
write(outputline, str2);
|
||||
write(outputline, str3);
|
||||
write(outputline, str4);
|
||||
write(outputline, str5);
|
||||
writeline(output, outputline);
|
||||
end simfreqprint;
|
||||
|
||||
begin
|
||||
report "Timing checks are not valid" severity note;
|
||||
RESET <= '1';
|
||||
wait for (PER1*6);
|
||||
RESET <= '0';
|
||||
wait until LOCKED = '1';
|
||||
wait for (PER1*20);
|
||||
COUNTER_RESET <= '1';
|
||||
wait for (PER1*19.5);
|
||||
COUNTER_RESET <= '0';
|
||||
wait for (PER1*1);
|
||||
report "Timing checks are valid" severity note;
|
||||
wait for (PER1*COUNT_PHASE);
|
||||
|
||||
|
||||
simtimeprint;
|
||||
end_of_sim <= '1';
|
||||
wait for 1 ps;
|
||||
report "Simulation Stopped." severity failure;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
process (CLK_IN1)
|
||||
procedure simtimeprint is
|
||||
variable outline : line;
|
||||
begin
|
||||
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
|
||||
write(outline, NOW/PER1);
|
||||
write(outline, string'(" ns"));
|
||||
writeline(output,outline);
|
||||
end simtimeprint;
|
||||
begin
|
||||
if (CLK_IN1'event and CLK_IN1='1') then
|
||||
timeout_counter <= timeout_counter + '1';
|
||||
if (timeout_counter = "10000000000000") then
|
||||
if (LOCKED /= '1') then
|
||||
simtimeprint;
|
||||
report "NO LOCK signal" severity failure;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Instantiation of the example design containing the clock
|
||||
-- network and sampling counters
|
||||
-----------------------------------------------------------
|
||||
dut : PLL_exdes
|
||||
port map
|
||||
(-- Clock in ports
|
||||
CLK_IN1 => CLK_IN1,
|
||||
-- Reset for logic in example design
|
||||
COUNTER_RESET => COUNTER_RESET,
|
||||
CLK_OUT => CLK_OUT,
|
||||
-- High bits of the counters
|
||||
COUNT => COUNT,
|
||||
-- Status and control signals
|
||||
RESET => RESET,
|
||||
LOCKED => LOCKED);
|
||||
|
||||
-- Freq Check
|
||||
|
||||
end test;
|
||||
+53
@@ -0,0 +1,53 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="SampleMemory.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="SampleMemory.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="SampleMemory.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="SampleMemory.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1654646662" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1654646662">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5346285223313661724" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7774384757506685939" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6611130985775322842" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
+149
@@ -0,0 +1,149 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2022 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file SampleMemory.vhd when simulating
|
||||
-- the core, SampleMemory. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
LIBRARY XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY SampleMemory IS
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END SampleMemory;
|
||||
|
||||
ARCHITECTURE SampleMemory_a OF SampleMemory IS
|
||||
-- synthesis translate_off
|
||||
COMPONENT wrapped_SampleMemory
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_SampleMemory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
|
||||
GENERIC MAP (
|
||||
c_addra_width => 11,
|
||||
c_addrb_width => 11,
|
||||
c_algorithm => 1,
|
||||
c_axi_id_width => 4,
|
||||
c_axi_slave_type => 0,
|
||||
c_axi_type => 1,
|
||||
c_byte_size => 9,
|
||||
c_common_clk => 0,
|
||||
c_default_data => "0",
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_enable_32bit_address => 0,
|
||||
c_family => "spartan6",
|
||||
c_has_axi_id => 0,
|
||||
c_has_ena => 0,
|
||||
c_has_enb => 0,
|
||||
c_has_injecterr => 0,
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_has_regcea => 0,
|
||||
c_has_regceb => 0,
|
||||
c_has_rsta => 0,
|
||||
c_has_rstb => 0,
|
||||
c_has_softecc_input_regs_a => 0,
|
||||
c_has_softecc_output_regs_b => 0,
|
||||
c_init_file => "BlankString",
|
||||
c_init_file_name => "no_coe_file_loaded",
|
||||
c_inita_val => "0",
|
||||
c_initb_val => "0",
|
||||
c_interface_type => 0,
|
||||
c_load_init_file => 0,
|
||||
c_mem_type => 1,
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_prim_type => 1,
|
||||
c_read_depth_a => 2048,
|
||||
c_read_depth_b => 2048,
|
||||
c_read_width_a => 8,
|
||||
c_read_width_b => 8,
|
||||
c_rst_priority_a => "CE",
|
||||
c_rst_priority_b => "CE",
|
||||
c_rst_type => "SYNC",
|
||||
c_rstram_a => 0,
|
||||
c_rstram_b => 0,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_use_bram_block => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_use_byte_web => 0,
|
||||
c_use_default_data => 0,
|
||||
c_use_ecc => 0,
|
||||
c_use_softecc => 0,
|
||||
c_wea_width => 1,
|
||||
c_web_width => 1,
|
||||
c_write_depth_a => 2048,
|
||||
c_write_depth_b => 2048,
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_write_width_a => 8,
|
||||
c_write_width_b => 8,
|
||||
c_xdevicefamily => "spartan6"
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_SampleMemory
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
wea => wea,
|
||||
addra => addra,
|
||||
dina => dina,
|
||||
clkb => clkb,
|
||||
addrb => addrb,
|
||||
doutb => doutb
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END SampleMemory_a;
|
||||
+53
@@ -0,0 +1,53 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="SinCos.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="SinCos.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="SinCos.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="SinCos.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1588801396" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1588801396">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6318242672365869964" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6896205234688070757" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="2493898235901227214" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
+106
@@ -0,0 +1,106 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2020 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file SinCos.vhd when simulating
|
||||
-- the core, SinCos. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
LIBRARY XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY SinCos IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END SinCos;
|
||||
|
||||
ARCHITECTURE SinCos_a OF SinCos IS
|
||||
-- synthesis translate_off
|
||||
COMPONENT wrapped_SinCos
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_SinCos USE ENTITY XilinxCoreLib.dds_compiler_v4_0(behavioral)
|
||||
GENERIC MAP (
|
||||
c_accumulator_width => 12,
|
||||
c_amplitude => 0,
|
||||
c_channels => 1,
|
||||
c_has_ce => 0,
|
||||
c_has_channel_index => 0,
|
||||
c_has_phase_out => 0,
|
||||
c_has_phasegen => 0,
|
||||
c_has_rdy => 0,
|
||||
c_has_rfd => 0,
|
||||
c_has_sclr => 0,
|
||||
c_has_sincos => 1,
|
||||
c_latency => -1,
|
||||
c_mem_type => 1,
|
||||
c_negative_cosine => 0,
|
||||
c_negative_sine => 0,
|
||||
c_noise_shaping => 0,
|
||||
c_optimise_goal => 0,
|
||||
c_output_width => 16,
|
||||
c_outputs_required => 2,
|
||||
c_phase_angle_width => 12,
|
||||
c_phase_increment => 2,
|
||||
c_phase_increment_value => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
|
||||
c_phase_offset => 0,
|
||||
c_phase_offset_value => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
|
||||
c_por_mode => 0,
|
||||
c_use_dsp48 => 0,
|
||||
c_xdevicefamily => "spartan6"
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_SinCos
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
phase_in => phase_in,
|
||||
cosine => cosine,
|
||||
sine => sine
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END SinCos_a;
|
||||
+53
@@ -0,0 +1,53 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="SweepConfigMem.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="SweepConfigMem.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="SweepConfigMem.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="SweepConfigMem.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1588801396" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1588801396">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4981023380131313696" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7428936449477002095" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3308610090153173282" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
+152
@@ -0,0 +1,152 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2020 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file SweepConfigMem.vhd when simulating
|
||||
-- the core, SweepConfigMem. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
LIBRARY XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY SweepConfigMem IS
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
ena : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
|
||||
);
|
||||
END SweepConfigMem;
|
||||
|
||||
ARCHITECTURE SweepConfigMem_a OF SweepConfigMem IS
|
||||
-- synthesis translate_off
|
||||
COMPONENT wrapped_SweepConfigMem
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
ena : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_SweepConfigMem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
|
||||
GENERIC MAP (
|
||||
c_addra_width => 13,
|
||||
c_addrb_width => 13,
|
||||
c_algorithm => 1,
|
||||
c_axi_id_width => 4,
|
||||
c_axi_slave_type => 0,
|
||||
c_axi_type => 1,
|
||||
c_byte_size => 9,
|
||||
c_common_clk => 0,
|
||||
c_default_data => "0",
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_enable_32bit_address => 0,
|
||||
c_family => "spartan6",
|
||||
c_has_axi_id => 0,
|
||||
c_has_ena => 1,
|
||||
c_has_enb => 0,
|
||||
c_has_injecterr => 0,
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_has_regcea => 0,
|
||||
c_has_regceb => 0,
|
||||
c_has_rsta => 0,
|
||||
c_has_rstb => 0,
|
||||
c_has_softecc_input_regs_a => 0,
|
||||
c_has_softecc_output_regs_b => 0,
|
||||
c_init_file => "BlankString",
|
||||
c_init_file_name => "no_coe_file_loaded",
|
||||
c_inita_val => "0",
|
||||
c_initb_val => "0",
|
||||
c_interface_type => 0,
|
||||
c_load_init_file => 0,
|
||||
c_mem_type => 1,
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_prim_type => 1,
|
||||
c_read_depth_a => 4501,
|
||||
c_read_depth_b => 4501,
|
||||
c_read_width_a => 96,
|
||||
c_read_width_b => 96,
|
||||
c_rst_priority_a => "CE",
|
||||
c_rst_priority_b => "CE",
|
||||
c_rst_type => "SYNC",
|
||||
c_rstram_a => 0,
|
||||
c_rstram_b => 0,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_use_bram_block => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_use_byte_web => 0,
|
||||
c_use_default_data => 0,
|
||||
c_use_ecc => 0,
|
||||
c_use_softecc => 0,
|
||||
c_wea_width => 1,
|
||||
c_web_width => 1,
|
||||
c_write_depth_a => 4501,
|
||||
c_write_depth_b => 4501,
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_write_width_a => 96,
|
||||
c_write_width_b => 96,
|
||||
c_xdevicefamily => "spartan6"
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_SweepConfigMem
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
ena => ena,
|
||||
wea => wea,
|
||||
addra => addra,
|
||||
dina => dina,
|
||||
clkb => clkb,
|
||||
addrb => addrb,
|
||||
doutb => doutb
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END SweepConfigMem_a;
|
||||
+61
@@ -0,0 +1,61 @@
|
||||
################################################################################
|
||||
#
|
||||
# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Tx Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
NET "CLKA" TNM_NET = "CLKA";
|
||||
|
||||
NET "CLKB" TNM_NET = "CLKB";
|
||||
|
||||
TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ;
|
||||
|
||||
TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ;
|
||||
|
||||
################################################################################
|
||||
+182
@@ -0,0 +1,182 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: SweepConfigMem_exdes.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the actual BMG core wrapper.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: August 31, 2005 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY UNISIM;
|
||||
USE UNISIM.VCOMPONENTS.ALL;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
ENTITY SweepConfigMem_exdes IS
|
||||
PORT (
|
||||
--Inputs - Port A
|
||||
ENA : IN STD_LOGIC; --opt port
|
||||
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
|
||||
DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
|
||||
CLKA : IN STD_LOGIC;
|
||||
|
||||
|
||||
--Inputs - Port B
|
||||
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
CLKB : IN STD_LOGIC
|
||||
|
||||
);
|
||||
|
||||
END SweepConfigMem_exdes;
|
||||
|
||||
|
||||
ARCHITECTURE xilinx OF SweepConfigMem_exdes IS
|
||||
|
||||
COMPONENT BUFG IS
|
||||
PORT (
|
||||
I : IN STD_ULOGIC;
|
||||
O : OUT STD_ULOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT SweepConfigMem IS
|
||||
PORT (
|
||||
--Port A
|
||||
ENA : IN STD_LOGIC; --opt port
|
||||
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
|
||||
DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
|
||||
|
||||
CLKA : IN STD_LOGIC;
|
||||
|
||||
|
||||
--Port B
|
||||
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
CLKB : IN STD_LOGIC
|
||||
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL CLKA_buf : STD_LOGIC;
|
||||
SIGNAL CLKB_buf : STD_LOGIC;
|
||||
SIGNAL S_ACLK_buf : STD_LOGIC;
|
||||
|
||||
BEGIN
|
||||
|
||||
bufg_A : BUFG
|
||||
PORT MAP (
|
||||
I => CLKA,
|
||||
O => CLKA_buf
|
||||
);
|
||||
|
||||
bufg_B : BUFG
|
||||
PORT MAP (
|
||||
I => CLKB,
|
||||
O => CLKB_buf
|
||||
);
|
||||
|
||||
|
||||
bmg0 : SweepConfigMem
|
||||
PORT MAP (
|
||||
--Port A
|
||||
ENA => ENA,
|
||||
|
||||
WEA => WEA,
|
||||
ADDRA => ADDRA,
|
||||
|
||||
DINA => DINA,
|
||||
|
||||
CLKA => CLKA_buf,
|
||||
|
||||
|
||||
--Port B
|
||||
ADDRB => ADDRB,
|
||||
DOUTB => DOUTB,
|
||||
CLKB => CLKB_buf
|
||||
|
||||
);
|
||||
|
||||
END xilinx;
|
||||
+277
@@ -0,0 +1,277 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7.1 Core - Top-level wrapper
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: SweepConfigMem_prod.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the top-level BMG wrapper (over BMG core).
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: August 31, 2005 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Configured Core Parameter Values:
|
||||
-- (Refer to the SIM Parameters table in the datasheet for more information on
|
||||
-- the these parameters.)
|
||||
-- C_FAMILY : spartan6
|
||||
-- C_XDEVICEFAMILY : spartan6
|
||||
-- C_INTERFACE_TYPE : 0
|
||||
-- C_ENABLE_32BIT_ADDRESS : 0
|
||||
-- C_AXI_TYPE : 1
|
||||
-- C_AXI_SLAVE_TYPE : 0
|
||||
-- C_AXI_ID_WIDTH : 4
|
||||
-- C_MEM_TYPE : 1
|
||||
-- C_BYTE_SIZE : 9
|
||||
-- C_ALGORITHM : 1
|
||||
-- C_PRIM_TYPE : 1
|
||||
-- C_LOAD_INIT_FILE : 0
|
||||
-- C_INIT_FILE_NAME : no_coe_file_loaded
|
||||
-- C_USE_DEFAULT_DATA : 0
|
||||
-- C_DEFAULT_DATA : 0
|
||||
-- C_RST_TYPE : SYNC
|
||||
-- C_HAS_RSTA : 0
|
||||
-- C_RST_PRIORITY_A : CE
|
||||
-- C_RSTRAM_A : 0
|
||||
-- C_INITA_VAL : 0
|
||||
-- C_HAS_ENA : 1
|
||||
-- C_HAS_REGCEA : 0
|
||||
-- C_USE_BYTE_WEA : 0
|
||||
-- C_WEA_WIDTH : 1
|
||||
-- C_WRITE_MODE_A : WRITE_FIRST
|
||||
-- C_WRITE_WIDTH_A : 96
|
||||
-- C_READ_WIDTH_A : 96
|
||||
-- C_WRITE_DEPTH_A : 4501
|
||||
-- C_READ_DEPTH_A : 4501
|
||||
-- C_ADDRA_WIDTH : 13
|
||||
-- C_HAS_RSTB : 0
|
||||
-- C_RST_PRIORITY_B : CE
|
||||
-- C_RSTRAM_B : 0
|
||||
-- C_INITB_VAL : 0
|
||||
-- C_HAS_ENB : 0
|
||||
-- C_HAS_REGCEB : 0
|
||||
-- C_USE_BYTE_WEB : 0
|
||||
-- C_WEB_WIDTH : 1
|
||||
-- C_WRITE_MODE_B : WRITE_FIRST
|
||||
-- C_WRITE_WIDTH_B : 96
|
||||
-- C_READ_WIDTH_B : 96
|
||||
-- C_WRITE_DEPTH_B : 4501
|
||||
-- C_READ_DEPTH_B : 4501
|
||||
-- C_ADDRB_WIDTH : 13
|
||||
-- C_HAS_MEM_OUTPUT_REGS_A : 0
|
||||
-- C_HAS_MEM_OUTPUT_REGS_B : 0
|
||||
-- C_HAS_MUX_OUTPUT_REGS_A : 0
|
||||
-- C_HAS_MUX_OUTPUT_REGS_B : 0
|
||||
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
|
||||
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
|
||||
-- C_MUX_PIPELINE_STAGES : 0
|
||||
-- C_USE_ECC : 0
|
||||
-- C_USE_SOFTECC : 0
|
||||
-- C_HAS_INJECTERR : 0
|
||||
-- C_SIM_COLLISION_CHECK : ALL
|
||||
-- C_COMMON_CLK : 0
|
||||
-- C_DISABLE_WARN_BHV_COLL : 0
|
||||
-- C_DISABLE_WARN_BHV_RANGE : 0
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY UNISIM;
|
||||
USE UNISIM.VCOMPONENTS.ALL;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
ENTITY SweepConfigMem_prod IS
|
||||
PORT (
|
||||
--Port A
|
||||
CLKA : IN STD_LOGIC;
|
||||
RSTA : IN STD_LOGIC; --opt port
|
||||
ENA : IN STD_LOGIC; --optional port
|
||||
REGCEA : IN STD_LOGIC; --optional port
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
|
||||
--Port B
|
||||
CLKB : IN STD_LOGIC;
|
||||
RSTB : IN STD_LOGIC; --opt port
|
||||
ENB : IN STD_LOGIC; --optional port
|
||||
REGCEB : IN STD_LOGIC; --optional port
|
||||
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
DINB : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
|
||||
--ECC
|
||||
INJECTSBITERR : IN STD_LOGIC; --optional port
|
||||
INJECTDBITERR : IN STD_LOGIC; --optional port
|
||||
SBITERR : OUT STD_LOGIC; --optional port
|
||||
DBITERR : OUT STD_LOGIC; --optional port
|
||||
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
|
||||
-- AXI BMG Input and Output Port Declarations
|
||||
|
||||
-- AXI Global Signals
|
||||
S_ACLK : IN STD_LOGIC;
|
||||
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_WLAST : IN STD_LOGIC;
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
S_AXI_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
|
||||
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Slave Read (Write side)
|
||||
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RLAST : OUT STD_LOGIC;
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Sideband Signals
|
||||
S_AXI_INJECTSBITERR : IN STD_LOGIC;
|
||||
S_AXI_INJECTDBITERR : IN STD_LOGIC;
|
||||
S_AXI_SBITERR : OUT STD_LOGIC;
|
||||
S_AXI_DBITERR : OUT STD_LOGIC;
|
||||
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
S_ARESETN : IN STD_LOGIC
|
||||
|
||||
|
||||
);
|
||||
|
||||
END SweepConfigMem_prod;
|
||||
|
||||
|
||||
ARCHITECTURE xilinx OF SweepConfigMem_prod IS
|
||||
|
||||
COMPONENT SweepConfigMem_exdes IS
|
||||
PORT (
|
||||
--Port A
|
||||
ENA : IN STD_LOGIC; --opt port
|
||||
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
|
||||
DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
|
||||
|
||||
CLKA : IN STD_LOGIC;
|
||||
|
||||
|
||||
--Port B
|
||||
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
CLKB : IN STD_LOGIC
|
||||
|
||||
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
bmg0 : SweepConfigMem_exdes
|
||||
PORT MAP (
|
||||
--Port A
|
||||
ENA => ENA,
|
||||
|
||||
WEA => WEA,
|
||||
ADDRA => ADDRA,
|
||||
|
||||
DINA => DINA,
|
||||
|
||||
CLKA => CLKA,
|
||||
|
||||
--Port B
|
||||
ADDRB => ADDRB,
|
||||
DOUTB => DOUTB,
|
||||
CLKB => CLKB
|
||||
|
||||
|
||||
|
||||
);
|
||||
END xilinx;
|
||||
+329
@@ -0,0 +1,329 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: SweepConfigMem_synth.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Synthesizable Testbench
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE IEEE.STD_LOGIC_MISC.ALL;
|
||||
|
||||
LIBRARY STD;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
--LIBRARY unisim;
|
||||
--USE unisim.vcomponents.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
ENTITY SweepConfigMem_synth IS
|
||||
PORT(
|
||||
CLK_IN : IN STD_LOGIC;
|
||||
CLKB_IN : IN STD_LOGIC;
|
||||
RESET_IN : IN STD_LOGIC;
|
||||
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
ARCHITECTURE SweepConfigMem_synth_ARCH OF SweepConfigMem_synth IS
|
||||
|
||||
|
||||
COMPONENT SweepConfigMem_exdes
|
||||
PORT (
|
||||
--Inputs - Port A
|
||||
ENA : IN STD_LOGIC; --opt port
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
CLKA : IN STD_LOGIC;
|
||||
|
||||
--Inputs - Port B
|
||||
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
CLKB : IN STD_LOGIC
|
||||
|
||||
);
|
||||
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
SIGNAL CLKA: STD_LOGIC := '0';
|
||||
SIGNAL RSTA: STD_LOGIC := '0';
|
||||
SIGNAL ENA: STD_LOGIC := '0';
|
||||
SIGNAL ENA_R: STD_LOGIC := '0';
|
||||
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINA: STD_LOGIC_VECTOR(95 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINA_R: STD_LOGIC_VECTOR(95 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL CLKB: STD_LOGIC := '0';
|
||||
SIGNAL RSTB: STD_LOGIC := '0';
|
||||
SIGNAL ADDRB: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DOUTB: STD_LOGIC_VECTOR(95 DOWNTO 0);
|
||||
SIGNAL CHECKER_EN : STD_LOGIC:='0';
|
||||
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
|
||||
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
|
||||
SIGNAL clk_in_i: STD_LOGIC;
|
||||
|
||||
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
|
||||
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
|
||||
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
|
||||
|
||||
SIGNAL clkb_in_i: STD_LOGIC;
|
||||
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
|
||||
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
|
||||
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
|
||||
SIGNAL ITER_R0 : STD_LOGIC := '0';
|
||||
SIGNAL ITER_R1 : STD_LOGIC := '0';
|
||||
SIGNAL ITER_R2 : STD_LOGIC := '0';
|
||||
|
||||
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
|
||||
BEGIN
|
||||
|
||||
-- clk_buf: bufg
|
||||
-- PORT map(
|
||||
-- i => CLK_IN,
|
||||
-- o => clk_in_i
|
||||
-- );
|
||||
clk_in_i <= CLK_IN;
|
||||
CLKA <= clk_in_i;
|
||||
|
||||
-- clkb_buf: bufg
|
||||
-- PORT map(
|
||||
-- i => CLKB_IN,
|
||||
-- o => clkb_in_i
|
||||
-- );
|
||||
clkb_in_i <= CLKB_IN;
|
||||
CLKB <= clkb_in_i;
|
||||
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
|
||||
|
||||
|
||||
PROCESS(clk_in_i)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(clk_in_i)) THEN
|
||||
RESET_SYNC_R1 <= RESET_IN;
|
||||
RESET_SYNC_R2 <= RESET_SYNC_R1;
|
||||
RESET_SYNC_R3 <= RESET_SYNC_R2;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
|
||||
|
||||
PROCESS(clkb_in_i)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(clkb_in_i)) THEN
|
||||
RESETB_SYNC_R1 <= RESET_IN;
|
||||
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
|
||||
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
ISSUE_FLAG_STATUS<= (OTHERS => '0');
|
||||
ELSE
|
||||
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
|
||||
|
||||
|
||||
|
||||
|
||||
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
|
||||
GENERIC MAP (
|
||||
WRITE_WIDTH => 96,
|
||||
READ_WIDTH => 96 )
|
||||
PORT MAP (
|
||||
CLK => clkb_in_i,
|
||||
RST => RSTB,
|
||||
EN => CHECKER_EN_R,
|
||||
DATA_IN => DOUTB,
|
||||
STATUS => ISSUE_FLAG(0)
|
||||
);
|
||||
|
||||
PROCESS(clkb_in_i)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(clkb_in_i)) THEN
|
||||
IF(RSTB='1') THEN
|
||||
CHECKER_EN_R <= '0';
|
||||
ELSE
|
||||
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
|
||||
PORT MAP(
|
||||
CLKA => clk_in_i,
|
||||
CLKB => clkb_in_i,
|
||||
TB_RST => RSTA,
|
||||
ADDRA => ADDRA,
|
||||
DINA => DINA,
|
||||
ENA => ENA,
|
||||
WEA => WEA,
|
||||
ADDRB => ADDRB,
|
||||
CHECK_DATA => CHECKER_EN
|
||||
);
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
STATUS(8) <= '0';
|
||||
iter_r2 <= '0';
|
||||
iter_r1 <= '0';
|
||||
iter_r0 <= '0';
|
||||
ELSE
|
||||
STATUS(8) <= iter_r2;
|
||||
iter_r2 <= iter_r1;
|
||||
iter_r1 <= iter_r0;
|
||||
iter_r0 <= STIMULUS_FLOW(8);
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
STIMULUS_FLOW <= (OTHERS => '0');
|
||||
ELSIF(WEA(0)='1') THEN
|
||||
STIMULUS_FLOW <= STIMULUS_FLOW+1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
ENA_R <= '0' AFTER 50 ns;
|
||||
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
|
||||
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
|
||||
|
||||
|
||||
ELSE
|
||||
ENA_R <= ENA AFTER 50 ns;
|
||||
WEA_R <= WEA AFTER 50 ns;
|
||||
DINA_R <= DINA AFTER 50 ns;
|
||||
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
|
||||
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
|
||||
ELSE
|
||||
ADDRA_R <= ADDRA AFTER 50 ns;
|
||||
ADDRB_R <= ADDRB AFTER 50 ns;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
BMG_PORT: SweepConfigMem_exdes PORT MAP (
|
||||
--Port A
|
||||
ENA => ENA_R,
|
||||
WEA => WEA_R,
|
||||
ADDRA => ADDRA_R,
|
||||
DINA => DINA_R,
|
||||
CLKA => CLKA,
|
||||
--Port B
|
||||
ADDRB => ADDRB_R,
|
||||
DOUTB => DOUTB,
|
||||
CLKB => CLKB
|
||||
|
||||
);
|
||||
END ARCHITECTURE;
|
||||
+142
@@ -0,0 +1,142 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Filename: SweepConfigMem_tb.vhd
|
||||
-- Description:
|
||||
-- Testbench Top
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
|
||||
ENTITY SweepConfigMem_tb IS
|
||||
END ENTITY;
|
||||
|
||||
|
||||
ARCHITECTURE SweepConfigMem_tb_ARCH OF SweepConfigMem_tb IS
|
||||
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
SIGNAL CLK : STD_LOGIC := '1';
|
||||
SIGNAL CLKB : STD_LOGIC := '1';
|
||||
SIGNAL RESET : STD_LOGIC;
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
CLK_GEN: PROCESS BEGIN
|
||||
CLK <= NOT CLK;
|
||||
WAIT FOR 100 NS;
|
||||
CLK <= NOT CLK;
|
||||
WAIT FOR 100 NS;
|
||||
END PROCESS;
|
||||
CLKB_GEN: PROCESS BEGIN
|
||||
CLKB <= NOT CLKB;
|
||||
WAIT FOR 100 NS;
|
||||
CLKB <= NOT CLKB;
|
||||
WAIT FOR 100 NS;
|
||||
END PROCESS;
|
||||
|
||||
RST_GEN: PROCESS BEGIN
|
||||
RESET <= '1';
|
||||
WAIT FOR 1000 NS;
|
||||
RESET <= '0';
|
||||
WAIT;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
--STOP_SIM: PROCESS BEGIN
|
||||
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
|
||||
-- ASSERT FALSE
|
||||
-- REPORT "END SIMULATION TIME REACHED"
|
||||
-- SEVERITY FAILURE;
|
||||
--END PROCESS;
|
||||
--
|
||||
PROCESS BEGIN
|
||||
WAIT UNTIL STATUS(8)='1';
|
||||
IF( STATUS(7 downto 0)/="0") THEN
|
||||
ASSERT false
|
||||
REPORT "Test Completed Successfully"
|
||||
SEVERITY NOTE;
|
||||
REPORT "Simulation Failed"
|
||||
SEVERITY FAILURE;
|
||||
ELSE
|
||||
ASSERT false
|
||||
REPORT "TEST PASS"
|
||||
SEVERITY NOTE;
|
||||
REPORT "Test Completed Successfully"
|
||||
SEVERITY FAILURE;
|
||||
END IF;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
SweepConfigMem_synth_inst:ENTITY work.SweepConfigMem_synth
|
||||
PORT MAP(
|
||||
CLK_IN => CLK,
|
||||
CLKB_IN => CLK,
|
||||
RESET_IN => RESET,
|
||||
STATUS => STATUS
|
||||
);
|
||||
|
||||
END ARCHITECTURE;
|
||||
+117
@@ -0,0 +1,117 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Address Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: addr_gen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Address Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
|
||||
ENTITY ADDR_GEN IS
|
||||
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
|
||||
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
|
||||
RST_INC : INTEGER := 0);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
LOAD :IN STD_LOGIC;
|
||||
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
|
||||
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
|
||||
);
|
||||
END ADDR_GEN;
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
|
||||
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
|
||||
BEGIN
|
||||
ADDR_OUT <= ADDR_TEMP;
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST='1') THEN
|
||||
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
|
||||
ELSE
|
||||
IF(EN='1') THEN
|
||||
IF(LOAD='1') THEN
|
||||
ADDR_TEMP <=LOAD_VALUE;
|
||||
ELSE
|
||||
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
|
||||
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
|
||||
ELSE
|
||||
ADDR_TEMP <= ADDR_TEMP + '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END ARCHITECTURE;
|
||||
+436
@@ -0,0 +1,436 @@
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: bmg_stim_gen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Stimulus Generation For SDP Configuration
|
||||
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
|
||||
-- simulation ends
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
USE IEEE.STD_LOGIC_MISC.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
|
||||
ENTITY REGISTER_LOGIC IS
|
||||
PORT(
|
||||
Q : OUT STD_LOGIC;
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
D : IN STD_LOGIC
|
||||
);
|
||||
END REGISTER_LOGIC;
|
||||
|
||||
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
|
||||
SIGNAL Q_O : STD_LOGIC :='0';
|
||||
BEGIN
|
||||
Q <= Q_O;
|
||||
FF_BEH: PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST ='1') THEN
|
||||
Q_O <= '0';
|
||||
ELSE
|
||||
Q_O <= D;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END REGISTER_ARCH;
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
USE IEEE.STD_LOGIC_MISC.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
|
||||
ENTITY BMG_STIM_GEN IS
|
||||
PORT (
|
||||
CLKA : IN STD_LOGIC;
|
||||
CLKB : IN STD_LOGIC;
|
||||
TB_RST : IN STD_LOGIC;
|
||||
ADDRA: OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
|
||||
DINA : OUT STD_LOGIC_VECTOR(95 DOWNTO 0) := (OTHERS => '0');
|
||||
ENA : OUT STD_LOGIC :='0';
|
||||
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
|
||||
ADDRB: OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
|
||||
CHECK_DATA: OUT STD_LOGIC:='0'
|
||||
);
|
||||
END BMG_STIM_GEN;
|
||||
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
|
||||
|
||||
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINA_INT : STD_LOGIC_VECTOR(95 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DO_WRITE : STD_LOGIC := '0';
|
||||
SIGNAL DO_READ : STD_LOGIC := '0';
|
||||
SIGNAL DO_READ_R : STD_LOGIC := '0';
|
||||
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
|
||||
SIGNAL PORTA_WR : STD_LOGIC:='0';
|
||||
SIGNAL COUNT : INTEGER :=0;
|
||||
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
|
||||
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
|
||||
SIGNAL PORTB_RD : STD_LOGIC:='0';
|
||||
SIGNAL COUNT_RD : INTEGER :=0;
|
||||
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
|
||||
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
|
||||
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
|
||||
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
|
||||
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
|
||||
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
|
||||
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
|
||||
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
|
||||
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
|
||||
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
|
||||
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
|
||||
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
|
||||
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
|
||||
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
|
||||
|
||||
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
|
||||
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((13 <= 13),WR_RD_DEEP_COUNT,
|
||||
((96/96)*WR_RD_DEEP_COUNT));
|
||||
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((13 <= 13),WR_RD_DEEP_COUNT,
|
||||
((96/96)*WR_RD_DEEP_COUNT));
|
||||
|
||||
BEGIN
|
||||
|
||||
ADDRA <= WRITE_ADDR(12 DOWNTO 0) ;
|
||||
DINA <= DINA_INT ;
|
||||
ADDRB <= READ_ADDR(12 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
|
||||
CHECK_DATA <= DO_READ;
|
||||
|
||||
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
|
||||
GENERIC MAP(
|
||||
C_MAX_DEPTH => 4501 ,
|
||||
RST_INC => 1 )
|
||||
PORT MAP(
|
||||
CLK => CLKB,
|
||||
RST => TB_RST,
|
||||
EN => DO_READ,
|
||||
LOAD => '0',
|
||||
LOAD_VALUE => ZERO,
|
||||
ADDR_OUT => READ_ADDR
|
||||
);
|
||||
|
||||
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
|
||||
GENERIC MAP(
|
||||
C_MAX_DEPTH => 4501,
|
||||
RST_INC => 1 )
|
||||
PORT MAP(
|
||||
CLK => CLKA,
|
||||
RST => TB_RST,
|
||||
EN => DO_WRITE,
|
||||
LOAD => '0',
|
||||
LOAD_VALUE => ZERO,
|
||||
ADDR_OUT => WRITE_ADDR
|
||||
);
|
||||
|
||||
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
|
||||
GENERIC MAP (
|
||||
DATA_GEN_WIDTH => 96,
|
||||
DOUT_WIDTH => 96 ,
|
||||
DATA_PART_CNT => 1,
|
||||
SEED => 2)
|
||||
PORT MAP (
|
||||
CLK => CLKA,
|
||||
RST => TB_RST,
|
||||
EN => DO_WRITE,
|
||||
DATA_OUT => DINA_INT
|
||||
);
|
||||
|
||||
|
||||
PORTA_WR_PROCESS: PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
PORTA_WR<='1';
|
||||
ELSE
|
||||
PORTA_WR<=PORTB_RD_COMPLETE;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PORTB_RD_PROCESS: PROCESS(CLKB)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKB)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
PORTB_RD<='0';
|
||||
ELSE
|
||||
PORTB_RD<=PORTA_WR_L2;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKB)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
LATCH_PORTB_RD_COMPLETE<='0';
|
||||
ELSIF(PORTB_RD_COMPLETE='1') THEN
|
||||
LATCH_PORTB_RD_COMPLETE <='1';
|
||||
ELSIF(PORTA_WR_HAPPENED='1') THEN
|
||||
LATCH_PORTB_RD_COMPLETE<='0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
PORTB_RD_L1 <='0';
|
||||
PORTB_RD_L2 <='0';
|
||||
ELSE
|
||||
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
|
||||
PORTB_RD_L2 <= PORTB_RD_L1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLKB)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKB)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
PORTA_WR_R1 <='0';
|
||||
PORTA_WR_R2 <='0';
|
||||
ELSE
|
||||
PORTA_WR_R1 <= PORTA_WR;
|
||||
PORTA_WR_R2 <= PORTA_WR_R1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PORTA_WR_HAPPENED <= PORTA_WR_R2;
|
||||
|
||||
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
LATCH_PORTA_WR_COMPLETE<='0';
|
||||
ELSIF(PORTA_WR_COMPLETE='1') THEN
|
||||
LATCH_PORTA_WR_COMPLETE <='1';
|
||||
--ELSIF(PORTB_RD_HAPPENED='1') THEN
|
||||
ELSE
|
||||
LATCH_PORTA_WR_COMPLETE<='0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLKB)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKB)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
PORTA_WR_L1 <='0';
|
||||
PORTA_WR_L2 <='0';
|
||||
ELSE
|
||||
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
|
||||
PORTA_WR_L2 <= PORTA_WR_L1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
PORTB_RD_R1 <='0';
|
||||
PORTB_RD_R2 <='0';
|
||||
ELSE
|
||||
PORTB_RD_R1 <= PORTB_RD;
|
||||
PORTB_RD_R2 <= PORTB_RD_R1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PORTB_RD_HAPPENED <= PORTB_RD_R2;
|
||||
|
||||
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
|
||||
|
||||
start_rd_counter: process(clkb)
|
||||
begin
|
||||
if(rising_edge(clkb)) then
|
||||
if(tb_rst='1') then
|
||||
incr_rd_cnt <= '0';
|
||||
elsif(portb_rd ='1') then
|
||||
incr_rd_cnt <='1';
|
||||
elsif(portb_rd_complete='1') then
|
||||
incr_rd_cnt <='0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
RD_COUNTER: process(clkb)
|
||||
begin
|
||||
if(rising_edge(clkb)) then
|
||||
if(tb_rst='1') then
|
||||
count_rd <= 0;
|
||||
elsif(incr_rd_cnt='1') then
|
||||
count_rd<=count_rd+1;
|
||||
end if;
|
||||
--if(count_rd=(wr_rd_deep_count)) then
|
||||
if(count_rd=(RD_DEEP_COUNT)) then
|
||||
count_rd<=0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
|
||||
|
||||
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
|
||||
|
||||
start_counter: process(clka)
|
||||
begin
|
||||
if(rising_edge(clka)) then
|
||||
if(tb_rst='1') then
|
||||
incr_wr_cnt <= '0';
|
||||
elsif(porta_wr ='1') then
|
||||
incr_wr_cnt <='1';
|
||||
elsif(porta_wr_complete='1') then
|
||||
incr_wr_cnt <='0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
COUNTER: process(clka)
|
||||
begin
|
||||
if(rising_edge(clka)) then
|
||||
if(tb_rst='1') then
|
||||
count <= 0;
|
||||
elsif(incr_wr_cnt='1') then
|
||||
count<=count+1;
|
||||
end if;
|
||||
if(count=(WR_DEEP_COUNT)) then
|
||||
count<=0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
|
||||
|
||||
|
||||
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
|
||||
BEGIN
|
||||
DFF_RIGHT: IF I=0 GENERATE
|
||||
BEGIN
|
||||
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
|
||||
PORT MAP(
|
||||
Q => DO_READ_REG(0),
|
||||
CLK => CLKB,
|
||||
RST => TB_RST,
|
||||
D => DO_READ
|
||||
);
|
||||
END GENERATE DFF_RIGHT;
|
||||
|
||||
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
|
||||
BEGIN
|
||||
SHIFT_INST: ENTITY work.REGISTER_LOGIC
|
||||
PORT MAP(
|
||||
Q => DO_READ_REG(I),
|
||||
CLK =>CLKB,
|
||||
RST =>TB_RST,
|
||||
D =>DO_READ_REG(I-1)
|
||||
);
|
||||
END GENERATE DFF_OTHERS;
|
||||
END GENERATE BEGIN_SHIFT_REG;
|
||||
|
||||
REGCE_PROCESS: PROCESS(CLKB)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKB)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
DO_READ_R <= '0';
|
||||
ELSE
|
||||
DO_READ_R <= DO_READ;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
ENA <= DO_WRITE ;
|
||||
|
||||
WEA(0) <= DO_WRITE ;
|
||||
|
||||
|
||||
END ARCHITECTURE;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
+200
@@ -0,0 +1,200 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Testbench Package
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: bmg_tb_pkg.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- BMG Testbench Package files
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
PACKAGE BMG_TB_PKG IS
|
||||
|
||||
FUNCTION DIVROUNDUP (
|
||||
DATA_VALUE : INTEGER;
|
||||
DIVISOR : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC_VECTOR;
|
||||
FALSE_CASE : STD_LOGIC_VECTOR)
|
||||
RETURN STD_LOGIC_VECTOR;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STRING;
|
||||
FALSE_CASE :STRING)
|
||||
RETURN STRING;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC;
|
||||
FALSE_CASE :STD_LOGIC)
|
||||
RETURN STD_LOGIC;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : INTEGER;
|
||||
FALSE_CASE : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION LOG2ROUNDUP (
|
||||
DATA_VALUE : INTEGER)
|
||||
RETURN INTEGER;
|
||||
|
||||
END BMG_TB_PKG;
|
||||
|
||||
PACKAGE BODY BMG_TB_PKG IS
|
||||
|
||||
FUNCTION DIVROUNDUP (
|
||||
DATA_VALUE : INTEGER;
|
||||
DIVISOR : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE DIV : INTEGER;
|
||||
BEGIN
|
||||
DIV := DATA_VALUE/DIVISOR;
|
||||
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
|
||||
DIV := DIV+1;
|
||||
END IF;
|
||||
RETURN DIV;
|
||||
END DIVROUNDUP;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC_VECTOR;
|
||||
FALSE_CASE : STD_LOGIC_VECTOR)
|
||||
RETURN STD_LOGIC_VECTOR IS
|
||||
BEGIN
|
||||
IF NOT CONDITION THEN
|
||||
RETURN FALSE_CASE;
|
||||
ELSE
|
||||
RETURN TRUE_CASE;
|
||||
END IF;
|
||||
END IF_THEN_ELSE;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC;
|
||||
FALSE_CASE : STD_LOGIC)
|
||||
RETURN STD_LOGIC IS
|
||||
BEGIN
|
||||
IF NOT CONDITION THEN
|
||||
RETURN FALSE_CASE;
|
||||
ELSE
|
||||
RETURN TRUE_CASE;
|
||||
END IF;
|
||||
END IF_THEN_ELSE;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : INTEGER;
|
||||
FALSE_CASE : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE RETVAL : INTEGER := 0;
|
||||
BEGIN
|
||||
IF CONDITION=FALSE THEN
|
||||
RETVAL:=FALSE_CASE;
|
||||
ELSE
|
||||
RETVAL:=TRUE_CASE;
|
||||
END IF;
|
||||
RETURN RETVAL;
|
||||
END IF_THEN_ELSE;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STRING;
|
||||
FALSE_CASE : STRING)
|
||||
RETURN STRING IS
|
||||
BEGIN
|
||||
IF NOT CONDITION THEN
|
||||
RETURN FALSE_CASE;
|
||||
ELSE
|
||||
RETURN TRUE_CASE;
|
||||
END IF;
|
||||
END IF_THEN_ELSE;
|
||||
-------------------------------
|
||||
FUNCTION LOG2ROUNDUP (
|
||||
DATA_VALUE : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE WIDTH : INTEGER := 0;
|
||||
VARIABLE CNT : INTEGER := 1;
|
||||
BEGIN
|
||||
IF (DATA_VALUE <= 1) THEN
|
||||
WIDTH := 1;
|
||||
ELSE
|
||||
WHILE (CNT < DATA_VALUE) LOOP
|
||||
WIDTH := WIDTH + 1;
|
||||
CNT := CNT *2;
|
||||
END LOOP;
|
||||
END IF;
|
||||
RETURN WIDTH;
|
||||
END LOG2ROUNDUP;
|
||||
|
||||
END BMG_TB_PKG;
|
||||
+161
@@ -0,0 +1,161 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Checker
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: checker.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Checker
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
ENTITY CHECKER IS
|
||||
GENERIC ( WRITE_WIDTH : INTEGER :=32;
|
||||
READ_WIDTH : INTEGER :=32
|
||||
);
|
||||
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
|
||||
STATUS : OUT STD_LOGIC:= '0'
|
||||
);
|
||||
END CHECKER;
|
||||
|
||||
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
|
||||
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
|
||||
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
|
||||
SIGNAL EN_R : STD_LOGIC := '0';
|
||||
SIGNAL EN_2R : STD_LOGIC := '0';
|
||||
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
|
||||
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
|
||||
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
|
||||
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
|
||||
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
|
||||
SIGNAL ERR_HOLD : STD_LOGIC :='0';
|
||||
SIGNAL ERR_DET : STD_LOGIC :='0';
|
||||
BEGIN
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST= '1') THEN
|
||||
EN_R <= '0';
|
||||
EN_2R <= '0';
|
||||
DATA_IN_R <= (OTHERS=>'0');
|
||||
ELSE
|
||||
EN_R <= EN;
|
||||
EN_2R <= EN_R;
|
||||
DATA_IN_R <= DATA_IN;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
|
||||
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
|
||||
DOUT_WIDTH => READ_WIDTH,
|
||||
DATA_PART_CNT => DATA_PART_CNT,
|
||||
SEED => 2
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RST => RST,
|
||||
EN => EN_2R,
|
||||
DATA_OUT => EXPECTED_DATA
|
||||
);
|
||||
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(EN_2R='1') THEN
|
||||
IF(EXPECTED_DATA = DATA_IN_R) THEN
|
||||
ERR_DET<='0';
|
||||
ELSE
|
||||
ERR_DET<= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLK,RST)
|
||||
BEGIN
|
||||
IF(RST='1') THEN
|
||||
ERR_HOLD <= '0';
|
||||
ELSIF(RISING_EDGE(CLK)) THEN
|
||||
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
STATUS <= ERR_HOLD;
|
||||
|
||||
END ARCHITECTURE;
|
||||
|
||||
|
||||
|
||||
+140
@@ -0,0 +1,140 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Data Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: data_gen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Data Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
ENTITY DATA_GEN IS
|
||||
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
|
||||
DOUT_WIDTH : INTEGER := 32;
|
||||
DATA_PART_CNT : INTEGER := 1;
|
||||
SEED : INTEGER := 2
|
||||
);
|
||||
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
|
||||
);
|
||||
END DATA_GEN;
|
||||
|
||||
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
|
||||
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
|
||||
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
|
||||
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
|
||||
SIGNAL LOCAL_CNT : INTEGER :=1;
|
||||
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
|
||||
BEGIN
|
||||
|
||||
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
|
||||
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
|
||||
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
|
||||
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE (CLK)) THEN
|
||||
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
|
||||
LOCAL_CNT <=1;
|
||||
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
|
||||
IF(LOCAL_CNT = 1) THEN
|
||||
LOCAL_CNT <= LOCAL_CNT+1;
|
||||
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
|
||||
LOCAL_CNT <= LOCAL_CNT+1;
|
||||
ELSE
|
||||
LOCAL_CNT <= 1;
|
||||
END IF;
|
||||
ELSE
|
||||
LOCAL_CNT <= 1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
|
||||
RAND_GEN_INST:ENTITY work.RANDOM
|
||||
GENERIC MAP(
|
||||
WIDTH => 8,
|
||||
SEED => (SEED+N)
|
||||
)
|
||||
PORT MAP(
|
||||
CLK => CLK,
|
||||
RST => RST,
|
||||
EN => DATA_GEN_I,
|
||||
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
|
||||
);
|
||||
END GENERATE RAND_GEN;
|
||||
|
||||
END ARCHITECTURE;
|
||||
|
||||
+112
@@ -0,0 +1,112 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Random Number Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: random.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Random Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
|
||||
ENTITY RANDOM IS
|
||||
GENERIC ( WIDTH : INTEGER := 32;
|
||||
SEED : INTEGER :=2
|
||||
);
|
||||
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
|
||||
);
|
||||
END RANDOM;
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF RANDOM IS
|
||||
BEGIN
|
||||
PROCESS(CLK)
|
||||
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
|
||||
VARIABLE TEMP : STD_LOGIC := '0';
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST='1') THEN
|
||||
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
|
||||
ELSE
|
||||
IF(EN = '1') THEN
|
||||
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
|
||||
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
|
||||
RAND_TEMP(0) := TEMP;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
RANDOM_NUM <= RAND_TEMP;
|
||||
END PROCESS;
|
||||
END ARCHITECTURE;
|
||||
+53
@@ -0,0 +1,53 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="VCO_Mem.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="VCO_Mem.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="VCO_Mem.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="VCO_Mem.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1654646662" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1654646662">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="9157515098364838426" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5794461498655324265" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5036159626982002724" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
+149
@@ -0,0 +1,149 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2022 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file VCO_Mem.vhd when simulating
|
||||
-- the core, VCO_Mem. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
LIBRARY XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY VCO_Mem IS
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END VCO_Mem;
|
||||
|
||||
ARCHITECTURE VCO_Mem_a OF VCO_Mem IS
|
||||
-- synthesis translate_off
|
||||
COMPONENT wrapped_VCO_Mem
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_VCO_Mem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
|
||||
GENERIC MAP (
|
||||
c_addra_width => 6,
|
||||
c_addrb_width => 6,
|
||||
c_algorithm => 1,
|
||||
c_axi_id_width => 4,
|
||||
c_axi_slave_type => 0,
|
||||
c_axi_type => 1,
|
||||
c_byte_size => 9,
|
||||
c_common_clk => 0,
|
||||
c_default_data => "0",
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_enable_32bit_address => 0,
|
||||
c_family => "spartan6",
|
||||
c_has_axi_id => 0,
|
||||
c_has_ena => 0,
|
||||
c_has_enb => 0,
|
||||
c_has_injecterr => 0,
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_has_regcea => 0,
|
||||
c_has_regceb => 0,
|
||||
c_has_rsta => 0,
|
||||
c_has_rstb => 0,
|
||||
c_has_softecc_input_regs_a => 0,
|
||||
c_has_softecc_output_regs_b => 0,
|
||||
c_init_file => "BlankString",
|
||||
c_init_file_name => "no_coe_file_loaded",
|
||||
c_inita_val => "0",
|
||||
c_initb_val => "0",
|
||||
c_interface_type => 0,
|
||||
c_load_init_file => 0,
|
||||
c_mem_type => 1,
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_prim_type => 1,
|
||||
c_read_depth_a => 64,
|
||||
c_read_depth_b => 64,
|
||||
c_read_width_a => 16,
|
||||
c_read_width_b => 16,
|
||||
c_rst_priority_a => "CE",
|
||||
c_rst_priority_b => "CE",
|
||||
c_rst_type => "SYNC",
|
||||
c_rstram_a => 0,
|
||||
c_rstram_b => 0,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_use_bram_block => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_use_byte_web => 0,
|
||||
c_use_default_data => 0,
|
||||
c_use_ecc => 0,
|
||||
c_use_softecc => 0,
|
||||
c_wea_width => 1,
|
||||
c_web_width => 1,
|
||||
c_write_depth_a => 64,
|
||||
c_write_depth_b => 64,
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_write_width_a => 16,
|
||||
c_write_width_b => 16,
|
||||
c_xdevicefamily => "spartan6"
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_VCO_Mem
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
wea => wea,
|
||||
addra => addra,
|
||||
dina => dina,
|
||||
clkb => clkb,
|
||||
addrb => addrb,
|
||||
doutb => doutb
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END VCO_Mem_a;
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="result_bram.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="result_bram.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="result_bram.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="result_bram.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
+149
@@ -0,0 +1,149 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2020 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file result_bram.vhd when simulating
|
||||
-- the core, result_bram. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
LIBRARY XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY result_bram IS
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(191 DOWNTO 0)
|
||||
);
|
||||
END result_bram;
|
||||
|
||||
ARCHITECTURE result_bram_a OF result_bram IS
|
||||
-- synthesis translate_off
|
||||
COMPONENT wrapped_result_bram
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(191 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_result_bram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
|
||||
GENERIC MAP (
|
||||
c_addra_width => 8,
|
||||
c_addrb_width => 8,
|
||||
c_algorithm => 1,
|
||||
c_axi_id_width => 4,
|
||||
c_axi_slave_type => 0,
|
||||
c_axi_type => 1,
|
||||
c_byte_size => 9,
|
||||
c_common_clk => 0,
|
||||
c_default_data => "0",
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_enable_32bit_address => 0,
|
||||
c_family => "spartan6",
|
||||
c_has_axi_id => 0,
|
||||
c_has_ena => 0,
|
||||
c_has_enb => 0,
|
||||
c_has_injecterr => 0,
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_has_regcea => 0,
|
||||
c_has_regceb => 0,
|
||||
c_has_rsta => 0,
|
||||
c_has_rstb => 0,
|
||||
c_has_softecc_input_regs_a => 0,
|
||||
c_has_softecc_output_regs_b => 0,
|
||||
c_init_file => "BlankString",
|
||||
c_init_file_name => "no_coe_file_loaded",
|
||||
c_inita_val => "0",
|
||||
c_initb_val => "0",
|
||||
c_interface_type => 0,
|
||||
c_load_init_file => 0,
|
||||
c_mem_type => 1,
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_prim_type => 1,
|
||||
c_read_depth_a => 256,
|
||||
c_read_depth_b => 256,
|
||||
c_read_width_a => 192,
|
||||
c_read_width_b => 192,
|
||||
c_rst_priority_a => "CE",
|
||||
c_rst_priority_b => "CE",
|
||||
c_rst_type => "SYNC",
|
||||
c_rstram_a => 0,
|
||||
c_rstram_b => 0,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_use_bram_block => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_use_byte_web => 0,
|
||||
c_use_default_data => 0,
|
||||
c_use_ecc => 0,
|
||||
c_use_softecc => 0,
|
||||
c_wea_width => 1,
|
||||
c_web_width => 1,
|
||||
c_write_depth_a => 256,
|
||||
c_write_depth_b => 256,
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_write_width_a => 192,
|
||||
c_write_width_b => 192,
|
||||
c_xdevicefamily => "spartan6"
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_result_bram
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
wea => wea,
|
||||
addra => addra,
|
||||
dina => dina,
|
||||
clkb => clkb,
|
||||
addrb => addrb,
|
||||
doutb => doutb
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END result_bram_a;
|
||||
+61
@@ -0,0 +1,61 @@
|
||||
################################################################################
|
||||
#
|
||||
# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Tx Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
NET "CLKA" TNM_NET = "CLKA";
|
||||
|
||||
NET "CLKB" TNM_NET = "CLKB";
|
||||
|
||||
TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ;
|
||||
|
||||
TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ;
|
||||
|
||||
################################################################################
|
||||
+179
@@ -0,0 +1,179 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: result_bram_exdes.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the actual BMG core wrapper.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: August 31, 2005 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY UNISIM;
|
||||
USE UNISIM.VCOMPONENTS.ALL;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
ENTITY result_bram_exdes IS
|
||||
PORT (
|
||||
--Inputs - Port A
|
||||
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
|
||||
DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
|
||||
CLKA : IN STD_LOGIC;
|
||||
|
||||
|
||||
--Inputs - Port B
|
||||
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
CLKB : IN STD_LOGIC
|
||||
|
||||
);
|
||||
|
||||
END result_bram_exdes;
|
||||
|
||||
|
||||
ARCHITECTURE xilinx OF result_bram_exdes IS
|
||||
|
||||
COMPONENT BUFG IS
|
||||
PORT (
|
||||
I : IN STD_ULOGIC;
|
||||
O : OUT STD_ULOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT result_bram IS
|
||||
PORT (
|
||||
--Port A
|
||||
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
|
||||
DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
|
||||
|
||||
CLKA : IN STD_LOGIC;
|
||||
|
||||
|
||||
--Port B
|
||||
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
CLKB : IN STD_LOGIC
|
||||
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL CLKA_buf : STD_LOGIC;
|
||||
SIGNAL CLKB_buf : STD_LOGIC;
|
||||
SIGNAL S_ACLK_buf : STD_LOGIC;
|
||||
|
||||
BEGIN
|
||||
|
||||
bufg_A : BUFG
|
||||
PORT MAP (
|
||||
I => CLKA,
|
||||
O => CLKA_buf
|
||||
);
|
||||
|
||||
bufg_B : BUFG
|
||||
PORT MAP (
|
||||
I => CLKB,
|
||||
O => CLKB_buf
|
||||
);
|
||||
|
||||
|
||||
bmg0 : result_bram
|
||||
PORT MAP (
|
||||
--Port A
|
||||
|
||||
WEA => WEA,
|
||||
ADDRA => ADDRA,
|
||||
|
||||
DINA => DINA,
|
||||
|
||||
CLKA => CLKA_buf,
|
||||
|
||||
|
||||
--Port B
|
||||
ADDRB => ADDRB,
|
||||
DOUTB => DOUTB,
|
||||
CLKB => CLKB_buf
|
||||
|
||||
);
|
||||
|
||||
END xilinx;
|
||||
+275
@@ -0,0 +1,275 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7.1 Core - Top-level wrapper
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: result_bram_prod.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the top-level BMG wrapper (over BMG core).
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: August 31, 2005 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Configured Core Parameter Values:
|
||||
-- (Refer to the SIM Parameters table in the datasheet for more information on
|
||||
-- the these parameters.)
|
||||
-- C_FAMILY : spartan6
|
||||
-- C_XDEVICEFAMILY : spartan6
|
||||
-- C_INTERFACE_TYPE : 0
|
||||
-- C_ENABLE_32BIT_ADDRESS : 0
|
||||
-- C_AXI_TYPE : 1
|
||||
-- C_AXI_SLAVE_TYPE : 0
|
||||
-- C_AXI_ID_WIDTH : 4
|
||||
-- C_MEM_TYPE : 1
|
||||
-- C_BYTE_SIZE : 9
|
||||
-- C_ALGORITHM : 1
|
||||
-- C_PRIM_TYPE : 1
|
||||
-- C_LOAD_INIT_FILE : 0
|
||||
-- C_INIT_FILE_NAME : no_coe_file_loaded
|
||||
-- C_USE_DEFAULT_DATA : 0
|
||||
-- C_DEFAULT_DATA : 0
|
||||
-- C_RST_TYPE : SYNC
|
||||
-- C_HAS_RSTA : 0
|
||||
-- C_RST_PRIORITY_A : CE
|
||||
-- C_RSTRAM_A : 0
|
||||
-- C_INITA_VAL : 0
|
||||
-- C_HAS_ENA : 0
|
||||
-- C_HAS_REGCEA : 0
|
||||
-- C_USE_BYTE_WEA : 0
|
||||
-- C_WEA_WIDTH : 1
|
||||
-- C_WRITE_MODE_A : WRITE_FIRST
|
||||
-- C_WRITE_WIDTH_A : 192
|
||||
-- C_READ_WIDTH_A : 192
|
||||
-- C_WRITE_DEPTH_A : 256
|
||||
-- C_READ_DEPTH_A : 256
|
||||
-- C_ADDRA_WIDTH : 8
|
||||
-- C_HAS_RSTB : 0
|
||||
-- C_RST_PRIORITY_B : CE
|
||||
-- C_RSTRAM_B : 0
|
||||
-- C_INITB_VAL : 0
|
||||
-- C_HAS_ENB : 0
|
||||
-- C_HAS_REGCEB : 0
|
||||
-- C_USE_BYTE_WEB : 0
|
||||
-- C_WEB_WIDTH : 1
|
||||
-- C_WRITE_MODE_B : WRITE_FIRST
|
||||
-- C_WRITE_WIDTH_B : 192
|
||||
-- C_READ_WIDTH_B : 192
|
||||
-- C_WRITE_DEPTH_B : 256
|
||||
-- C_READ_DEPTH_B : 256
|
||||
-- C_ADDRB_WIDTH : 8
|
||||
-- C_HAS_MEM_OUTPUT_REGS_A : 0
|
||||
-- C_HAS_MEM_OUTPUT_REGS_B : 0
|
||||
-- C_HAS_MUX_OUTPUT_REGS_A : 0
|
||||
-- C_HAS_MUX_OUTPUT_REGS_B : 0
|
||||
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
|
||||
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
|
||||
-- C_MUX_PIPELINE_STAGES : 0
|
||||
-- C_USE_ECC : 0
|
||||
-- C_USE_SOFTECC : 0
|
||||
-- C_HAS_INJECTERR : 0
|
||||
-- C_SIM_COLLISION_CHECK : ALL
|
||||
-- C_COMMON_CLK : 0
|
||||
-- C_DISABLE_WARN_BHV_COLL : 0
|
||||
-- C_DISABLE_WARN_BHV_RANGE : 0
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY UNISIM;
|
||||
USE UNISIM.VCOMPONENTS.ALL;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
ENTITY result_bram_prod IS
|
||||
PORT (
|
||||
--Port A
|
||||
CLKA : IN STD_LOGIC;
|
||||
RSTA : IN STD_LOGIC; --opt port
|
||||
ENA : IN STD_LOGIC; --optional port
|
||||
REGCEA : IN STD_LOGIC; --optional port
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
|
||||
--Port B
|
||||
CLKB : IN STD_LOGIC;
|
||||
RSTB : IN STD_LOGIC; --opt port
|
||||
ENB : IN STD_LOGIC; --optional port
|
||||
REGCEB : IN STD_LOGIC; --optional port
|
||||
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
DINB : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
|
||||
--ECC
|
||||
INJECTSBITERR : IN STD_LOGIC; --optional port
|
||||
INJECTDBITERR : IN STD_LOGIC; --optional port
|
||||
SBITERR : OUT STD_LOGIC; --optional port
|
||||
DBITERR : OUT STD_LOGIC; --optional port
|
||||
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
|
||||
-- AXI BMG Input and Output Port Declarations
|
||||
|
||||
-- AXI Global Signals
|
||||
S_ACLK : IN STD_LOGIC;
|
||||
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_WLAST : IN STD_LOGIC;
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
S_AXI_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
|
||||
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Slave Read (Write side)
|
||||
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RLAST : OUT STD_LOGIC;
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Sideband Signals
|
||||
S_AXI_INJECTSBITERR : IN STD_LOGIC;
|
||||
S_AXI_INJECTDBITERR : IN STD_LOGIC;
|
||||
S_AXI_SBITERR : OUT STD_LOGIC;
|
||||
S_AXI_DBITERR : OUT STD_LOGIC;
|
||||
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_ARESETN : IN STD_LOGIC
|
||||
|
||||
|
||||
);
|
||||
|
||||
END result_bram_prod;
|
||||
|
||||
|
||||
ARCHITECTURE xilinx OF result_bram_prod IS
|
||||
|
||||
COMPONENT result_bram_exdes IS
|
||||
PORT (
|
||||
--Port A
|
||||
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
|
||||
DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
|
||||
|
||||
CLKA : IN STD_LOGIC;
|
||||
|
||||
|
||||
--Port B
|
||||
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
CLKB : IN STD_LOGIC
|
||||
|
||||
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
bmg0 : result_bram_exdes
|
||||
PORT MAP (
|
||||
--Port A
|
||||
|
||||
WEA => WEA,
|
||||
ADDRA => ADDRA,
|
||||
|
||||
DINA => DINA,
|
||||
|
||||
CLKA => CLKA,
|
||||
|
||||
--Port B
|
||||
ADDRB => ADDRB,
|
||||
DOUTB => DOUTB,
|
||||
CLKB => CLKB
|
||||
|
||||
|
||||
|
||||
);
|
||||
END xilinx;
|
||||
+117
@@ -0,0 +1,117 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Address Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: addr_gen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Address Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
|
||||
ENTITY ADDR_GEN IS
|
||||
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
|
||||
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
|
||||
RST_INC : INTEGER := 0);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
LOAD :IN STD_LOGIC;
|
||||
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
|
||||
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
|
||||
);
|
||||
END ADDR_GEN;
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
|
||||
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
|
||||
BEGIN
|
||||
ADDR_OUT <= ADDR_TEMP;
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST='1') THEN
|
||||
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
|
||||
ELSE
|
||||
IF(EN='1') THEN
|
||||
IF(LOAD='1') THEN
|
||||
ADDR_TEMP <=LOAD_VALUE;
|
||||
ELSE
|
||||
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
|
||||
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
|
||||
ELSE
|
||||
ADDR_TEMP <= ADDR_TEMP + '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END ARCHITECTURE;
|
||||
+434
@@ -0,0 +1,434 @@
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: bmg_stim_gen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Stimulus Generation For SDP Configuration
|
||||
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
|
||||
-- simulation ends
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
USE IEEE.STD_LOGIC_MISC.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
|
||||
ENTITY REGISTER_LOGIC IS
|
||||
PORT(
|
||||
Q : OUT STD_LOGIC;
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
D : IN STD_LOGIC
|
||||
);
|
||||
END REGISTER_LOGIC;
|
||||
|
||||
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
|
||||
SIGNAL Q_O : STD_LOGIC :='0';
|
||||
BEGIN
|
||||
Q <= Q_O;
|
||||
FF_BEH: PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST ='1') THEN
|
||||
Q_O <= '0';
|
||||
ELSE
|
||||
Q_O <= D;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END REGISTER_ARCH;
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
USE IEEE.STD_LOGIC_MISC.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
|
||||
ENTITY BMG_STIM_GEN IS
|
||||
PORT (
|
||||
CLKA : IN STD_LOGIC;
|
||||
CLKB : IN STD_LOGIC;
|
||||
TB_RST : IN STD_LOGIC;
|
||||
ADDRA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
DINA : OUT STD_LOGIC_VECTOR(191 DOWNTO 0) := (OTHERS => '0');
|
||||
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
|
||||
ADDRB: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
CHECK_DATA: OUT STD_LOGIC:='0'
|
||||
);
|
||||
END BMG_STIM_GEN;
|
||||
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
|
||||
|
||||
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINA_INT : STD_LOGIC_VECTOR(191 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DO_WRITE : STD_LOGIC := '0';
|
||||
SIGNAL DO_READ : STD_LOGIC := '0';
|
||||
SIGNAL DO_READ_R : STD_LOGIC := '0';
|
||||
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
|
||||
SIGNAL PORTA_WR : STD_LOGIC:='0';
|
||||
SIGNAL COUNT : INTEGER :=0;
|
||||
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
|
||||
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
|
||||
SIGNAL PORTB_RD : STD_LOGIC:='0';
|
||||
SIGNAL COUNT_RD : INTEGER :=0;
|
||||
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
|
||||
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
|
||||
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
|
||||
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
|
||||
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
|
||||
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
|
||||
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
|
||||
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
|
||||
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
|
||||
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
|
||||
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
|
||||
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
|
||||
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
|
||||
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
|
||||
|
||||
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
|
||||
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((8 <= 8),WR_RD_DEEP_COUNT,
|
||||
((192/192)*WR_RD_DEEP_COUNT));
|
||||
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((8 <= 8),WR_RD_DEEP_COUNT,
|
||||
((192/192)*WR_RD_DEEP_COUNT));
|
||||
|
||||
BEGIN
|
||||
|
||||
ADDRA <= WRITE_ADDR(7 DOWNTO 0) ;
|
||||
DINA <= DINA_INT ;
|
||||
ADDRB <= READ_ADDR(7 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
|
||||
CHECK_DATA <= DO_READ;
|
||||
|
||||
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
|
||||
GENERIC MAP(
|
||||
C_MAX_DEPTH => 256 ,
|
||||
RST_INC => 1 )
|
||||
PORT MAP(
|
||||
CLK => CLKB,
|
||||
RST => TB_RST,
|
||||
EN => DO_READ,
|
||||
LOAD => '0',
|
||||
LOAD_VALUE => ZERO,
|
||||
ADDR_OUT => READ_ADDR
|
||||
);
|
||||
|
||||
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
|
||||
GENERIC MAP(
|
||||
C_MAX_DEPTH => 256,
|
||||
RST_INC => 1 )
|
||||
PORT MAP(
|
||||
CLK => CLKA,
|
||||
RST => TB_RST,
|
||||
EN => DO_WRITE,
|
||||
LOAD => '0',
|
||||
LOAD_VALUE => ZERO,
|
||||
ADDR_OUT => WRITE_ADDR
|
||||
);
|
||||
|
||||
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
|
||||
GENERIC MAP (
|
||||
DATA_GEN_WIDTH => 192,
|
||||
DOUT_WIDTH => 192 ,
|
||||
DATA_PART_CNT => 1,
|
||||
SEED => 2)
|
||||
PORT MAP (
|
||||
CLK => CLKA,
|
||||
RST => TB_RST,
|
||||
EN => DO_WRITE,
|
||||
DATA_OUT => DINA_INT
|
||||
);
|
||||
|
||||
|
||||
PORTA_WR_PROCESS: PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
PORTA_WR<='1';
|
||||
ELSE
|
||||
PORTA_WR<=PORTB_RD_COMPLETE;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PORTB_RD_PROCESS: PROCESS(CLKB)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKB)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
PORTB_RD<='0';
|
||||
ELSE
|
||||
PORTB_RD<=PORTA_WR_L2;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKB)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
LATCH_PORTB_RD_COMPLETE<='0';
|
||||
ELSIF(PORTB_RD_COMPLETE='1') THEN
|
||||
LATCH_PORTB_RD_COMPLETE <='1';
|
||||
ELSIF(PORTA_WR_HAPPENED='1') THEN
|
||||
LATCH_PORTB_RD_COMPLETE<='0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
PORTB_RD_L1 <='0';
|
||||
PORTB_RD_L2 <='0';
|
||||
ELSE
|
||||
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
|
||||
PORTB_RD_L2 <= PORTB_RD_L1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLKB)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKB)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
PORTA_WR_R1 <='0';
|
||||
PORTA_WR_R2 <='0';
|
||||
ELSE
|
||||
PORTA_WR_R1 <= PORTA_WR;
|
||||
PORTA_WR_R2 <= PORTA_WR_R1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PORTA_WR_HAPPENED <= PORTA_WR_R2;
|
||||
|
||||
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
LATCH_PORTA_WR_COMPLETE<='0';
|
||||
ELSIF(PORTA_WR_COMPLETE='1') THEN
|
||||
LATCH_PORTA_WR_COMPLETE <='1';
|
||||
--ELSIF(PORTB_RD_HAPPENED='1') THEN
|
||||
ELSE
|
||||
LATCH_PORTA_WR_COMPLETE<='0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLKB)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKB)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
PORTA_WR_L1 <='0';
|
||||
PORTA_WR_L2 <='0';
|
||||
ELSE
|
||||
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
|
||||
PORTA_WR_L2 <= PORTA_WR_L1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
PORTB_RD_R1 <='0';
|
||||
PORTB_RD_R2 <='0';
|
||||
ELSE
|
||||
PORTB_RD_R1 <= PORTB_RD;
|
||||
PORTB_RD_R2 <= PORTB_RD_R1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PORTB_RD_HAPPENED <= PORTB_RD_R2;
|
||||
|
||||
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
|
||||
|
||||
start_rd_counter: process(clkb)
|
||||
begin
|
||||
if(rising_edge(clkb)) then
|
||||
if(tb_rst='1') then
|
||||
incr_rd_cnt <= '0';
|
||||
elsif(portb_rd ='1') then
|
||||
incr_rd_cnt <='1';
|
||||
elsif(portb_rd_complete='1') then
|
||||
incr_rd_cnt <='0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
RD_COUNTER: process(clkb)
|
||||
begin
|
||||
if(rising_edge(clkb)) then
|
||||
if(tb_rst='1') then
|
||||
count_rd <= 0;
|
||||
elsif(incr_rd_cnt='1') then
|
||||
count_rd<=count_rd+1;
|
||||
end if;
|
||||
--if(count_rd=(wr_rd_deep_count)) then
|
||||
if(count_rd=(RD_DEEP_COUNT)) then
|
||||
count_rd<=0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
|
||||
|
||||
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
|
||||
|
||||
start_counter: process(clka)
|
||||
begin
|
||||
if(rising_edge(clka)) then
|
||||
if(tb_rst='1') then
|
||||
incr_wr_cnt <= '0';
|
||||
elsif(porta_wr ='1') then
|
||||
incr_wr_cnt <='1';
|
||||
elsif(porta_wr_complete='1') then
|
||||
incr_wr_cnt <='0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
COUNTER: process(clka)
|
||||
begin
|
||||
if(rising_edge(clka)) then
|
||||
if(tb_rst='1') then
|
||||
count <= 0;
|
||||
elsif(incr_wr_cnt='1') then
|
||||
count<=count+1;
|
||||
end if;
|
||||
if(count=(WR_DEEP_COUNT)) then
|
||||
count<=0;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
|
||||
|
||||
|
||||
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
|
||||
BEGIN
|
||||
DFF_RIGHT: IF I=0 GENERATE
|
||||
BEGIN
|
||||
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
|
||||
PORT MAP(
|
||||
Q => DO_READ_REG(0),
|
||||
CLK => CLKB,
|
||||
RST => TB_RST,
|
||||
D => DO_READ
|
||||
);
|
||||
END GENERATE DFF_RIGHT;
|
||||
|
||||
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
|
||||
BEGIN
|
||||
SHIFT_INST: ENTITY work.REGISTER_LOGIC
|
||||
PORT MAP(
|
||||
Q => DO_READ_REG(I),
|
||||
CLK =>CLKB,
|
||||
RST =>TB_RST,
|
||||
D =>DO_READ_REG(I-1)
|
||||
);
|
||||
END GENERATE DFF_OTHERS;
|
||||
END GENERATE BEGIN_SHIFT_REG;
|
||||
|
||||
REGCE_PROCESS: PROCESS(CLKB)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKB)) THEN
|
||||
IF(TB_RST='1') THEN
|
||||
DO_READ_R <= '0';
|
||||
ELSE
|
||||
DO_READ_R <= DO_READ;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
|
||||
WEA(0) <= DO_WRITE ;
|
||||
|
||||
|
||||
END ARCHITECTURE;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
+200
@@ -0,0 +1,200 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Testbench Package
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: bmg_tb_pkg.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- BMG Testbench Package files
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
PACKAGE BMG_TB_PKG IS
|
||||
|
||||
FUNCTION DIVROUNDUP (
|
||||
DATA_VALUE : INTEGER;
|
||||
DIVISOR : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC_VECTOR;
|
||||
FALSE_CASE : STD_LOGIC_VECTOR)
|
||||
RETURN STD_LOGIC_VECTOR;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STRING;
|
||||
FALSE_CASE :STRING)
|
||||
RETURN STRING;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC;
|
||||
FALSE_CASE :STD_LOGIC)
|
||||
RETURN STD_LOGIC;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : INTEGER;
|
||||
FALSE_CASE : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION LOG2ROUNDUP (
|
||||
DATA_VALUE : INTEGER)
|
||||
RETURN INTEGER;
|
||||
|
||||
END BMG_TB_PKG;
|
||||
|
||||
PACKAGE BODY BMG_TB_PKG IS
|
||||
|
||||
FUNCTION DIVROUNDUP (
|
||||
DATA_VALUE : INTEGER;
|
||||
DIVISOR : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE DIV : INTEGER;
|
||||
BEGIN
|
||||
DIV := DATA_VALUE/DIVISOR;
|
||||
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
|
||||
DIV := DIV+1;
|
||||
END IF;
|
||||
RETURN DIV;
|
||||
END DIVROUNDUP;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC_VECTOR;
|
||||
FALSE_CASE : STD_LOGIC_VECTOR)
|
||||
RETURN STD_LOGIC_VECTOR IS
|
||||
BEGIN
|
||||
IF NOT CONDITION THEN
|
||||
RETURN FALSE_CASE;
|
||||
ELSE
|
||||
RETURN TRUE_CASE;
|
||||
END IF;
|
||||
END IF_THEN_ELSE;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC;
|
||||
FALSE_CASE : STD_LOGIC)
|
||||
RETURN STD_LOGIC IS
|
||||
BEGIN
|
||||
IF NOT CONDITION THEN
|
||||
RETURN FALSE_CASE;
|
||||
ELSE
|
||||
RETURN TRUE_CASE;
|
||||
END IF;
|
||||
END IF_THEN_ELSE;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : INTEGER;
|
||||
FALSE_CASE : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE RETVAL : INTEGER := 0;
|
||||
BEGIN
|
||||
IF CONDITION=FALSE THEN
|
||||
RETVAL:=FALSE_CASE;
|
||||
ELSE
|
||||
RETVAL:=TRUE_CASE;
|
||||
END IF;
|
||||
RETURN RETVAL;
|
||||
END IF_THEN_ELSE;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STRING;
|
||||
FALSE_CASE : STRING)
|
||||
RETURN STRING IS
|
||||
BEGIN
|
||||
IF NOT CONDITION THEN
|
||||
RETURN FALSE_CASE;
|
||||
ELSE
|
||||
RETURN TRUE_CASE;
|
||||
END IF;
|
||||
END IF_THEN_ELSE;
|
||||
-------------------------------
|
||||
FUNCTION LOG2ROUNDUP (
|
||||
DATA_VALUE : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE WIDTH : INTEGER := 0;
|
||||
VARIABLE CNT : INTEGER := 1;
|
||||
BEGIN
|
||||
IF (DATA_VALUE <= 1) THEN
|
||||
WIDTH := 1;
|
||||
ELSE
|
||||
WHILE (CNT < DATA_VALUE) LOOP
|
||||
WIDTH := WIDTH + 1;
|
||||
CNT := CNT *2;
|
||||
END LOOP;
|
||||
END IF;
|
||||
RETURN WIDTH;
|
||||
END LOG2ROUNDUP;
|
||||
|
||||
END BMG_TB_PKG;
|
||||
+161
@@ -0,0 +1,161 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Checker
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: checker.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Checker
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
ENTITY CHECKER IS
|
||||
GENERIC ( WRITE_WIDTH : INTEGER :=32;
|
||||
READ_WIDTH : INTEGER :=32
|
||||
);
|
||||
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
|
||||
STATUS : OUT STD_LOGIC:= '0'
|
||||
);
|
||||
END CHECKER;
|
||||
|
||||
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
|
||||
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
|
||||
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
|
||||
SIGNAL EN_R : STD_LOGIC := '0';
|
||||
SIGNAL EN_2R : STD_LOGIC := '0';
|
||||
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
|
||||
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
|
||||
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
|
||||
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
|
||||
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
|
||||
SIGNAL ERR_HOLD : STD_LOGIC :='0';
|
||||
SIGNAL ERR_DET : STD_LOGIC :='0';
|
||||
BEGIN
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST= '1') THEN
|
||||
EN_R <= '0';
|
||||
EN_2R <= '0';
|
||||
DATA_IN_R <= (OTHERS=>'0');
|
||||
ELSE
|
||||
EN_R <= EN;
|
||||
EN_2R <= EN_R;
|
||||
DATA_IN_R <= DATA_IN;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
|
||||
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
|
||||
DOUT_WIDTH => READ_WIDTH,
|
||||
DATA_PART_CNT => DATA_PART_CNT,
|
||||
SEED => 2
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RST => RST,
|
||||
EN => EN_2R,
|
||||
DATA_OUT => EXPECTED_DATA
|
||||
);
|
||||
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(EN_2R='1') THEN
|
||||
IF(EXPECTED_DATA = DATA_IN_R) THEN
|
||||
ERR_DET<='0';
|
||||
ELSE
|
||||
ERR_DET<= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLK,RST)
|
||||
BEGIN
|
||||
IF(RST='1') THEN
|
||||
ERR_HOLD <= '0';
|
||||
ELSIF(RISING_EDGE(CLK)) THEN
|
||||
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
STATUS <= ERR_HOLD;
|
||||
|
||||
END ARCHITECTURE;
|
||||
|
||||
|
||||
|
||||
+140
@@ -0,0 +1,140 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Data Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: data_gen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Data Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
ENTITY DATA_GEN IS
|
||||
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
|
||||
DOUT_WIDTH : INTEGER := 32;
|
||||
DATA_PART_CNT : INTEGER := 1;
|
||||
SEED : INTEGER := 2
|
||||
);
|
||||
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
|
||||
);
|
||||
END DATA_GEN;
|
||||
|
||||
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
|
||||
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
|
||||
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
|
||||
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
|
||||
SIGNAL LOCAL_CNT : INTEGER :=1;
|
||||
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
|
||||
BEGIN
|
||||
|
||||
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
|
||||
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
|
||||
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
|
||||
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE (CLK)) THEN
|
||||
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
|
||||
LOCAL_CNT <=1;
|
||||
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
|
||||
IF(LOCAL_CNT = 1) THEN
|
||||
LOCAL_CNT <= LOCAL_CNT+1;
|
||||
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
|
||||
LOCAL_CNT <= LOCAL_CNT+1;
|
||||
ELSE
|
||||
LOCAL_CNT <= 1;
|
||||
END IF;
|
||||
ELSE
|
||||
LOCAL_CNT <= 1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
|
||||
RAND_GEN_INST:ENTITY work.RANDOM
|
||||
GENERIC MAP(
|
||||
WIDTH => 8,
|
||||
SEED => (SEED+N)
|
||||
)
|
||||
PORT MAP(
|
||||
CLK => CLK,
|
||||
RST => RST,
|
||||
EN => DATA_GEN_I,
|
||||
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
|
||||
);
|
||||
END GENERATE RAND_GEN;
|
||||
|
||||
END ARCHITECTURE;
|
||||
|
||||
+112
@@ -0,0 +1,112 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Random Number Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: random.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Random Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
|
||||
ENTITY RANDOM IS
|
||||
GENERIC ( WIDTH : INTEGER := 32;
|
||||
SEED : INTEGER :=2
|
||||
);
|
||||
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
|
||||
);
|
||||
END RANDOM;
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF RANDOM IS
|
||||
BEGIN
|
||||
PROCESS(CLK)
|
||||
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
|
||||
VARIABLE TEMP : STD_LOGIC := '0';
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST='1') THEN
|
||||
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
|
||||
ELSE
|
||||
IF(EN = '1') THEN
|
||||
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
|
||||
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
|
||||
RAND_TEMP(0) := TEMP;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
RANDOM_NUM <= RAND_TEMP;
|
||||
END PROCESS;
|
||||
END ARCHITECTURE;
|
||||
+322
@@ -0,0 +1,322 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: result_bram_synth.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Synthesizable Testbench
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE IEEE.STD_LOGIC_MISC.ALL;
|
||||
|
||||
LIBRARY STD;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
--LIBRARY unisim;
|
||||
--USE unisim.vcomponents.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
ENTITY result_bram_synth IS
|
||||
PORT(
|
||||
CLK_IN : IN STD_LOGIC;
|
||||
CLKB_IN : IN STD_LOGIC;
|
||||
RESET_IN : IN STD_LOGIC;
|
||||
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
ARCHITECTURE result_bram_synth_ARCH OF result_bram_synth IS
|
||||
|
||||
|
||||
COMPONENT result_bram_exdes
|
||||
PORT (
|
||||
--Inputs - Port A
|
||||
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
CLKA : IN STD_LOGIC;
|
||||
|
||||
--Inputs - Port B
|
||||
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
CLKB : IN STD_LOGIC
|
||||
|
||||
);
|
||||
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
SIGNAL CLKA: STD_LOGIC := '0';
|
||||
SIGNAL RSTA: STD_LOGIC := '0';
|
||||
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINA: STD_LOGIC_VECTOR(191 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DINA_R: STD_LOGIC_VECTOR(191 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL CLKB: STD_LOGIC := '0';
|
||||
SIGNAL RSTB: STD_LOGIC := '0';
|
||||
SIGNAL ADDRB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL DOUTB: STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
SIGNAL CHECKER_EN : STD_LOGIC:='0';
|
||||
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
|
||||
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
|
||||
SIGNAL clk_in_i: STD_LOGIC;
|
||||
|
||||
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
|
||||
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
|
||||
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
|
||||
|
||||
SIGNAL clkb_in_i: STD_LOGIC;
|
||||
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
|
||||
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
|
||||
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
|
||||
SIGNAL ITER_R0 : STD_LOGIC := '0';
|
||||
SIGNAL ITER_R1 : STD_LOGIC := '0';
|
||||
SIGNAL ITER_R2 : STD_LOGIC := '0';
|
||||
|
||||
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
|
||||
BEGIN
|
||||
|
||||
-- clk_buf: bufg
|
||||
-- PORT map(
|
||||
-- i => CLK_IN,
|
||||
-- o => clk_in_i
|
||||
-- );
|
||||
clk_in_i <= CLK_IN;
|
||||
CLKA <= clk_in_i;
|
||||
|
||||
-- clkb_buf: bufg
|
||||
-- PORT map(
|
||||
-- i => CLKB_IN,
|
||||
-- o => clkb_in_i
|
||||
-- );
|
||||
clkb_in_i <= CLKB_IN;
|
||||
CLKB <= clkb_in_i;
|
||||
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
|
||||
|
||||
|
||||
PROCESS(clk_in_i)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(clk_in_i)) THEN
|
||||
RESET_SYNC_R1 <= RESET_IN;
|
||||
RESET_SYNC_R2 <= RESET_SYNC_R1;
|
||||
RESET_SYNC_R3 <= RESET_SYNC_R2;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
|
||||
|
||||
PROCESS(clkb_in_i)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(clkb_in_i)) THEN
|
||||
RESETB_SYNC_R1 <= RESET_IN;
|
||||
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
|
||||
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
ISSUE_FLAG_STATUS<= (OTHERS => '0');
|
||||
ELSE
|
||||
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
|
||||
|
||||
|
||||
|
||||
|
||||
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
|
||||
GENERIC MAP (
|
||||
WRITE_WIDTH => 192,
|
||||
READ_WIDTH => 192 )
|
||||
PORT MAP (
|
||||
CLK => clkb_in_i,
|
||||
RST => RSTB,
|
||||
EN => CHECKER_EN_R,
|
||||
DATA_IN => DOUTB,
|
||||
STATUS => ISSUE_FLAG(0)
|
||||
);
|
||||
|
||||
PROCESS(clkb_in_i)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(clkb_in_i)) THEN
|
||||
IF(RSTB='1') THEN
|
||||
CHECKER_EN_R <= '0';
|
||||
ELSE
|
||||
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
|
||||
PORT MAP(
|
||||
CLKA => clk_in_i,
|
||||
CLKB => clkb_in_i,
|
||||
TB_RST => RSTA,
|
||||
ADDRA => ADDRA,
|
||||
DINA => DINA,
|
||||
WEA => WEA,
|
||||
ADDRB => ADDRB,
|
||||
CHECK_DATA => CHECKER_EN
|
||||
);
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
STATUS(8) <= '0';
|
||||
iter_r2 <= '0';
|
||||
iter_r1 <= '0';
|
||||
iter_r0 <= '0';
|
||||
ELSE
|
||||
STATUS(8) <= iter_r2;
|
||||
iter_r2 <= iter_r1;
|
||||
iter_r1 <= iter_r0;
|
||||
iter_r0 <= STIMULUS_FLOW(8);
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
STIMULUS_FLOW <= (OTHERS => '0');
|
||||
ELSIF(WEA(0)='1') THEN
|
||||
STIMULUS_FLOW <= STIMULUS_FLOW+1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
|
||||
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
|
||||
|
||||
|
||||
ELSE
|
||||
WEA_R <= WEA AFTER 50 ns;
|
||||
DINA_R <= DINA AFTER 50 ns;
|
||||
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
|
||||
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
|
||||
ELSE
|
||||
ADDRA_R <= ADDRA AFTER 50 ns;
|
||||
ADDRB_R <= ADDRB AFTER 50 ns;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
BMG_PORT: result_bram_exdes PORT MAP (
|
||||
--Port A
|
||||
WEA => WEA_R,
|
||||
ADDRA => ADDRA_R,
|
||||
DINA => DINA_R,
|
||||
CLKA => CLKA,
|
||||
--Port B
|
||||
ADDRB => ADDRB_R,
|
||||
DOUTB => DOUTB,
|
||||
CLKB => CLKB
|
||||
|
||||
);
|
||||
END ARCHITECTURE;
|
||||
+142
@@ -0,0 +1,142 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Filename: result_bram_tb.vhd
|
||||
-- Description:
|
||||
-- Testbench Top
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
|
||||
ENTITY result_bram_tb IS
|
||||
END ENTITY;
|
||||
|
||||
|
||||
ARCHITECTURE result_bram_tb_ARCH OF result_bram_tb IS
|
||||
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
SIGNAL CLK : STD_LOGIC := '1';
|
||||
SIGNAL CLKB : STD_LOGIC := '1';
|
||||
SIGNAL RESET : STD_LOGIC;
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
CLK_GEN: PROCESS BEGIN
|
||||
CLK <= NOT CLK;
|
||||
WAIT FOR 100 NS;
|
||||
CLK <= NOT CLK;
|
||||
WAIT FOR 100 NS;
|
||||
END PROCESS;
|
||||
CLKB_GEN: PROCESS BEGIN
|
||||
CLKB <= NOT CLKB;
|
||||
WAIT FOR 100 NS;
|
||||
CLKB <= NOT CLKB;
|
||||
WAIT FOR 100 NS;
|
||||
END PROCESS;
|
||||
|
||||
RST_GEN: PROCESS BEGIN
|
||||
RESET <= '1';
|
||||
WAIT FOR 1000 NS;
|
||||
RESET <= '0';
|
||||
WAIT;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
--STOP_SIM: PROCESS BEGIN
|
||||
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
|
||||
-- ASSERT FALSE
|
||||
-- REPORT "END SIMULATION TIME REACHED"
|
||||
-- SEVERITY FAILURE;
|
||||
--END PROCESS;
|
||||
--
|
||||
PROCESS BEGIN
|
||||
WAIT UNTIL STATUS(8)='1';
|
||||
IF( STATUS(7 downto 0)/="0") THEN
|
||||
ASSERT false
|
||||
REPORT "Test Completed Successfully"
|
||||
SEVERITY NOTE;
|
||||
REPORT "Simulation Failed"
|
||||
SEVERITY FAILURE;
|
||||
ELSE
|
||||
ASSERT false
|
||||
REPORT "TEST PASS"
|
||||
SEVERITY NOTE;
|
||||
REPORT "Test Completed Successfully"
|
||||
SEVERITY FAILURE;
|
||||
END IF;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
result_bram_synth_inst:ENTITY work.result_bram_synth
|
||||
PORT MAP(
|
||||
CLK_IN => CLK,
|
||||
CLKB_IN => CLK,
|
||||
RESET_IN => RESET,
|
||||
STATUS => STATUS
|
||||
);
|
||||
|
||||
END ARCHITECTURE;
|
||||
+53
@@ -0,0 +1,53 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="wide_mult.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="wide_mult.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="wide_mult.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="wide_mult.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1654646662" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1654646662">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4659816854749047906" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5812453015497774159" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1654895235" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7916142474556992292" xil_pn:start_ts="1654895235">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
+102
@@ -0,0 +1,102 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used solely --
|
||||
-- for design, simulation, implementation and creation of design files --
|
||||
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
||||
-- devices or technologies is expressly prohibited and immediately --
|
||||
-- terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
||||
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
||||
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
||||
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
||||
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
||||
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
||||
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
||||
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
||||
-- PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support appliances, --
|
||||
-- devices, or systems. Use in such applications are expressly --
|
||||
-- prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2022 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file wide_mult.vhd when simulating
|
||||
-- the core, wide_mult. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
LIBRARY XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY wide_mult IS
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
a : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
b : IN STD_LOGIC_VECTOR(26 DOWNTO 0);
|
||||
ce : IN STD_LOGIC;
|
||||
p : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
|
||||
);
|
||||
END wide_mult;
|
||||
|
||||
ARCHITECTURE wide_mult_a OF wide_mult IS
|
||||
-- synthesis translate_off
|
||||
COMPONENT wrapped_wide_mult
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
a : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
b : IN STD_LOGIC_VECTOR(26 DOWNTO 0);
|
||||
ce : IN STD_LOGIC;
|
||||
p : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Configuration specification
|
||||
FOR ALL : wrapped_wide_mult USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
|
||||
GENERIC MAP (
|
||||
c_a_type => 1,
|
||||
c_a_width => 13,
|
||||
c_b_type => 1,
|
||||
c_b_value => "10000001",
|
||||
c_b_width => 27,
|
||||
c_ccm_imp => 0,
|
||||
c_ce_overrides_sclr => 0,
|
||||
c_has_ce => 1,
|
||||
c_has_sclr => 0,
|
||||
c_has_zero_detect => 0,
|
||||
c_latency => 5,
|
||||
c_model_type => 0,
|
||||
c_mult_type => 1,
|
||||
c_optimize_goal => 1,
|
||||
c_out_high => 39,
|
||||
c_out_low => 0,
|
||||
c_round_output => 0,
|
||||
c_round_pt => 0,
|
||||
c_verbosity => 0,
|
||||
c_xdevicefamily => "spartan6"
|
||||
);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_wide_mult
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
a => a,
|
||||
b => b,
|
||||
ce => ce,
|
||||
p => p
|
||||
);
|
||||
-- synthesis translate_on
|
||||
|
||||
END wide_mult_a;
|
||||
@@ -0,0 +1,6 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
package BuildConfig is
|
||||
constant EXTERNAL_MASTER_LO_SLAVE : boolean := false;
|
||||
end package BuildConfig;
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
package BuildConfig is
|
||||
constant EXTERNAL_MASTER_LO_SLAVE : boolean := true;
|
||||
end package BuildConfig;
|
||||
@@ -0,0 +1,358 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 20:38:37 09/18/2020
|
||||
-- Design Name:
|
||||
-- Module Name: DFT - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity DFT is
|
||||
Generic (BINS : integer);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RESET : in STD_LOGIC;
|
||||
PORT1 : in STD_LOGIC_VECTOR (17 downto 0);
|
||||
PORT2 : in STD_LOGIC_VECTOR (17 downto 0);
|
||||
NEW_SAMPLE : in STD_LOGIC;
|
||||
NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
|
||||
BIN1_PHASEINC : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
DIFFBIN_PHASEINC : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
RESULT_READY : out STD_LOGIC;
|
||||
OUTPUT : out STD_LOGIC_VECTOR (191 downto 0);
|
||||
NEXT_OUTPUT : in STD_LOGIC);
|
||||
end DFT;
|
||||
|
||||
architecture Behavioral of DFT is
|
||||
COMPONENT result_bram
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(191 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT SinCos
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT DSP_SLICE
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
ce : IN STD_LOGIC;
|
||||
sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||
p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT window
|
||||
PORT(
|
||||
CLK : IN std_logic;
|
||||
INDEX : IN std_logic_vector(6 downto 0);
|
||||
WINDOW_TYPE : IN std_logic_vector(1 downto 0);
|
||||
VALUE : OUT std_logic_vector(15 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--type result is array(BINS-1 downto 0) of std_logic_vector(47 downto 0);
|
||||
--signal port1_real : result;
|
||||
--signal port1_imag : result;
|
||||
--signal port2_real : result;
|
||||
--signal port2_imag : result;
|
||||
|
||||
--signal port1_real_read : std_logic_vector(47 downto 0);
|
||||
--signal port1_imag_read : std_logic_vector(47 downto 0);
|
||||
--signal port2_real_read : std_logic_vector(47 downto 0);
|
||||
--signal port2_imag_read : std_logic_vector(47 downto 0);
|
||||
|
||||
signal sample_cnt : integer range 0 to 131072;
|
||||
signal samples_to_take : integer range 0 to 131072;
|
||||
signal bin_cnt : integer range 0 to BINS+2;
|
||||
|
||||
signal read_address : integer range 0 to BINS-1;
|
||||
signal write_address : integer range 0 to BINS-1;
|
||||
signal read_address_vector : std_logic_vector(7 downto 0);
|
||||
signal write_address_vector : std_logic_vector(7 downto 0);
|
||||
signal we : std_logic_vector(0 downto 0);
|
||||
signal ram_in : std_logic_vector(191 downto 0);
|
||||
signal ram_out : std_logic_vector(191 downto 0);
|
||||
|
||||
type States is (WaitingForSample, WaitMult, WaitSinCos, Busy, Ready);
|
||||
signal state : States;
|
||||
signal port1_latch : std_logic_vector(17 downto 0);
|
||||
signal port2_latch : std_logic_vector(17 downto 0);
|
||||
|
||||
signal phase : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal sine : std_logic_vector(15 downto 0);
|
||||
signal cosine : std_logic_vector(15 downto 0);
|
||||
|
||||
signal mult1_a : std_logic_vector(17 downto 0);
|
||||
signal mult1_b : std_logic_vector(17 downto 0);
|
||||
signal mult1_c : std_logic_vector(47 downto 0);
|
||||
signal mult1_p : std_logic_vector(47 downto 0);
|
||||
|
||||
signal mult2_a : std_logic_vector(17 downto 0);
|
||||
signal mult2_b : std_logic_vector(17 downto 0);
|
||||
signal mult2_c : std_logic_vector(47 downto 0);
|
||||
signal mult2_p : std_logic_vector(47 downto 0);
|
||||
|
||||
signal mult3_a : std_logic_vector(17 downto 0);
|
||||
signal mult3_b : std_logic_vector(17 downto 0);
|
||||
signal mult3_c : std_logic_vector(47 downto 0);
|
||||
signal mult3_p : std_logic_vector(47 downto 0);
|
||||
|
||||
signal mult4_a : std_logic_vector(17 downto 0);
|
||||
signal mult4_b : std_logic_vector(17 downto 0);
|
||||
signal mult4_c : std_logic_vector(47 downto 0);
|
||||
signal mult4_p : std_logic_vector(47 downto 0);
|
||||
|
||||
signal mult_enable : std_logic;
|
||||
signal mult_accumulate : std_logic_vector(0 downto 0);
|
||||
begin
|
||||
|
||||
LookupTable : SinCos
|
||||
PORT MAP (
|
||||
clk => CLK,
|
||||
phase_in => phase(31 downto 20),
|
||||
cosine => cosine,
|
||||
sine => sine
|
||||
);
|
||||
Mult1 : DSP_SLICE
|
||||
PORT MAP (
|
||||
clk => CLK,
|
||||
ce => mult_enable,
|
||||
sel => mult_accumulate,
|
||||
a => mult1_a,
|
||||
b => mult1_b,
|
||||
c => mult1_c,
|
||||
p => mult1_p
|
||||
);
|
||||
Mult2 : DSP_SLICE
|
||||
PORT MAP (
|
||||
clk => CLK,
|
||||
ce => mult_enable,
|
||||
sel => mult_accumulate,
|
||||
a => mult2_a,
|
||||
b => mult2_b,
|
||||
c => mult2_c,
|
||||
p => mult2_p
|
||||
);
|
||||
Mult3 : DSP_SLICE
|
||||
PORT MAP (
|
||||
clk => CLK,
|
||||
ce => mult_enable,
|
||||
sel => mult_accumulate,
|
||||
a => mult3_a,
|
||||
b => mult3_b,
|
||||
c => mult3_c,
|
||||
p => mult3_p
|
||||
);
|
||||
Mult4 : DSP_SLICE
|
||||
PORT MAP (
|
||||
clk => CLK,
|
||||
ce => mult_enable,
|
||||
sel => mult_accumulate,
|
||||
a => mult4_a,
|
||||
b => mult4_b,
|
||||
c => mult4_c,
|
||||
p => mult4_p
|
||||
);
|
||||
|
||||
result_ram: result_bram
|
||||
PORT MAP (
|
||||
clka => CLK,
|
||||
wea => we,
|
||||
addra => write_address_vector,
|
||||
dina => ram_in,
|
||||
clkb => CLK,
|
||||
addrb => read_address_vector,
|
||||
doutb => ram_out
|
||||
);
|
||||
|
||||
read_address_vector <= std_logic_vector(to_unsigned(read_address, 8));
|
||||
write_address_vector <= std_logic_vector(to_unsigned(write_address, 8));
|
||||
OUTPUT <= ram_out;
|
||||
|
||||
mult1_c <= ram_out(191 downto 144);
|
||||
mult2_c <= ram_out(143 downto 96);
|
||||
mult3_c <= ram_out(95 downto 48);
|
||||
mult4_c <= ram_out(47 downto 0);
|
||||
|
||||
ram_in <= mult1_p & mult2_p & mult3_p & mult4_p;
|
||||
|
||||
process(CLK, RESET)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RESET = '1' then
|
||||
mult_enable <= '0';
|
||||
mult_accumulate <= "0";
|
||||
sample_cnt <= 0;
|
||||
RESULT_READY <= '0';
|
||||
read_address <= 0;
|
||||
write_address <= 0;
|
||||
we <= "0";
|
||||
state <= WaitingForSample;
|
||||
else
|
||||
samples_to_take <= to_integer(unsigned(NSAMPLES & "0000")) - 1;
|
||||
case state is
|
||||
when WaitingForSample =>
|
||||
we <= "0";
|
||||
mult_enable <= '0';
|
||||
mult_accumulate <= "0";
|
||||
read_address <= 0;
|
||||
write_address <= 0;
|
||||
if NEW_SAMPLE = '1' then
|
||||
-- calculate phase for initial bin
|
||||
mult1_a <= std_logic_vector(to_unsigned(sample_cnt, 18));
|
||||
mult1_b <= "00" & BIN1_PHASEINC;
|
||||
mult2_a <= std_logic_vector(to_unsigned(sample_cnt, 18));
|
||||
mult2_b <= "00" & DIFFBIN_PHASEINC;
|
||||
state <= WaitMult;
|
||||
bin_cnt <= 0;
|
||||
mult_enable <= '1';
|
||||
end if;
|
||||
when WaitMult =>
|
||||
RESULT_READY <= '0';
|
||||
we <= "0";
|
||||
mult_enable <= '1';
|
||||
mult_accumulate <= "0";
|
||||
read_address <= 0;
|
||||
write_address <= 0;
|
||||
if bin_cnt < 4 then
|
||||
bin_cnt <= bin_cnt + 1;
|
||||
else
|
||||
bin_cnt <= 0;
|
||||
mult_enable <= '0';
|
||||
state <= WaitSinCos;
|
||||
phase <= mult1_p(15 downto 0) & "0000000000000000";
|
||||
phase_inc <= mult2_p(23 downto 0) & "00000000";
|
||||
port1_latch <= PORT1;
|
||||
port2_latch <= PORT2;
|
||||
end if;
|
||||
when WaitSinCos =>
|
||||
phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
|
||||
RESULT_READY <= '0';
|
||||
we <= "0";
|
||||
mult_enable <= '0';
|
||||
mult_accumulate <= "0";
|
||||
read_address <= 0;
|
||||
write_address <= 0;
|
||||
if bin_cnt < 6 then
|
||||
bin_cnt <= bin_cnt + 1;
|
||||
else
|
||||
bin_cnt <= 0;
|
||||
mult_enable <= '1';
|
||||
read_address <= 1;
|
||||
-- sign extended multiplication
|
||||
mult1_a <= port1_latch;
|
||||
mult1_b <= sine(15) & sine(15) & sine;
|
||||
mult2_a <= port1_latch;
|
||||
mult2_b <= cosine(15) & cosine(15) & cosine;
|
||||
mult3_a <= port2_latch;
|
||||
mult3_b <= sine(15) & sine(15) & sine;
|
||||
mult4_a <= port2_latch;
|
||||
mult4_b <= cosine(15) & cosine(15) & cosine;
|
||||
state <= BUSY;
|
||||
if sample_cnt = 0 then
|
||||
mult_accumulate <= "0";
|
||||
else
|
||||
mult_accumulate <= "1";
|
||||
end if;
|
||||
end if;
|
||||
when BUSY =>
|
||||
mult_enable <= '1';
|
||||
if sample_cnt = 0 then
|
||||
mult_accumulate <= "0";
|
||||
else
|
||||
mult_accumulate <= "1";
|
||||
end if;
|
||||
RESULT_READY <= '0';
|
||||
phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
|
||||
-- sign extended multiplication
|
||||
mult1_a <= port1_latch;
|
||||
mult1_b <= sine(15) & sine(15) & sine;
|
||||
mult2_a <= port1_latch;
|
||||
mult2_b <= cosine(15) & cosine(15) & cosine;
|
||||
mult3_a <= port2_latch;
|
||||
mult3_b <= sine(15) & sine(15) & sine;
|
||||
mult4_a <= port2_latch;
|
||||
mult4_b <= cosine(15) & cosine(15) & cosine;
|
||||
if bin_cnt >= 3 then
|
||||
-- multiplier result is available, advance write address
|
||||
we <= "1";
|
||||
write_address <= bin_cnt - 3;
|
||||
else
|
||||
we <= "0";
|
||||
write_address <= 0;
|
||||
end if;
|
||||
if bin_cnt >= BINS+2 then
|
||||
read_address <= 0;
|
||||
if sample_cnt < samples_to_take then
|
||||
sample_cnt <= sample_cnt + 1;
|
||||
state <= WaitingForSample;
|
||||
else
|
||||
state <= Ready;
|
||||
end if;
|
||||
else
|
||||
bin_cnt <= bin_cnt + 1;
|
||||
if bin_cnt < BINS - 2 then
|
||||
read_address <= bin_cnt + 2;
|
||||
end if;
|
||||
end if;
|
||||
when Ready =>
|
||||
we <= "0";
|
||||
RESULT_READY <= '1';
|
||||
write_address <= 0;
|
||||
if NEXT_OUTPUT = '1' then
|
||||
-- fetch next entry from RAM
|
||||
if read_address < BINS - 1 then
|
||||
read_address <= read_address + 1;
|
||||
else
|
||||
RESULT_READY <= '0';
|
||||
sample_cnt <= 0;
|
||||
mult_enable <= '0';
|
||||
state <= WaitingForSample;
|
||||
read_address <= 0;
|
||||
end if;
|
||||
end if;
|
||||
when others =>
|
||||
state <= WaitingForSample;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,128 @@
|
||||
1111111111111000
|
||||
1111111111110110
|
||||
1111111111110001
|
||||
1111111111101001
|
||||
1111111111011111
|
||||
1111111111010001
|
||||
1111111110111111
|
||||
1111111110101001
|
||||
1111111110001110
|
||||
1111111101101110
|
||||
1111111101001000
|
||||
1111111100011100
|
||||
1111111011101001
|
||||
1111111010101111
|
||||
1111111001101111
|
||||
1111111000101000
|
||||
1111110111011011
|
||||
1111110110001000
|
||||
1111110100110001
|
||||
1111110011011000
|
||||
1111110001111101
|
||||
1111110000100011
|
||||
1111101111001101
|
||||
1111101101111101
|
||||
1111101100110111
|
||||
1111101011111110
|
||||
1111101011010111
|
||||
1111101011000100
|
||||
1111101011001011
|
||||
1111101011110001
|
||||
1111101100111001
|
||||
1111101110101000
|
||||
1111110001000011
|
||||
1111110100001110
|
||||
1111111000001100
|
||||
1111111101000001
|
||||
0000000010101110
|
||||
0000001001011001
|
||||
0000010001000000
|
||||
0000011001100100
|
||||
0000100011000101
|
||||
0000101101100010
|
||||
0000111000111000
|
||||
0001000101000100
|
||||
0001010010000000
|
||||
0001011111100111
|
||||
0001101101110011
|
||||
0001111100011100
|
||||
0010001011011001
|
||||
0010011010100001
|
||||
0010101001101011
|
||||
0010111000101100
|
||||
0011000111011001
|
||||
0011010101101000
|
||||
0011100011001110
|
||||
0011110000000000
|
||||
0011111011110100
|
||||
0100000110100001
|
||||
0100001111111101
|
||||
0100011000000010
|
||||
0100011110101000
|
||||
0100100011101001
|
||||
0100100111000010
|
||||
0100101000101111
|
||||
0100101000101111
|
||||
0100100111000010
|
||||
0100100011101001
|
||||
0100011110101000
|
||||
0100011000000010
|
||||
0100001111111101
|
||||
0100000110100001
|
||||
0011111011110100
|
||||
0011110000000000
|
||||
0011100011001110
|
||||
0011010101101000
|
||||
0011000111011001
|
||||
0010111000101100
|
||||
0010101001101011
|
||||
0010011010100001
|
||||
0010001011011001
|
||||
0001111100011100
|
||||
0001101101110011
|
||||
0001011111100111
|
||||
0001010010000000
|
||||
0001000101000100
|
||||
0000111000111000
|
||||
0000101101100010
|
||||
0000100011000101
|
||||
0000011001100100
|
||||
0000010001000000
|
||||
0000001001011001
|
||||
0000000010101110
|
||||
1111111101000001
|
||||
1111111000001100
|
||||
1111110100001110
|
||||
1111110001000011
|
||||
1111101110101000
|
||||
1111101100111001
|
||||
1111101011110001
|
||||
1111101011001011
|
||||
1111101011000100
|
||||
1111101011010111
|
||||
1111101011111110
|
||||
1111101100110111
|
||||
1111101101111101
|
||||
1111101111001101
|
||||
1111110000100011
|
||||
1111110001111101
|
||||
1111110011011000
|
||||
1111110100110001
|
||||
1111110110001000
|
||||
1111110111011011
|
||||
1111111000101000
|
||||
1111111001101111
|
||||
1111111010101111
|
||||
1111111011101001
|
||||
1111111100011100
|
||||
1111111101001000
|
||||
1111111101101110
|
||||
1111111110001110
|
||||
1111111110101001
|
||||
1111111110111111
|
||||
1111111111010001
|
||||
1111111111011111
|
||||
1111111111101001
|
||||
1111111111110001
|
||||
1111111111110110
|
||||
1111111111111000
|
||||
@@ -0,0 +1,128 @@
|
||||
0000000000000001
|
||||
0000000000001011
|
||||
0000000000011110
|
||||
0000000000111100
|
||||
0000000001100011
|
||||
0000000010010100
|
||||
0000000011001110
|
||||
0000000100010010
|
||||
0000000101011111
|
||||
0000000110110101
|
||||
0000001000010100
|
||||
0000001001111011
|
||||
0000001011101011
|
||||
0000001101100010
|
||||
0000001111100010
|
||||
0000010001101001
|
||||
0000010011110111
|
||||
0000010110001100
|
||||
0000011000101000
|
||||
0000011011001001
|
||||
0000011101110000
|
||||
0000100000011101
|
||||
0000100011001110
|
||||
0000100110000100
|
||||
0000101000111101
|
||||
0000101011111011
|
||||
0000101110111011
|
||||
0000110001111110
|
||||
0000110101000011
|
||||
0000111000001010
|
||||
0000111011010010
|
||||
0000111110011011
|
||||
0001000001100100
|
||||
0001000100101101
|
||||
0001000111110101
|
||||
0001001010111100
|
||||
0001001110000001
|
||||
0001010001000100
|
||||
0001010100000100
|
||||
0001010111000010
|
||||
0001011001111011
|
||||
0001011100110001
|
||||
0001011111100010
|
||||
0001100010001111
|
||||
0001100100110110
|
||||
0001100111010111
|
||||
0001101001110011
|
||||
0001101100001000
|
||||
0001101110010110
|
||||
0001110000011101
|
||||
0001110010011101
|
||||
0001110100010100
|
||||
0001110110000100
|
||||
0001110111101011
|
||||
0001111001001010
|
||||
0001111010100000
|
||||
0001111011101101
|
||||
0001111100110001
|
||||
0001111101101011
|
||||
0001111110011100
|
||||
0001111111000011
|
||||
0001111111100001
|
||||
0001111111110100
|
||||
0001111111111110
|
||||
0001111111111110
|
||||
0001111111110100
|
||||
0001111111100001
|
||||
0001111111000011
|
||||
0001111110011100
|
||||
0001111101101011
|
||||
0001111100110001
|
||||
0001111011101101
|
||||
0001111010100000
|
||||
0001111001001010
|
||||
0001110111101011
|
||||
0001110110000100
|
||||
0001110100010100
|
||||
0001110010011101
|
||||
0001110000011101
|
||||
0001101110010110
|
||||
0001101100001000
|
||||
0001101001110011
|
||||
0001100111010111
|
||||
0001100100110110
|
||||
0001100010001111
|
||||
0001011111100010
|
||||
0001011100110001
|
||||
0001011001111011
|
||||
0001010111000010
|
||||
0001010100000100
|
||||
0001010001000100
|
||||
0001001110000001
|
||||
0001001010111100
|
||||
0001000111110101
|
||||
0001000100101101
|
||||
0001000001100100
|
||||
0000111110011011
|
||||
0000111011010010
|
||||
0000111000001010
|
||||
0000110101000011
|
||||
0000110001111110
|
||||
0000101110111011
|
||||
0000101011111011
|
||||
0000101000111101
|
||||
0000100110000100
|
||||
0000100011001110
|
||||
0000100000011101
|
||||
0000011101110000
|
||||
0000011011001001
|
||||
0000011000101000
|
||||
0000010110001100
|
||||
0000010011110111
|
||||
0000010001101001
|
||||
0000001111100010
|
||||
0000001101100010
|
||||
0000001011101011
|
||||
0000001001111011
|
||||
0000001000010100
|
||||
0000000110110101
|
||||
0000000101011111
|
||||
0000000100010010
|
||||
0000000011001110
|
||||
0000000010010100
|
||||
0000000001100011
|
||||
0000000000111100
|
||||
0000000000011110
|
||||
0000000000001011
|
||||
0000000000000001
|
||||
@@ -0,0 +1,128 @@
|
||||
0000000000000110
|
||||
0000000000001011
|
||||
0000000000010010
|
||||
0000000000011011
|
||||
0000000000100111
|
||||
0000000000110110
|
||||
0000000001000111
|
||||
0000000001011101
|
||||
0000000001110111
|
||||
0000000010010101
|
||||
0000000010111001
|
||||
0000000011100010
|
||||
0000000100010001
|
||||
0000000101001000
|
||||
0000000110000101
|
||||
0000000111001010
|
||||
0000001000011000
|
||||
0000001001101111
|
||||
0000001011001110
|
||||
0000001100111000
|
||||
0000001110101100
|
||||
0000010000101010
|
||||
0000010010110011
|
||||
0000010101000111
|
||||
0000010111100111
|
||||
0000011010010010
|
||||
0000011101001000
|
||||
0000100000001010
|
||||
0000100011010111
|
||||
0000100110110000
|
||||
0000101010010011
|
||||
0000101110000001
|
||||
0000110001111001
|
||||
0000110101111011
|
||||
0000111010000101
|
||||
0000111110011000
|
||||
0001000010110010
|
||||
0001000111010011
|
||||
0001001011111001
|
||||
0001010000100011
|
||||
0001010101010000
|
||||
0001011010000000
|
||||
0001011110110000
|
||||
0001100011100000
|
||||
0001101000001110
|
||||
0001101100111000
|
||||
0001110001011101
|
||||
0001110101111101
|
||||
0001111010010100
|
||||
0001111110100011
|
||||
0010000010100110
|
||||
0010000110011110
|
||||
0010001010001001
|
||||
0010001101100101
|
||||
0010010000110001
|
||||
0010010011101101
|
||||
0010010110010110
|
||||
0010011000101101
|
||||
0010011010101111
|
||||
0010011100011101
|
||||
0010011101110110
|
||||
0010011110111001
|
||||
0010011111100110
|
||||
0010011111111101
|
||||
0010011111111101
|
||||
0010011111100110
|
||||
0010011110111001
|
||||
0010011101110110
|
||||
0010011100011101
|
||||
0010011010101111
|
||||
0010011000101101
|
||||
0010010110010110
|
||||
0010010011101101
|
||||
0010010000110001
|
||||
0010001101100101
|
||||
0010001010001001
|
||||
0010000110011110
|
||||
0010000010100110
|
||||
0001111110100011
|
||||
0001111010010100
|
||||
0001110101111101
|
||||
0001110001011101
|
||||
0001101100111000
|
||||
0001101000001110
|
||||
0001100011100000
|
||||
0001011110110000
|
||||
0001011010000000
|
||||
0001010101010000
|
||||
0001010000100011
|
||||
0001001011111001
|
||||
0001000111010011
|
||||
0001000010110010
|
||||
0000111110011000
|
||||
0000111010000101
|
||||
0000110101111011
|
||||
0000110001111001
|
||||
0000101110000001
|
||||
0000101010010011
|
||||
0000100110110000
|
||||
0000100011010111
|
||||
0000100000001010
|
||||
0000011101001000
|
||||
0000011010010010
|
||||
0000010111100111
|
||||
0000010101000111
|
||||
0000010010110011
|
||||
0000010000101010
|
||||
0000001110101100
|
||||
0000001100111000
|
||||
0000001011001110
|
||||
0000001001101111
|
||||
0000001000011000
|
||||
0000000111001010
|
||||
0000000110000101
|
||||
0000000101001000
|
||||
0000000100010001
|
||||
0000000011100010
|
||||
0000000010111001
|
||||
0000000010010101
|
||||
0000000001110111
|
||||
0000000001011101
|
||||
0000000001000111
|
||||
0000000000110110
|
||||
0000000000100111
|
||||
0000000000011011
|
||||
0000000000010010
|
||||
0000000000001011
|
||||
0000000000000110
|
||||
@@ -0,0 +1,117 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16:59:45 05/05/2020
|
||||
-- Design Name:
|
||||
-- Module Name: MAX2871 - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity MAX2871 is
|
||||
Generic (CLK_DIV : integer);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RESET : in STD_LOGIC;
|
||||
REG4 : in STD_LOGIC_VECTOR (31 downto 0);
|
||||
REG3 : in STD_LOGIC_VECTOR (31 downto 0);
|
||||
REG1 : in STD_LOGIC_VECTOR (31 downto 0);
|
||||
REG0 : in STD_LOGIC_VECTOR (31 downto 0);
|
||||
RELOAD : in STD_LOGIC;
|
||||
CLK_OUT : out STD_LOGIC;
|
||||
MOSI : out STD_LOGIC;
|
||||
LE : out STD_LOGIC;
|
||||
DONE : out STD_LOGIC);
|
||||
end MAX2871;
|
||||
|
||||
architecture Behavioral of MAX2871 is
|
||||
signal clk_cnt : integer range 0 to (CLK_DIV/2)-1;
|
||||
signal reg_cnt : integer range 0 to 3;
|
||||
signal bit_cnt : integer range 0 to 32;
|
||||
signal latched_regs : std_logic_vector(127 downto 0);
|
||||
|
||||
signal sclk : std_logic;
|
||||
signal latch : std_logic;
|
||||
signal done_int : std_logic;
|
||||
begin
|
||||
|
||||
CLK_OUT <= sclk;
|
||||
MOSI <= latched_regs(127);
|
||||
LE <= latch;
|
||||
DONE <= done_int;
|
||||
|
||||
process(CLK, RESET)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RESET = '1' then
|
||||
sclk <= '0';
|
||||
latch <= '0';
|
||||
done_int <= '1';
|
||||
else
|
||||
if done_int = '1' then
|
||||
-- can start a new reload process
|
||||
if RELOAD = '1' then
|
||||
done_int <= '0';
|
||||
latched_regs <= REG4 & REG3 & REG1 & REG0;
|
||||
reg_cnt <= 0;
|
||||
bit_cnt <= 0;
|
||||
clk_cnt <= 0;
|
||||
end if;
|
||||
else
|
||||
if clk_cnt < (CLK_DIV/2) - 1 then
|
||||
clk_cnt <= clk_cnt + 1;
|
||||
else
|
||||
clk_cnt <= 0;
|
||||
-- advance SPI state machine
|
||||
if bit_cnt < 32 then
|
||||
if sclk = '0' then
|
||||
sclk <= '1';
|
||||
else
|
||||
-- falling edge of clk, shift out new bit
|
||||
sclk <= '0';
|
||||
latched_regs <= latched_regs(126 downto 0) & "0";
|
||||
bit_cnt <= bit_cnt + 1;
|
||||
end if;
|
||||
else
|
||||
-- shifted out one register, strobe latch
|
||||
if latch = '0' then
|
||||
latch <= '1';
|
||||
else
|
||||
latch <= '0';
|
||||
-- move on to next register
|
||||
if reg_cnt < 3 then
|
||||
reg_cnt <= reg_cnt + 1;
|
||||
bit_cnt <= 0;
|
||||
else
|
||||
-- all done
|
||||
done_int <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,161 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16:01:43 05/05/2020
|
||||
-- Design Name:
|
||||
-- Module Name: MCP33131 - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity MCP33131 is
|
||||
Generic(CLK_DIV : integer;
|
||||
CONVCYCLES : integer);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RESET : in STD_LOGIC;
|
||||
START : in STD_LOGIC;
|
||||
READY : out STD_LOGIC;
|
||||
DATA : out STD_LOGIC_VECTOR (15 downto 0);
|
||||
MIN : out STD_LOGIC_VECTOR (15 downto 0);
|
||||
MAX : out STD_LOGIC_VECTOR (15 downto 0);
|
||||
RESET_MINMAX : in STD_LOGIC;
|
||||
SDO : in STD_LOGIC;
|
||||
CONVSTART : out STD_LOGIC;
|
||||
SCLK : inout STD_LOGIC);
|
||||
end MCP33131;
|
||||
|
||||
architecture Behavioral of MCP33131 is
|
||||
signal conv_cnt : integer range 0 to CONVCYCLES-1;
|
||||
signal div_cnt : integer range 0 to (CLK_DIV/2)-1;
|
||||
signal bit_cnt : integer range 0 to 15;
|
||||
signal sclk_phase : std_logic;
|
||||
signal adc_data : std_logic_vector(15 downto 0);
|
||||
type States is (Idle, Conversion, WAIT_tEN, Transmission, Done);
|
||||
signal state : States;
|
||||
signal ready_int : std_logic;
|
||||
signal ready_delay : integer range 0 to 30;
|
||||
signal min_int, max_int, data_int : signed(15 downto 0);
|
||||
begin
|
||||
|
||||
MIN <= std_logic_vector(min_int);
|
||||
MAX <= std_logic_vector(max_int);
|
||||
DATA <= std_logic_vector(data_int);
|
||||
SCLK <= sclk_phase;
|
||||
|
||||
process(SCLK, START)
|
||||
begin
|
||||
if(falling_edge(SCLK)) then
|
||||
adc_data <= adc_data(14 downto 0) & SDO;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(CLK, RESET)
|
||||
begin
|
||||
if(rising_edge(CLK)) then
|
||||
if(RESET = '1') then
|
||||
state <= Idle;
|
||||
READY <= '0';
|
||||
ready_int <= '0';
|
||||
CONVSTART <= '0';
|
||||
sclk_phase <= '0';
|
||||
CONVSTART <= '0';
|
||||
conv_cnt <= 0;
|
||||
div_cnt <= 0;
|
||||
bit_cnt <= 0;
|
||||
min_int <= to_signed(32767, 16);
|
||||
max_int <= to_signed(-32768, 16);
|
||||
else
|
||||
if RESET_MINMAX = '1' then
|
||||
min_int <= to_signed(32767, 16);
|
||||
max_int <= to_signed(-32768, 16);
|
||||
else
|
||||
if data_int < min_int then
|
||||
min_int <= data_int;
|
||||
end if;
|
||||
if data_int > max_int then
|
||||
max_int <= data_int;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
READY <= '0';
|
||||
if ready_int = '1' then
|
||||
ready_delay <= 3;
|
||||
else
|
||||
if ready_delay > 0 then
|
||||
ready_delay <= ready_delay - 1;
|
||||
end if;
|
||||
if ready_delay = 1 then
|
||||
READY <= '1';
|
||||
data_int <= signed(adc_data);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
case state is
|
||||
when Idle =>
|
||||
ready_int <= '0';
|
||||
if START = '1' then
|
||||
state <= Conversion;
|
||||
conv_cnt <= 0;
|
||||
CONVSTART <= '1';
|
||||
end if;
|
||||
when Conversion =>
|
||||
ready_int <= '0';
|
||||
if(conv_cnt < CONVCYCLES-1) then
|
||||
conv_cnt <= conv_cnt + 1;
|
||||
else
|
||||
div_cnt <= 0;
|
||||
CONVSTART <= '0';
|
||||
state <= WAIT_tEN;
|
||||
end if;
|
||||
when WAIT_tEN =>
|
||||
ready_int <= '0';
|
||||
state <= Transmission;
|
||||
when Transmission =>
|
||||
ready_int <= '0';
|
||||
if(div_cnt < (CLK_DIV/2)-1) then
|
||||
div_cnt <= div_cnt + 1;
|
||||
else
|
||||
if(sclk_phase = '0') then
|
||||
sclk_phase <= '1';
|
||||
else
|
||||
sclk_phase <= '0';
|
||||
if bit_cnt = 15 then
|
||||
state <= Done;
|
||||
bit_cnt <= 0;
|
||||
else
|
||||
bit_cnt <= bit_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
div_cnt <= 0;
|
||||
end if;
|
||||
when Done =>
|
||||
ready_int <= '1';
|
||||
state <= Idle;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 20:06:31 05/12/2020
|
||||
-- Design Name:
|
||||
-- Module Name: ResetDelay - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity ResetDelay is
|
||||
Generic(CLK_DELAY : integer);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
IN_RESET : in STD_LOGIC;
|
||||
OUT_RESET : out STD_LOGIC);
|
||||
end ResetDelay;
|
||||
|
||||
architecture Behavioral of ResetDelay is
|
||||
signal clk_cnt : integer range 0 to CLK_DELAY-1;
|
||||
begin
|
||||
|
||||
process(CLK, IN_RESET)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if IN_RESET = '1' then
|
||||
clk_cnt <= 0;
|
||||
OUT_RESET <= '1';
|
||||
else
|
||||
if clk_cnt < CLK_DELAY-1 then
|
||||
clk_cnt <= clk_cnt + 1;
|
||||
else
|
||||
OUT_RESET <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,329 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 19:51:11 05/05/2020
|
||||
-- Design Name:
|
||||
-- Module Name: SPICommands - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity SPICommands is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RESET : in STD_LOGIC;
|
||||
SCLK : in STD_LOGIC;
|
||||
MOSI : in STD_LOGIC;
|
||||
MISO : out STD_LOGIC;
|
||||
NSS : in STD_LOGIC;
|
||||
NEW_SAMPLING_DATA : in STD_LOGIC;
|
||||
SAMPLING_RESULT : in STD_LOGIC_VECTOR (303 downto 0);
|
||||
ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
|
||||
SOURCE_UNLOCKED : in STD_LOGIC;
|
||||
LO_UNLOCKED : in STD_LOGIC;
|
||||
MAX2871_DEF_4 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
MAX2871_DEF_3 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
MAX2871_DEF_1 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
MAX2871_DEF_0 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
SWEEP_DATA : out STD_LOGIC_VECTOR (95 downto 0);
|
||||
SWEEP_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
|
||||
SWEEP_WRITE : out STD_LOGIC_VECTOR (0 downto 0);
|
||||
SWEEP_POINTS : out STD_LOGIC_VECTOR (12 downto 0);
|
||||
NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
|
||||
STAGES : out STD_LOGIC_VECTOR (2 downto 0);
|
||||
SETTLING_TIME : out STD_LOGIC_VECTOR (19 downto 0);
|
||||
SYNC_ENABLED : out STD_LOGIC;
|
||||
SYNC_MASTER : out STD_LOGIC;
|
||||
PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
|
||||
PORT2_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
|
||||
PORT1_EN : out STD_LOGIC;
|
||||
PORT2_EN : out STD_LOGIC;
|
||||
REF_EN : out STD_LOGIC;
|
||||
AMP_SHDN : out STD_LOGIC;
|
||||
SOURCE_RF_EN : out STD_LOGIC;
|
||||
LO_RF_EN : out STD_LOGIC;
|
||||
SOURCE_CE_EN : out STD_LOGIC;
|
||||
LO_CE_EN : out STD_LOGIC;
|
||||
PORTSWITCH_EN : out STD_LOGIC;
|
||||
LEDS : out STD_LOGIC_VECTOR(2 downto 0);
|
||||
WINDOW_SETTING : out STD_LOGIC_VECTOR(1 downto 0);
|
||||
ADC_PRESCALER : out STD_LOGIC_VECTOR(7 downto 0);
|
||||
ADC_PHASEINC : out STD_LOGIC_VECTOR(11 downto 0);
|
||||
INTERRUPT_ASSERTED : out STD_LOGIC;
|
||||
RESET_MINMAX : out STD_LOGIC;
|
||||
SWEEP_HALTED : in STD_LOGIC;
|
||||
SWEEP_RESUME : out STD_LOGIC;
|
||||
|
||||
-- hardware overwrite signals
|
||||
SPI_OVERWRITE_ENABLED : out STD_LOGIC;
|
||||
SPI_OVERWRITE_DATA : out STD_LOGIC_VECTOR(14 downto 0);
|
||||
|
||||
-- DFT signals
|
||||
DFT_BIN1_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
|
||||
DFT_DIFFBIN_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
|
||||
DFT_RESULT_READY : in STD_LOGIC;
|
||||
DFT_OUTPUT : in STD_LOGIC_VECTOR (191 downto 0);
|
||||
DFT_NEXT_OUTPUT : out STD_LOGIC;
|
||||
DFT_ENABLE : out STD_LOGIC;
|
||||
|
||||
DEBUG_STATUS : in STD_LOGIC_VECTOR(10 downto 0));
|
||||
end SPICommands;
|
||||
|
||||
architecture Behavioral of SPICommands is
|
||||
COMPONENT spi_slave
|
||||
Generic(W : integer;
|
||||
PREWIDTH : integer);
|
||||
PORT(
|
||||
SPI_CLK : in STD_LOGIC;
|
||||
MISO : out STD_LOGIC;
|
||||
MOSI : in STD_LOGIC;
|
||||
CS : in STD_LOGIC;
|
||||
BUF_OUT : out STD_LOGIC_VECTOR (W-1 downto 0) := (others => '0');
|
||||
BUF_IN : in STD_LOGIC_VECTOR (W-1 downto 0);
|
||||
CLK : in STD_LOGIC;
|
||||
COMPLETE : out STD_LOGIC;
|
||||
PRE_COMPLETE : out STD_LOGIC;
|
||||
PRE_BUF_OUT : out STD_LOGIC_VECTOR (PREWIDTH-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- SPI control signals
|
||||
signal spi_buf_out : std_logic_vector(15 downto 0);
|
||||
signal spi_buf_in : std_logic_vector(15 downto 0);
|
||||
signal spi_complete : std_logic;
|
||||
signal spi_pre_complete : std_logic;
|
||||
signal spi_pre_buf_out : std_logic_vector(2 downto 0);
|
||||
signal word_cnt : integer range 0 to 19;
|
||||
type SPI_states is (FirstWord, WriteSweepConfig, ReadResult, WriteRegister);
|
||||
signal state : SPI_states;
|
||||
signal selected_register : integer range 0 to 31;
|
||||
|
||||
signal dft_next : std_logic;
|
||||
|
||||
signal last_NSS : std_logic;
|
||||
|
||||
signal sweep_config_write : std_logic;
|
||||
signal unread_sampling_data : std_logic;
|
||||
signal data_overrun : std_logic;
|
||||
-- Configuration registers
|
||||
signal interrupt_mask : std_logic_vector(15 downto 0);
|
||||
signal interrupt_status : std_logic_vector(15 downto 0);
|
||||
|
||||
signal latched_result : std_logic_vector(287 downto 0);
|
||||
signal sweepconfig_buffer : std_logic_vector(79 downto 0);
|
||||
begin
|
||||
SPI: spi_slave
|
||||
GENERIC MAP(W => 16,
|
||||
PREWIDTH => 3)
|
||||
PORT MAP(
|
||||
SPI_CLK => SCLK,
|
||||
MISO => MISO,
|
||||
MOSI => MOSI,
|
||||
CS => NSS,
|
||||
BUF_OUT => spi_buf_out,
|
||||
BUF_IN => spi_buf_in,
|
||||
CLK => CLK,
|
||||
COMPLETE => spi_complete,
|
||||
PRE_COMPLETE => spi_pre_complete,
|
||||
PRE_BUF_OUT => spi_pre_buf_out
|
||||
);
|
||||
|
||||
SWEEP_WRITE(0) <= sweep_config_write;
|
||||
DFT_NEXT_OUTPUT <= dft_next;
|
||||
DFT_ENABLE <= interrupt_mask(5);
|
||||
|
||||
process(CLK, RESET)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RESET = '1' then
|
||||
sweep_config_write <= '0';
|
||||
data_overrun <= '0';
|
||||
SWEEP_POINTS <= (others => '0');
|
||||
NSAMPLES <= (others => '0');
|
||||
--SETTLING_TIME <= (others => '0');
|
||||
PORT1_EN <= '0';
|
||||
PORT2_EN <= '0';
|
||||
REF_EN <= '0';
|
||||
AMP_SHDN <= '1';
|
||||
SOURCE_RF_EN <= '0';
|
||||
LO_RF_EN <= '0';
|
||||
SOURCE_CE_EN <= '0';
|
||||
LO_CE_EN <= '0';
|
||||
PORTSWITCH_EN <= '0';
|
||||
LEDS <= (others => '1');
|
||||
WINDOW_SETTING <= "00";
|
||||
unread_sampling_data <= '0';
|
||||
interrupt_mask <= (others => '0');
|
||||
ADC_PRESCALER <= std_logic_vector(to_unsigned(112, 8));
|
||||
ADC_PHASEINC <= std_logic_vector(to_unsigned(1120, 12));
|
||||
RESET_MINMAX <= '0';
|
||||
INTERRUPT_ASSERTED <= '0';
|
||||
latched_result <= (others => '0');
|
||||
|
||||
SPI_OVERWRITE_ENABLED <= '0';
|
||||
SPI_OVERWRITE_DATA <= (others => '0');
|
||||
|
||||
DFT_BIN1_PHASEINC <= (others => '0');
|
||||
DFT_DIFFBIN_PHASEINC <= (others => '0');
|
||||
dft_next <= '0';
|
||||
last_NSS <= '1';
|
||||
else
|
||||
interrupt_status <= DEBUG_STATUS(10 downto 1) & DFT_RESULT_READY & SWEEP_HALTED & data_overrun & unread_sampling_data & SOURCE_UNLOCKED & LO_UNLOCKED;
|
||||
if (interrupt_status and interrupt_mask) = "0000000000000000" then
|
||||
INTERRUPT_ASSERTED <= '0';
|
||||
else
|
||||
INTERRUPT_ASSERTED <= '1';
|
||||
end if;
|
||||
if sweep_config_write = '1' then
|
||||
sweep_config_write <= '0';
|
||||
end if;
|
||||
if dft_next = '1' then
|
||||
dft_next <= '0';
|
||||
end if;
|
||||
RESET_MINMAX <= '0';
|
||||
SWEEP_RESUME <= '0';
|
||||
if NEW_SAMPLING_DATA = '1' then
|
||||
unread_sampling_data <= '1';
|
||||
if unread_sampling_data = '1' then
|
||||
data_overrun <= '1';
|
||||
end if;
|
||||
end if;
|
||||
last_NSS <= NSS;
|
||||
if NSS = '0' and last_NSS = '1' then
|
||||
word_cnt <= 0;
|
||||
spi_buf_in <= interrupt_status;
|
||||
state <= FirstWord;
|
||||
else
|
||||
-- handle read operations when the first PREWIDTH bits are complete
|
||||
if spi_pre_complete = '1' then
|
||||
case state is
|
||||
when FirstWord =>
|
||||
-- initial word determines the action
|
||||
case spi_pre_buf_out is
|
||||
when "010" => state <= FirstWord;
|
||||
spi_buf_in <= "1111000010100101";
|
||||
when "101" => state <= ReadResult;-- can use same state as read result, but the latched data will contain the DFT values
|
||||
latched_result(175 downto 0) <= DFT_OUTPUT(191 downto 16);
|
||||
spi_buf_in <= DFT_OUTPUT(15 downto 0);
|
||||
dft_next <= '1';
|
||||
when "110" => state <= ReadResult;
|
||||
latched_result <= SAMPLING_RESULT(303 downto 16);
|
||||
spi_buf_in <= SAMPLING_RESULT(15 downto 0);
|
||||
unread_sampling_data <= '0';
|
||||
when "111" => state <= ReadResult; -- can use same state as read result, but the latched data will contain the min/max ADC values
|
||||
latched_result(79 downto 0) <= ADC_MINMAX(95 downto 16);
|
||||
spi_buf_in <= ADC_MINMAX(15 downto 0);
|
||||
--ignore other options
|
||||
when others =>
|
||||
end case;
|
||||
when ReadResult =>
|
||||
-- pass on next word of latched result
|
||||
spi_buf_in <= latched_result(15 downto 0);
|
||||
latched_result <= "0000000000000000" & latched_result(287 downto 16);
|
||||
when others =>
|
||||
end case;
|
||||
end if;
|
||||
-- handle write operations when the whole word is complete
|
||||
if spi_complete = '1' then
|
||||
word_cnt <= word_cnt + 1;
|
||||
case state is
|
||||
when FirstWord =>
|
||||
-- initial word determines action
|
||||
case spi_buf_out(15 downto 13) is
|
||||
when "000" => state <= WriteSweepConfig;
|
||||
-- also extract the point number
|
||||
SWEEP_ADDRESS <= spi_buf_out(12 downto 0);
|
||||
when "001" => state <= FirstWord;
|
||||
SWEEP_RESUME <= '1';
|
||||
when "011" => state <= FirstWord;
|
||||
RESET_MINMAX <= '1';
|
||||
when "100" => state <= WriteRegister;
|
||||
selected_register <= to_integer(unsigned(spi_buf_out(4 downto 0)));
|
||||
-- ignore read options (already handled in other state machine)
|
||||
when "010" =>
|
||||
when "101" =>
|
||||
when "110" =>
|
||||
when "111" =>
|
||||
when others => state <= FirstWord;
|
||||
end case;
|
||||
when WriteRegister =>
|
||||
-- write received data into previously selected register
|
||||
case selected_register is
|
||||
when 0 => interrupt_mask <= spi_buf_out;
|
||||
when 1 => SWEEP_POINTS <= spi_buf_out(12 downto 0);
|
||||
when 2 => NSAMPLES <= spi_buf_out(12 downto 0);
|
||||
when 3 => PORTSWITCH_EN <= spi_buf_out(0);
|
||||
PORT1_EN <= spi_buf_out(15);
|
||||
PORT2_EN <= spi_buf_out(14);
|
||||
REF_EN <= spi_buf_out(13);
|
||||
AMP_SHDN <= not spi_buf_out(12);
|
||||
SOURCE_RF_EN <= spi_buf_out(11);
|
||||
LO_RF_EN <= spi_buf_out(10);
|
||||
LEDS <= not spi_buf_out(9 downto 7);
|
||||
WINDOW_SETTING <= spi_buf_out(6 downto 5);
|
||||
SOURCE_CE_EN <= spi_buf_out(4);
|
||||
LO_CE_EN <= spi_buf_out(3);
|
||||
SYNC_MASTER <= spi_buf_out(1);
|
||||
when 4 => ADC_PRESCALER <= spi_buf_out(7 downto 0);
|
||||
when 5 => ADC_PHASEINC <= spi_buf_out(11 downto 0);
|
||||
when 6 => STAGES <= spi_buf_out(15 downto 13);
|
||||
SYNC_ENABLED <= spi_buf_out(12);
|
||||
PORT1_STAGE <= spi_buf_out(5 downto 3);
|
||||
PORT2_STAGE <= spi_buf_out(2 downto 0);
|
||||
when 7 => SPI_OVERWRITE_ENABLED <= spi_buf_out(15);
|
||||
SPI_OVERWRITE_DATA <= spi_buf_out(14 downto 0);
|
||||
when 8 => MAX2871_DEF_0(15 downto 0) <= spi_buf_out;
|
||||
when 9 => MAX2871_DEF_0(31 downto 16) <= spi_buf_out;
|
||||
when 10 => MAX2871_DEF_1(15 downto 0) <= spi_buf_out;
|
||||
when 11 => MAX2871_DEF_1(31 downto 16) <= spi_buf_out;
|
||||
when 12 => MAX2871_DEF_3(15 downto 0) <= spi_buf_out;
|
||||
when 13 => MAX2871_DEF_3(31 downto 16) <= spi_buf_out;
|
||||
when 14 => MAX2871_DEF_4(15 downto 0) <= spi_buf_out;
|
||||
when 15 => MAX2871_DEF_4(31 downto 16) <= spi_buf_out;
|
||||
when 18 => DFT_BIN1_PHASEINC <= spi_buf_out;
|
||||
when 19 => DFT_DIFFBIN_PHASEINC <= spi_buf_out;
|
||||
when 20 => SETTLING_TIME(15 downto 0) <= spi_buf_out;
|
||||
when 21 => SETTLING_TIME(19 downto 16) <= spi_buf_out(3 downto 0);
|
||||
when others =>
|
||||
end case;
|
||||
selected_register <= selected_register + 1;
|
||||
when WriteSweepConfig =>
|
||||
if word_cnt = 6 then
|
||||
-- Sweep config data is complete pass on
|
||||
SWEEP_DATA <= sweepconfig_buffer & spi_buf_out;
|
||||
sweep_config_write <= '1';
|
||||
else
|
||||
-- shift next word into buffer
|
||||
sweepconfig_buffer <= sweepconfig_buffer(63 downto 0) & spi_buf_out;
|
||||
end if;
|
||||
-- read already handled in pre_complete, ignore
|
||||
when ReadResult =>
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,301 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:27:54 05/05/2020
|
||||
-- Design Name:
|
||||
-- Module Name: Sampling - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Sampling is
|
||||
Generic(CLK_CYCLES_PRE_DONE : integer);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RESET : in STD_LOGIC;
|
||||
ADC_PRESCALER : in STD_LOGIC_VECTOR(7 downto 0);
|
||||
PHASEINC : in STD_LOGIC_VECTOR(11 downto 0);
|
||||
PORT1 : in STD_LOGIC_VECTOR (17 downto 0);
|
||||
PORT2 : in STD_LOGIC_VECTOR (17 downto 0);
|
||||
REF : in STD_LOGIC_VECTOR (17 downto 0);
|
||||
ADC_START : out STD_LOGIC;
|
||||
NEW_SAMPLE : in STD_LOGIC;
|
||||
DONE : out STD_LOGIC;
|
||||
PRE_DONE : out STD_LOGIC;
|
||||
START : in STD_LOGIC;
|
||||
SAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
|
||||
PORT1_I : out STD_LOGIC_VECTOR (47 downto 0);
|
||||
PORT1_Q : out STD_LOGIC_VECTOR (47 downto 0);
|
||||
PORT2_I : out STD_LOGIC_VECTOR (47 downto 0);
|
||||
PORT2_Q : out STD_LOGIC_VECTOR (47 downto 0);
|
||||
REF_I : out STD_LOGIC_VECTOR (47 downto 0);
|
||||
REF_Q : out STD_LOGIC_VECTOR (47 downto 0);
|
||||
ACTIVE : out STD_LOGIC);
|
||||
end Sampling;
|
||||
|
||||
architecture Behavioral of Sampling is
|
||||
COMPONENT SinCos
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT DSP_SLICE
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
ce : IN STD_LOGIC;
|
||||
sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||
p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT window
|
||||
PORT(
|
||||
CLK : IN std_logic;
|
||||
INDEX : IN std_logic_vector(6 downto 0);
|
||||
WINDOW_TYPE : IN std_logic_vector(1 downto 0);
|
||||
VALUE : OUT std_logic_vector(15 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal p1_I : std_logic_vector(47 downto 0);
|
||||
signal p1_Q : std_logic_vector(47 downto 0);
|
||||
signal p2_I : std_logic_vector(47 downto 0);
|
||||
signal p2_Q : std_logic_vector(47 downto 0);
|
||||
signal r_I : std_logic_vector(47 downto 0);
|
||||
signal r_Q : std_logic_vector(47 downto 0);
|
||||
signal clk_cnt : integer range 0 to 255;
|
||||
signal sample_cnt : integer range 0 to 131071;
|
||||
signal samples_to_take : integer range 0 to 131071;
|
||||
|
||||
signal phase : std_logic_vector(11 downto 0);
|
||||
signal sine : std_logic_vector(15 downto 0);
|
||||
signal cosine : std_logic_vector(15 downto 0);
|
||||
|
||||
signal mult_a : std_logic_vector(17 downto 0);
|
||||
signal mult_b : std_logic_vector(17 downto 0);
|
||||
signal mult_c : std_logic_vector(47 downto 0);
|
||||
signal mult_p : std_logic_vector(47 downto 0);
|
||||
|
||||
signal mult_enable : std_logic;
|
||||
signal mult_accumulate : std_logic_vector(0 downto 0);
|
||||
|
||||
type States is (Idle, Sampling, P1Q, P2I, P2Q, RI, RQ, SaveP1Q, SaveP2I, SaveP2Q, SaveRI, SaveRQ, Ready);
|
||||
signal state : States;
|
||||
begin
|
||||
-- Always fails for simulation, comment out
|
||||
-- assert (phase_inc * CLK_FREQ / (4096*CLK_DIV) = IF_FREQ)
|
||||
-- report "Phase increment not exact"
|
||||
-- severity FAILURE;
|
||||
|
||||
LookupTable : SinCos
|
||||
PORT MAP (
|
||||
clk => CLK,
|
||||
phase_in => phase,
|
||||
cosine => cosine,
|
||||
sine => sine
|
||||
);
|
||||
|
||||
Mult : DSP_SLICE
|
||||
PORT MAP (
|
||||
clk => CLK,
|
||||
ce => mult_enable,
|
||||
sel => mult_accumulate,
|
||||
a => mult_a,
|
||||
b => mult_b,
|
||||
c => mult_c,
|
||||
p => mult_p
|
||||
);
|
||||
|
||||
-- sign extend b input of multiplier (sin/cos)
|
||||
mult_b(17 downto 16) <= mult_b(15) & mult_b(15);
|
||||
|
||||
process(CLK, RESET)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RESET = '1' then
|
||||
state <= Idle;
|
||||
ADC_START <= '0';
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
ACTIVE <= '0';
|
||||
clk_cnt <= 0;
|
||||
sample_cnt <= 0;
|
||||
phase <= (others => '0');
|
||||
mult_enable <= '0';
|
||||
mult_accumulate <= "0";
|
||||
else
|
||||
-- when not idle, generate pulses for ADCs
|
||||
if state /= Idle then
|
||||
if clk_cnt = unsigned(ADC_PRESCALER) - 1 then
|
||||
if sample_cnt < samples_to_take then
|
||||
ADC_START <= '1';
|
||||
end if;
|
||||
clk_cnt <= 0;
|
||||
else
|
||||
clk_cnt <= clk_cnt + 1;
|
||||
ADC_START <= '0';
|
||||
end if;
|
||||
else
|
||||
ADC_START <= '0';
|
||||
end if;
|
||||
-- handle state transitions
|
||||
case state is
|
||||
when Idle =>
|
||||
sample_cnt <= 0;
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
ACTIVE <= '0';
|
||||
clk_cnt <= 0;
|
||||
phase <= (others => '0');
|
||||
mult_enable <= '0';
|
||||
mult_accumulate <= "0";
|
||||
if START = '1' then
|
||||
state <= Sampling;
|
||||
samples_to_take <= to_integer(unsigned(SAMPLES & "0000"));
|
||||
end if;
|
||||
when Sampling =>
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
ACTIVE <= '1';
|
||||
mult_enable <= '0';
|
||||
if NEW_SAMPLE = '1' then
|
||||
sample_cnt <= sample_cnt + 1;
|
||||
mult_enable <= '1';
|
||||
mult_a <= PORT1;
|
||||
mult_b(15 downto 0) <= cosine;
|
||||
mult_c <= p1_I;
|
||||
state <= P1Q;
|
||||
end if;
|
||||
when P1Q =>
|
||||
ACTIVE <= '1';
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
mult_a <= PORT1;
|
||||
mult_b(15 downto 0) <= sine;
|
||||
mult_c <= p1_Q;
|
||||
state <= P2I;
|
||||
when P2I =>
|
||||
ACTIVE <= '1';
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
mult_a <= PORT2;
|
||||
mult_b(15 downto 0) <= cosine;
|
||||
mult_c <= p2_I;
|
||||
state <= P2Q;
|
||||
when P2Q =>
|
||||
ACTIVE <= '1';
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
mult_a <= PORT2;
|
||||
mult_b(15 downto 0) <= sine;
|
||||
mult_c <= p2_Q;
|
||||
state <= RI;
|
||||
when RI =>
|
||||
ACTIVE <= '1';
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
mult_a <= REF;
|
||||
mult_b(15 downto 0) <= cosine;
|
||||
mult_c <= r_I;
|
||||
state <= RQ;
|
||||
when RQ =>
|
||||
ACTIVE <= '1';
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
mult_a <= REF;
|
||||
mult_b(15 downto 0) <= sine;
|
||||
mult_c <= r_Q;
|
||||
-- first result is available
|
||||
p1_I <= mult_p;
|
||||
state <= SaveP1Q;
|
||||
when SaveP1Q =>
|
||||
ACTIVE <= '1';
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
p1_Q <= mult_p;
|
||||
state <= SaveP2I;
|
||||
when SaveP2I =>
|
||||
ACTIVE <= '1';
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
p2_I <= mult_p;
|
||||
state <= SaveP2Q;
|
||||
when SaveP2Q =>
|
||||
ACTIVE <= '1';
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
p2_Q <= mult_p;
|
||||
state <= SaveRI;
|
||||
when SaveRI =>
|
||||
ACTIVE <= '1';
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
r_I <= mult_p;
|
||||
state <= SaveRQ;
|
||||
when SaveRQ =>
|
||||
ACTIVE <= '1';
|
||||
DONE <= '0';
|
||||
PRE_DONE <= '0';
|
||||
mult_enable <= '0';
|
||||
r_Q <= mult_p;
|
||||
-- from now on accumulate results
|
||||
mult_accumulate <= "1";
|
||||
phase <= std_logic_vector(unsigned(phase) + unsigned(PHASEINC));
|
||||
if sample_cnt < samples_to_take then
|
||||
state <= Sampling;
|
||||
else
|
||||
state <= Ready;
|
||||
end if;
|
||||
when Ready =>
|
||||
ACTIVE <= '1';
|
||||
DONE <= '1';
|
||||
PRE_DONE <= '1';
|
||||
mult_enable <= '0';
|
||||
PORT1_I <= p1_I;
|
||||
PORT1_Q <= p1_Q;
|
||||
PORT2_I <= p2_I;
|
||||
PORT2_Q <= p2_Q;
|
||||
REF_I <= r_I;
|
||||
REF_Q <= r_Q;
|
||||
state <= Idle;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,272 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 21:35:02 05/06/2020
|
||||
-- Design Name:
|
||||
-- Module Name: Sweep - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Sweep is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RESET : in STD_LOGIC;
|
||||
NPOINTS : in STD_LOGIC_VECTOR (12 downto 0);
|
||||
CONFIG_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
|
||||
CONFIG_DATA : in STD_LOGIC_VECTOR (95 downto 0);
|
||||
USER_NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
|
||||
NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
|
||||
SETTLING_TIME : in STD_LOGIC_VECTOR (19 downto 0);
|
||||
SAMPLING_BUSY : in STD_LOGIC;
|
||||
SAMPLING_DONE : in STD_LOGIC;
|
||||
START_SAMPLING : out STD_LOGIC;
|
||||
BAND_SELECT : out STD_LOGIC;
|
||||
-- fixed part of source/LO registers
|
||||
MAX2871_DEF_4 : in STD_LOGIC_VECTOR (31 downto 0);
|
||||
MAX2871_DEF_3 : in STD_LOGIC_VECTOR (31 downto 0);
|
||||
MAX2871_DEF_1 : in STD_LOGIC_VECTOR (31 downto 0);
|
||||
MAX2871_DEF_0 : in STD_LOGIC_VECTOR (31 downto 0);
|
||||
-- assembled source/LO registers
|
||||
SOURCE_REG_4 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
SOURCE_REG_3 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
SOURCE_REG_1 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
SOURCE_REG_0 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
LO_REG_4 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
LO_REG_3 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
LO_REG_1 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
LO_REG_0 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
RELOAD_PLL_REGS : out STD_LOGIC;
|
||||
PLL_RELOAD_DONE : in STD_LOGIC;
|
||||
PLL_LOCKED : in STD_LOGIC;
|
||||
SWEEP_HALTED : out STD_LOGIC;
|
||||
SWEEP_RESUME : in STD_LOGIC;
|
||||
|
||||
SYNC_ENABLED : in STD_LOGIC;
|
||||
SYNC_MASTER : in STD_LOGIC;
|
||||
TRIGGER_IN : in STD_LOGIC;
|
||||
TRIGGER_OUT : out STD_LOGIC;
|
||||
|
||||
NEW_DATA : out STD_LOGIC;
|
||||
|
||||
ATTENUATOR : out STD_LOGIC_VECTOR(6 downto 0);
|
||||
SOURCE_FILTER : out STD_LOGIC_VECTOR(1 downto 0);
|
||||
|
||||
--SETTLING_TIME : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
|
||||
STAGES : in STD_LOGIC_VECTOR (2 downto 0);
|
||||
PORT1_STAGE : in STD_LOGIC_VECTOR (2 downto 0);
|
||||
PORT2_STAGE : in STD_LOGIC_VECTOR (2 downto 0);
|
||||
|
||||
PORT1_ACTIVE : out STD_LOGIC;
|
||||
PORT2_ACTIVE : out STD_LOGIC;
|
||||
|
||||
SOURCE_CE : out STD_LOGIC;
|
||||
|
||||
-- Debug signals
|
||||
DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0);
|
||||
RESULT_INDEX : out STD_LOGIC_VECTOR (15 downto 0)
|
||||
);
|
||||
end Sweep;
|
||||
|
||||
architecture Behavioral of Sweep is
|
||||
signal point_cnt : unsigned(12 downto 0);
|
||||
type Point_states is (WaitInitialLow, TriggerSetup, SettingUp, Settling, WaitTriggerHigh, Exciting, WaitTriggerLow, SamplingDone, NextPoint, Done);
|
||||
signal state : Point_states;
|
||||
signal settling_cnt : unsigned(19 downto 0);
|
||||
signal stage_cnt : unsigned (2 downto 0);
|
||||
signal config_reg : std_logic_vector(95 downto 0);
|
||||
signal source_active : std_logic;
|
||||
begin
|
||||
|
||||
CONFIG_ADDRESS <= std_logic_vector(point_cnt);
|
||||
|
||||
-- assemble registers
|
||||
-- source register 0: N divider and fractional division value
|
||||
SOURCE_REG_0 <= MAX2871_DEF_0(31) & "000000000" & config_reg(93) & config_reg(5 downto 0) & config_reg(26 downto 15) & "000";
|
||||
-- source register 1: Modulus value
|
||||
SOURCE_REG_1 <= MAX2871_DEF_1(31 downto 15) & config_reg(38 downto 27) & "001";
|
||||
-- source register 3: VCO selection
|
||||
SOURCE_REG_3 <= config_reg(11 downto 6) & MAX2871_DEF_3(25 downto 3) & "011";
|
||||
-- output power A from config, output B disabled
|
||||
SOURCE_REG_4 <= MAX2871_DEF_4(31 downto 23) & config_reg(14 downto 12) & MAX2871_DEF_4(19 downto 9) & "000" & MAX2871_DEF_4(5) & config_reg(47 downto 46) & "100";
|
||||
|
||||
-- LO register 0: N divider and fractional division value
|
||||
LO_REG_0 <= MAX2871_DEF_0(31) & "000000000" & config_reg(94) & config_reg(54 downto 49) & config_reg(75 downto 64) & "000";
|
||||
-- LO register 1: Modulus value
|
||||
LO_REG_1 <= MAX2871_DEF_1(31 downto 15) & config_reg(87 downto 76) & "001";
|
||||
-- LO register 3: VCO selection
|
||||
LO_REG_3 <= config_reg(60 downto 55) & MAX2871_DEF_3(25 downto 3) & "011";
|
||||
-- both outputs enabled at +5dbm
|
||||
LO_REG_4 <= MAX2871_DEF_4(31 downto 23) & config_reg(63 downto 61) & MAX2871_DEF_4(19 downto 9) & "111111100";
|
||||
|
||||
ATTENUATOR <= config_reg(45 downto 39);
|
||||
SOURCE_FILTER <= config_reg(89 downto 88);
|
||||
BAND_SELECT <= config_reg(48);
|
||||
SOURCE_CE <= source_active;
|
||||
|
||||
NSAMPLES <= USER_NSAMPLES when config_reg(92 downto 90) = "000" else
|
||||
std_logic_vector(to_unsigned(6, 13)) when config_reg(92 downto 90) = "001" else
|
||||
std_logic_vector(to_unsigned(19, 13)) when config_reg(92 downto 90) = "010" else
|
||||
std_logic_vector(to_unsigned(57, 13)) when config_reg(92 downto 90) = "011" else
|
||||
std_logic_vector(to_unsigned(190, 13)) when config_reg(92 downto 90) = "100" else
|
||||
std_logic_vector(to_unsigned(571, 13)) when config_reg(92 downto 90) = "101" else
|
||||
std_logic_vector(to_unsigned(1904, 13)) when config_reg(92 downto 90) = "110" else
|
||||
std_logic_vector(to_unsigned(5712, 13));
|
||||
|
||||
DEBUG_STATUS(10 downto 7) <= "0000" when state = TriggerSetup else
|
||||
"0001" when state = SettingUp else
|
||||
"0010" when state = Settling else
|
||||
"0011" when state = WaitTriggerHigh else
|
||||
"0100" when state = Exciting else
|
||||
"0101" when state = WaitTriggerLow else
|
||||
"0110" when state = SamplingDone else
|
||||
"0111" when state = NextPoint else
|
||||
"1000" when state = Done else
|
||||
"1001";
|
||||
DEBUG_STATUS(6) <= PLL_RELOAD_DONE;
|
||||
DEBUG_STATUS(5) <= PLL_RELOAD_DONE and PLL_LOCKED;
|
||||
DEBUG_STATUS(4) <= SAMPLING_BUSY;
|
||||
DEBUG_STATUS(3) <= TRIGGER_IN;
|
||||
DEBUG_STATUS(2) <= source_active;
|
||||
DEBUG_STATUS(1 downto 0) <= (others => '1');
|
||||
|
||||
config_reg <= CONFIG_DATA;
|
||||
|
||||
process(CLK, RESET)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RESET = '1' then
|
||||
point_cnt <= (others => '0');
|
||||
stage_cnt <= (others => '0');
|
||||
state <= WaitInitialLow;
|
||||
START_SAMPLING <= '0';
|
||||
RELOAD_PLL_REGS <= '0';
|
||||
SWEEP_HALTED <= '0';
|
||||
RESULT_INDEX <= (others => '1');
|
||||
PORT1_ACTIVE <= '0';
|
||||
PORT2_ACTIVE <= '0';
|
||||
TRIGGER_OUT <= '0';
|
||||
source_active <= '0';
|
||||
else
|
||||
case state is
|
||||
when WaitInitialLow =>
|
||||
TRIGGER_OUT <= '0';
|
||||
if TRIGGER_IN = '0' or SYNC_ENABLED = '0' then
|
||||
state <= TriggerSetup;
|
||||
end if;
|
||||
when TriggerSetup =>
|
||||
RELOAD_PLL_REGS <= '1';
|
||||
if PLL_RELOAD_DONE = '0' then
|
||||
state <= SettingUp;
|
||||
end if;
|
||||
when SettingUp =>
|
||||
-- highest bit in config_reg determines whether the sweep should be halted prior to sampling
|
||||
SWEEP_HALTED <= config_reg(95);
|
||||
RELOAD_PLL_REGS <= '0';
|
||||
settling_cnt <= unsigned(SETTLING_TIME);
|
||||
if PLL_RELOAD_DONE = '1' and PLL_LOCKED = '1' then
|
||||
-- check if halted sweep is resumed
|
||||
if config_reg(95) = '0' or SWEEP_RESUME = '1' then
|
||||
SWEEP_HALTED <= '0';
|
||||
state <= Settling;
|
||||
end if;
|
||||
end if;
|
||||
when Settling =>
|
||||
NEW_DATA <= '0';
|
||||
source_active <= '0';
|
||||
if std_logic_vector(stage_cnt) = PORT1_STAGE then
|
||||
PORT1_ACTIVE <= '1';
|
||||
source_active <= '1';
|
||||
else
|
||||
PORT1_ACTIVE <= '0';
|
||||
end if;
|
||||
if std_logic_vector(stage_cnt) = PORT2_STAGE then
|
||||
PORT2_ACTIVE <= '1';
|
||||
source_active <= '1';
|
||||
else
|
||||
PORT2_ACTIVE <= '0';
|
||||
end if;
|
||||
-- wait for settling time to elapse
|
||||
if settling_cnt > 0 then
|
||||
settling_cnt <= settling_cnt - 1;
|
||||
else
|
||||
-- need to wait for the trigger
|
||||
state <= WaitTriggerHigh;
|
||||
if SYNC_MASTER = '1' then
|
||||
-- this device generates the stimulus signal, it needs start the trigger itself
|
||||
TRIGGER_OUT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when WaitTriggerHigh =>
|
||||
if TRIGGER_IN = '1' or SYNC_ENABLED = '0' then
|
||||
TRIGGER_OUT <= SYNC_ENABLED; -- pass on trigger signal if enabled
|
||||
START_SAMPLING <= '1';
|
||||
if SAMPLING_BUSY = '1' then
|
||||
state <= Exciting;
|
||||
end if;
|
||||
end if;
|
||||
when Exciting =>
|
||||
-- wait for sampling to finish
|
||||
START_SAMPLING <= '0';
|
||||
if SAMPLING_BUSY = '0' then
|
||||
RESULT_INDEX <= std_logic_vector(stage_cnt) & std_logic_vector(point_cnt);
|
||||
state <= WaitTriggerLow;
|
||||
end if;
|
||||
when WaitTriggerLow =>
|
||||
NEW_DATA <= '0';
|
||||
if SYNC_MASTER = '1' then
|
||||
TRIGGER_OUT <= '0';
|
||||
end if;
|
||||
if TRIGGER_IN = '0' or SYNC_ENABLED = '0' then
|
||||
TRIGGER_OUT <= '0';
|
||||
state <= SamplingDone;
|
||||
end if;
|
||||
when SamplingDone =>
|
||||
NEW_DATA <= '1';
|
||||
if stage_cnt < unsigned(STAGES) then
|
||||
stage_cnt <= stage_cnt + 1;
|
||||
-- can go directly to preperation for next stage
|
||||
state <= Settling;
|
||||
else
|
||||
state <= NextPoint;
|
||||
end if;
|
||||
settling_cnt <= unsigned(SETTLING_TIME);
|
||||
when NextPoint =>
|
||||
NEW_DATA <= '0';
|
||||
if point_cnt < unsigned(NPOINTS) then
|
||||
point_cnt <= point_cnt + 1;
|
||||
stage_cnt <= (others => '0');
|
||||
state <= TriggerSetup;
|
||||
else
|
||||
point_cnt <= (others => '0');
|
||||
state <= Done;
|
||||
TRIGGER_OUT <= '0';
|
||||
end if;
|
||||
when others =>
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,53 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 23:31:10 05/15/2020
|
||||
-- Design Name:
|
||||
-- Module Name: Synchronizer - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Synchronizer is
|
||||
Generic(stages : integer);
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
SYNC_IN : in STD_LOGIC;
|
||||
SYNC_OUT : out STD_LOGIC);
|
||||
end Synchronizer;
|
||||
|
||||
architecture Behavioral of Synchronizer is
|
||||
signal sync_line : std_logic_vector(stages downto 0);
|
||||
begin
|
||||
|
||||
SYNC_OUT <= sync_line(stages);
|
||||
|
||||
process(CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
sync_line <= sync_line(stages-1 downto 0) & SYNC_IN;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,133 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 21:25:23 09/18/2020
|
||||
-- Design Name:
|
||||
-- Module Name: /home/jan/Projekte/VNA2/FPGA/VNA/Test_DFT.vhd
|
||||
-- Project Name: VNA
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: DFT
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY Test_DFT IS
|
||||
END Test_DFT;
|
||||
|
||||
ARCHITECTURE behavior OF Test_DFT IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT DFT
|
||||
GENERIC(BINS : integer);
|
||||
PORT(
|
||||
CLK : IN std_logic;
|
||||
RESET : IN std_logic;
|
||||
PORT1 : IN std_logic_vector(17 downto 0);
|
||||
PORT2 : IN std_logic_vector(17 downto 0);
|
||||
NEW_SAMPLE : IN std_logic;
|
||||
NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
|
||||
BIN1_PHASEINC : IN std_logic_vector(15 downto 0);
|
||||
DIFFBIN_PHASEINC : IN std_logic_vector(15 downto 0);
|
||||
RESULT_READY : OUT std_logic;
|
||||
OUTPUT : out STD_LOGIC_VECTOR (191 downto 0);
|
||||
NEXT_OUTPUT : IN std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal CLK : std_logic := '0';
|
||||
signal RESET : std_logic := '0';
|
||||
signal PORT1 : std_logic_vector(17 downto 0) := (others => '0');
|
||||
signal PORT2 : std_logic_vector(17 downto 0) := (others => '0');
|
||||
signal NEW_SAMPLE : std_logic := '0';
|
||||
signal BIN1_PHASEINC : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal DIFFBIN_PHASEINC : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal NEXT_OUTPUT : std_logic := '0';
|
||||
signal NSAMPLES : STD_LOGIC_VECTOR (12 downto 0);
|
||||
|
||||
--Outputs
|
||||
signal RESULT_READY : std_logic;
|
||||
signal OUTPUT : STD_LOGIC_VECTOR (191 downto 0);
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 10 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: DFT
|
||||
GENERIC MAP(BINS => 64)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
PORT1 => PORT1,
|
||||
PORT2 => PORT2,
|
||||
NEW_SAMPLE => NEW_SAMPLE,
|
||||
NSAMPLES => NSAMPLES,
|
||||
BIN1_PHASEINC => BIN1_PHASEINC,
|
||||
DIFFBIN_PHASEINC => DIFFBIN_PHASEINC,
|
||||
RESULT_READY => RESULT_READY,
|
||||
OUTPUT => OUTPUT,
|
||||
NEXT_OUTPUT => NEXT_OUTPUT
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
RESET <= '1';
|
||||
PORT1 <= "100000000000000000";
|
||||
PORT2 <= "010000000000000000";
|
||||
BIN1_PHASEINC <= "0100000000000000";
|
||||
DIFFBIN_PHASEINC <= "0010000000000000";
|
||||
NSAMPLES <= "0000000000011";
|
||||
wait for 100 ns;
|
||||
RESET <= '0';
|
||||
wait for CLK_period*10;
|
||||
NEW_SAMPLE <= '1';
|
||||
wait for CLK_period;
|
||||
NEW_SAMPLE <= '0';
|
||||
while True loop
|
||||
wait for CLK_period * 79;
|
||||
NEW_SAMPLE <= '1';
|
||||
wait for CLK_period;
|
||||
NEW_SAMPLE <= '0';
|
||||
end loop;
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,127 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 10:46:34 05/07/2020
|
||||
-- Design Name:
|
||||
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_MAX2871.vhd
|
||||
-- Project Name: VNA
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: MAX2871
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY Test_MAX2871 IS
|
||||
END Test_MAX2871;
|
||||
|
||||
ARCHITECTURE behavior OF Test_MAX2871 IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT MAX2871
|
||||
Generic (CLK_DIV : integer);
|
||||
PORT(
|
||||
CLK : IN std_logic;
|
||||
RESET : IN std_logic;
|
||||
REG4 : IN std_logic_vector(31 downto 0);
|
||||
REG3 : IN std_logic_vector(31 downto 0);
|
||||
REG1 : IN std_logic_vector(31 downto 0);
|
||||
REG0 : IN std_logic_vector(31 downto 0);
|
||||
RELOAD : IN std_logic;
|
||||
CLK_OUT : OUT std_logic;
|
||||
MOSI : OUT std_logic;
|
||||
LE : OUT std_logic;
|
||||
DONE : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal CLK : std_logic := '0';
|
||||
signal RESET : std_logic := '0';
|
||||
signal REG4 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal REG3 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal REG1 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal REG0 : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal RELOAD : std_logic := '0';
|
||||
|
||||
--Outputs
|
||||
signal CLK_OUT : std_logic;
|
||||
signal MOSI : std_logic;
|
||||
signal LE : std_logic;
|
||||
signal DONE : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 6.25 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: MAX2871
|
||||
GENERIC MAP(CLK_DIV => 10)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
REG4 => REG4,
|
||||
REG3 => REG3,
|
||||
REG1 => REG1,
|
||||
REG0 => REG0,
|
||||
RELOAD => RELOAD,
|
||||
CLK_OUT => CLK_OUT,
|
||||
MOSI => MOSI,
|
||||
LE => LE,
|
||||
DONE => DONE
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
RESET <= '1';
|
||||
wait for 100 ns;
|
||||
RESET <= '0';
|
||||
wait for CLK_period*10;
|
||||
|
||||
-- insert stimulus here
|
||||
REG4 <= "11111111000000001111111100000000";
|
||||
REG3 <= "11110000111100001111000011110000";
|
||||
REG1 <= "11001100110011001100110011001100";
|
||||
REG0 <= "10101010101010101010101010101010";
|
||||
RELOAD <= '1';
|
||||
wait for CLK_period;
|
||||
RELOAD <= '0';
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
+123
@@ -0,0 +1,123 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 16:27:40 05/05/2020
|
||||
-- Design Name:
|
||||
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_MCP33131.vhd
|
||||
-- Project Name: VNA
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: MCP33131
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY Test_MCP33131 IS
|
||||
END Test_MCP33131;
|
||||
|
||||
ARCHITECTURE behavior OF Test_MCP33131 IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT MCP33131
|
||||
Generic(CLK_DIV : integer;
|
||||
CONVCYCLES : integer);
|
||||
PORT(
|
||||
CLK : IN std_logic;
|
||||
RESET : IN std_logic;
|
||||
START : IN std_logic;
|
||||
READY : OUT std_logic;
|
||||
DATA : OUT std_logic_vector(15 downto 0);
|
||||
MIN : out STD_LOGIC_VECTOR (15 downto 0);
|
||||
MAX : out STD_LOGIC_VECTOR (15 downto 0);
|
||||
RESET_MINMAX : in STD_LOGIC;
|
||||
SDO : IN std_logic;
|
||||
CONVSTART : OUT std_logic;
|
||||
SCLK : INOUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal CLK : std_logic := '0';
|
||||
signal RESET : std_logic := '0';
|
||||
signal START : std_logic := '0';
|
||||
signal SDO : std_logic := '0';
|
||||
signal RESET_MINMAX : STD_LOGIC := '0';
|
||||
|
||||
--Outputs
|
||||
signal READY : std_logic;
|
||||
signal DATA : std_logic_vector(15 downto 0);
|
||||
signal CONVSTART : std_logic;
|
||||
signal SCLK : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 9.765 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: MCP33131
|
||||
GENERIC MAP(CLK_DIV => 2,
|
||||
CONVCYCLES => 77)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
START => START,
|
||||
READY => READY,
|
||||
DATA => DATA,
|
||||
RESET_MINMAX => RESET_MINMAX,
|
||||
SDO => SDO,
|
||||
CONVSTART => CONVSTART,
|
||||
SCLK => SCLK
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
RESET <= '1';
|
||||
wait for CLK_period*10.5;
|
||||
RESET <= '0';
|
||||
wait for CLK_period*10;
|
||||
|
||||
-- insert stimulus here
|
||||
while True loop
|
||||
wait for CLK_period*111;
|
||||
START <= '1';
|
||||
wait for CLK_period;
|
||||
START <= '0';
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,99 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:58:50 05/08/2020
|
||||
-- Design Name:
|
||||
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_PLL.vhd
|
||||
-- Project Name: VNA
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: PLL
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY Test_PLL IS
|
||||
END Test_PLL;
|
||||
|
||||
ARCHITECTURE behavior OF Test_PLL IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT PLL
|
||||
PORT(
|
||||
CLK_IN1 : IN std_logic;
|
||||
CLK_OUT1 : OUT std_logic;
|
||||
RESET : IN std_logic;
|
||||
LOCKED : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal CLK_IN1 : std_logic := '0';
|
||||
signal RESET : std_logic := '0';
|
||||
|
||||
--Outputs
|
||||
signal CLK_OUT1 : std_logic;
|
||||
signal LOCKED : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_IN1_period : time := 20 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: PLL PORT MAP (
|
||||
CLK_IN1 => CLK_IN1,
|
||||
CLK_OUT1 => CLK_OUT1,
|
||||
RESET => RESET,
|
||||
LOCKED => LOCKED
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_IN1_process :process
|
||||
begin
|
||||
CLK_IN1 <= '0';
|
||||
wait for CLK_IN1_period/2;
|
||||
CLK_IN1 <= '1';
|
||||
wait for CLK_IN1_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
RESET <= '1';
|
||||
wait for 100 ns;
|
||||
RESET <= '0';
|
||||
|
||||
wait for CLK_IN1_period*10;
|
||||
|
||||
-- insert stimulus here
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,237 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 15:32:41 05/15/2020
|
||||
-- Design Name:
|
||||
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SPI.vhd
|
||||
-- Project Name: VNA
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: spi_slave
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY Test_SPI IS
|
||||
END Test_SPI;
|
||||
|
||||
ARCHITECTURE behavior OF Test_SPI IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT spi_slave
|
||||
GENERIC(W : integer;
|
||||
PREWIDTH : integer);
|
||||
PORT(
|
||||
SPI_CLK : IN std_logic;
|
||||
MISO : OUT std_logic;
|
||||
MOSI : IN std_logic;
|
||||
CS : IN std_logic;
|
||||
BUF_OUT : OUT std_logic_vector(W-1 downto 0);
|
||||
BUF_IN : IN std_logic_vector(W-1 downto 0);
|
||||
CLK : IN std_logic;
|
||||
COMPLETE : OUT std_logic;
|
||||
PRE_COMPLETE : out STD_LOGIC;
|
||||
PRE_BUF_OUT : out STD_LOGIC_VECTOR (PREWIDTH-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal SPI_CLK : std_logic := '0';
|
||||
signal MOSI : std_logic := '0';
|
||||
signal CS : std_logic := '0';
|
||||
signal BUF_IN : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal CLK : std_logic := '0';
|
||||
|
||||
--Outputs
|
||||
signal MISO : std_logic;
|
||||
signal BUF_OUT : std_logic_vector(15 downto 0);
|
||||
signal COMPLETE : std_logic;
|
||||
signal PRE_COMPLETE : std_logic;
|
||||
signal PRE_BUF_OUT : std_logic_vector(2 downto 0);
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 9.765625 ns;
|
||||
constant SPI_CLK_period : time := 25 ns;
|
||||
|
||||
signal data_signal : std_logic_vector(15 downto 0);
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: spi_slave
|
||||
GENERIC MAP(W => 16, PREWIDTH => 3)
|
||||
PORT MAP (
|
||||
SPI_CLK => SPI_CLK,
|
||||
MISO => MISO,
|
||||
MOSI => MOSI,
|
||||
CS => CS,
|
||||
BUF_OUT => BUF_OUT,
|
||||
BUF_IN => BUF_IN,
|
||||
CLK => CLK,
|
||||
COMPLETE => COMPLETE,
|
||||
PRE_COMPLETE => PRE_COMPLETE,
|
||||
PRE_BUF_OUT => PRE_BUF_OUT
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
procedure SPI(data : std_logic_vector(15 downto 0)) is
|
||||
begin
|
||||
MOSI <= data(15);
|
||||
data_signal <= data(14 downto 0) & "0";
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI_CLK <= '0';
|
||||
end procedure SPI;
|
||||
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
CS <= '1';
|
||||
wait for 100 ns;
|
||||
|
||||
wait for CLK_period*10;
|
||||
BUF_IN <= "1111000010100101";
|
||||
-- insert stimulus here
|
||||
wait for CLK_period*10;
|
||||
CS <= '0';
|
||||
SPI("0101010101010101");
|
||||
CS <= '1';
|
||||
|
||||
wait for CLK_period*10;
|
||||
BUF_IN <= "0000111100001111";
|
||||
wait for CLK_period*10;
|
||||
CS <= '0';
|
||||
SPI("0101010101010101");
|
||||
BUF_IN <= "1010101010101010";
|
||||
wait for SPI_CLK_period/2;
|
||||
SPI("1100110011001100");
|
||||
CS <= '1';
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
+363
@@ -0,0 +1,363 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 18:42:26 05/07/2020
|
||||
-- Design Name:
|
||||
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SPICommands.vhd
|
||||
-- Project Name: VNA
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: SPICommands
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY Test_SPICommands IS
|
||||
END Test_SPICommands;
|
||||
|
||||
ARCHITECTURE behavior OF Test_SPICommands IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT SPICommands
|
||||
PORT(
|
||||
CLK : in STD_LOGIC;
|
||||
RESET : in STD_LOGIC;
|
||||
SCLK : in STD_LOGIC;
|
||||
MOSI : in STD_LOGIC;
|
||||
MISO : out STD_LOGIC;
|
||||
NSS : in STD_LOGIC;
|
||||
NEW_SAMPLING_DATA : in STD_LOGIC;
|
||||
SAMPLING_RESULT : in STD_LOGIC_VECTOR (303 downto 0);
|
||||
ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
|
||||
SOURCE_UNLOCKED : in STD_LOGIC;
|
||||
LO_UNLOCKED : in STD_LOGIC;
|
||||
MAX2871_DEF_4 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
MAX2871_DEF_3 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
MAX2871_DEF_1 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
MAX2871_DEF_0 : out STD_LOGIC_VECTOR (31 downto 0);
|
||||
SWEEP_DATA : out STD_LOGIC_VECTOR (95 downto 0);
|
||||
SWEEP_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
|
||||
SWEEP_WRITE : out STD_LOGIC_VECTOR (0 downto 0);
|
||||
SWEEP_POINTS : out STD_LOGIC_VECTOR (12 downto 0);
|
||||
NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
|
||||
STAGES : out STD_LOGIC_VECTOR (2 downto 0);
|
||||
SETTLING_TIME : out STD_LOGIC_VECTOR (19 downto 0);
|
||||
SYNC_ENABLED : out STD_LOGIC;
|
||||
SYNC_MASTER : out STD_LOGIC;
|
||||
PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
|
||||
PORT2_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
|
||||
PORT1_EN : out STD_LOGIC;
|
||||
PORT2_EN : out STD_LOGIC;
|
||||
REF_EN : out STD_LOGIC;
|
||||
AMP_SHDN : out STD_LOGIC;
|
||||
SOURCE_RF_EN : out STD_LOGIC;
|
||||
LO_RF_EN : out STD_LOGIC;
|
||||
SOURCE_CE_EN : out STD_LOGIC;
|
||||
LO_CE_EN : out STD_LOGIC;
|
||||
PORTSWITCH_EN : out STD_LOGIC;
|
||||
LEDS : out STD_LOGIC_VECTOR(2 downto 0);
|
||||
WINDOW_SETTING : out STD_LOGIC_VECTOR(1 downto 0);
|
||||
ADC_PRESCALER : out STD_LOGIC_VECTOR(7 downto 0);
|
||||
ADC_PHASEINC : out STD_LOGIC_VECTOR(11 downto 0);
|
||||
INTERRUPT_ASSERTED : out STD_LOGIC;
|
||||
RESET_MINMAX : out STD_LOGIC;
|
||||
SWEEP_HALTED : in STD_LOGIC;
|
||||
SWEEP_RESUME : out STD_LOGIC;
|
||||
|
||||
-- hardware overwrite signals
|
||||
SPI_OVERWRITE_ENABLED : out STD_LOGIC;
|
||||
SPI_OVERWRITE_DATA : out STD_LOGIC_VECTOR(14 downto 0);
|
||||
|
||||
-- DFT signals
|
||||
DFT_BIN1_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
|
||||
DFT_DIFFBIN_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
|
||||
DFT_RESULT_READY : in STD_LOGIC;
|
||||
DFT_OUTPUT : in STD_LOGIC_VECTOR (191 downto 0);
|
||||
DFT_NEXT_OUTPUT : out STD_LOGIC;
|
||||
DFT_ENABLE : out STD_LOGIC;
|
||||
|
||||
DEBUG_STATUS : in STD_LOGIC_VECTOR(10 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal CLK : std_logic := '0';
|
||||
signal RESET : std_logic := '0';
|
||||
signal SCLK : std_logic := '0';
|
||||
signal MOSI : std_logic := '0';
|
||||
signal NSS : std_logic := '0';
|
||||
signal NEW_SAMPLING_DATA : std_logic := '0';
|
||||
signal SAMPLING_RESULT : std_logic_vector(303 downto 0) := (others => '0');
|
||||
signal SOURCE_UNLOCKED : std_logic := '1';
|
||||
signal LO_UNLOCKED : std_logic := '1';
|
||||
|
||||
--Outputs
|
||||
signal MISO : std_logic;
|
||||
signal MAX2871_DEF_4 : std_logic_vector(31 downto 0);
|
||||
signal MAX2871_DEF_3 : std_logic_vector(31 downto 0);
|
||||
signal MAX2871_DEF_1 : std_logic_vector(31 downto 0);
|
||||
signal MAX2871_DEF_0 : std_logic_vector(31 downto 0);
|
||||
signal SWEEP_DATA : std_logic_vector(95 downto 0);
|
||||
signal SWEEP_ADDRESS : std_logic_vector(12 downto 0);
|
||||
signal SWEEP_WRITE : std_logic_vector(0 downto 0);
|
||||
signal SWEEP_POINTS : std_logic_vector(12 downto 0);
|
||||
signal NSAMPLES : std_logic_vector(12 downto 0);
|
||||
signal PORT1_EN : std_logic;
|
||||
signal PORT2_EN : std_logic;
|
||||
signal REF_EN : std_logic;
|
||||
signal AMP_SHDN : std_logic;
|
||||
signal SOURCE_RF_EN : std_logic;
|
||||
signal LO_RF_EN : std_logic;
|
||||
signal LEDS : std_logic_vector(2 downto 0);
|
||||
signal INTERRUPT_ASSERTED : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 9.765625 ns;
|
||||
constant SPI_CLK_period : time := 23.52941176 ns;
|
||||
|
||||
signal data_signal : std_logic_vector(15 downto 0);
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: SPICommands PORT MAP (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
SCLK => SCLK,
|
||||
MOSI => MOSI,
|
||||
MISO => MISO,
|
||||
NSS => NSS,
|
||||
NEW_SAMPLING_DATA => NEW_SAMPLING_DATA,
|
||||
SAMPLING_RESULT => SAMPLING_RESULT,
|
||||
ADC_MINMAX => (others => '0'),
|
||||
SOURCE_UNLOCKED => SOURCE_UNLOCKED,
|
||||
LO_UNLOCKED => LO_UNLOCKED,
|
||||
MAX2871_DEF_4 => MAX2871_DEF_4,
|
||||
MAX2871_DEF_3 => MAX2871_DEF_3,
|
||||
MAX2871_DEF_1 => MAX2871_DEF_1,
|
||||
MAX2871_DEF_0 => MAX2871_DEF_0,
|
||||
SWEEP_DATA => SWEEP_DATA,
|
||||
SWEEP_ADDRESS => SWEEP_ADDRESS,
|
||||
SWEEP_WRITE => SWEEP_WRITE,
|
||||
SWEEP_POINTS => SWEEP_POINTS,
|
||||
NSAMPLES => NSAMPLES,
|
||||
PORT1_EN => PORT1_EN,
|
||||
PORT2_EN => PORT2_EN,
|
||||
REF_EN => REF_EN,
|
||||
AMP_SHDN => AMP_SHDN,
|
||||
SOURCE_RF_EN => SOURCE_RF_EN,
|
||||
LO_RF_EN => LO_RF_EN,
|
||||
LEDS => LEDS,
|
||||
INTERRUPT_ASSERTED => INTERRUPT_ASSERTED,
|
||||
SWEEP_HALTED => '0',
|
||||
DFT_RESULT_READY => '0',
|
||||
DFT_OUTPUT => (others => '0'),
|
||||
DEBUG_STATUS => (others => '0')
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
procedure SPI(data : std_logic_vector(15 downto 0)) is
|
||||
begin
|
||||
MOSI <= data(15);
|
||||
data_signal <= data(14 downto 0) & "0";
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
MOSI <= data_signal(15);
|
||||
data_signal <= data_signal(14 downto 0) & '0';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '1';
|
||||
wait for SPI_CLK_period/2;
|
||||
SCLK <= '0';
|
||||
end procedure SPI;
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
RESET <= '1';
|
||||
NSS <= '1';
|
||||
wait for 100 ns;
|
||||
RESET <= '0';
|
||||
wait for CLK_period*10;
|
||||
-- read static test register
|
||||
NSS <= '0';
|
||||
SPI("0100000000000000");
|
||||
SPI("0000000000000000");
|
||||
NSS <= '1';
|
||||
|
||||
wait for CLK_period*50;
|
||||
-- write register 3 = 0xFFFF (enable all periphery)
|
||||
NSS <= '0';
|
||||
SPI("1000000000000011");
|
||||
SPI("1111111111111111");
|
||||
NSS <= '1';
|
||||
|
||||
wait for CLK_period*50;
|
||||
-- set sampling result and read first 4 words
|
||||
SAMPLING_RESULT(63 downto 0) <= "1111000011110000101010101010101001010101010101010000111100001111";
|
||||
NSS <= '0';
|
||||
SPI("1100000000000000");
|
||||
SPI("0000000000000000");
|
||||
SPI("0000000000000000");
|
||||
SPI("0000000000000000");
|
||||
SPI("0000000000000000");
|
||||
NSS <= '1';
|
||||
|
||||
wait for CLK_period*50;
|
||||
-- insert stimulus here
|
||||
-- write number of points
|
||||
NSS <= '0';
|
||||
SPI("1000000000000001");
|
||||
SPI("1111000011110000");
|
||||
NSS <= '1';
|
||||
|
||||
wait for CLK_period*100;
|
||||
-- Write sweep config
|
||||
NSS <= '0';
|
||||
SPI("0000000000001011");
|
||||
SPI("1111111100000000");
|
||||
SPI("1111000011110000");
|
||||
SPI("1100110011001100");
|
||||
SPI("1010101010101010");
|
||||
SPI("1101101101101101");
|
||||
SPI("1110111011101110");
|
||||
SPI("1111101111101111");
|
||||
NSS <= '1';
|
||||
|
||||
wait for CLK_period*50;
|
||||
NEW_SAMPLING_DATA <= '1';
|
||||
wait for CLK_period;
|
||||
NEW_SAMPLING_DATA <= '0';
|
||||
wait for CLK_period*20;
|
||||
NSS <= '0';
|
||||
SPI("1100000000000000");
|
||||
NSS <= '1';
|
||||
|
||||
wait for CLK_period*50;
|
||||
NEW_SAMPLING_DATA <= '1';
|
||||
wait for CLK_period;
|
||||
NEW_SAMPLING_DATA <= '0';
|
||||
wait for CLK_period*20;
|
||||
NSS <= '0';
|
||||
SPI("1100000000000000");
|
||||
NSS <= '1';
|
||||
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
+161
@@ -0,0 +1,161 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 18:40:38 05/05/2020
|
||||
-- Design Name:
|
||||
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_Sampling.vhd
|
||||
-- Project Name: VNA
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: Sampling
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY Test_Sampling IS
|
||||
END Test_Sampling;
|
||||
|
||||
ARCHITECTURE behavior OF Test_Sampling IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT Sampling
|
||||
Generic(CLK_CYCLES_PRE_DONE : integer);
|
||||
PORT(
|
||||
CLK : IN std_logic;
|
||||
RESET : IN std_logic;
|
||||
ADC_PRESCALER : IN std_logic_vector(7 downto 0);
|
||||
PHASEINC : IN std_logic_vector(11 downto 0);
|
||||
PORT1 : IN std_logic_vector(17 downto 0);
|
||||
PORT2 : IN std_logic_vector(17 downto 0);
|
||||
REF : IN std_logic_vector(17 downto 0);
|
||||
NEW_SAMPLE : IN std_logic;
|
||||
START : IN std_logic;
|
||||
SAMPLES : IN std_logic_vector(12 downto 0);
|
||||
ADC_START : OUT std_logic;
|
||||
DONE : OUT std_logic;
|
||||
PRE_DONE : OUT std_logic;
|
||||
PORT1_I : OUT std_logic_vector(47 downto 0);
|
||||
PORT1_Q : OUT std_logic_vector(47 downto 0);
|
||||
PORT2_I : OUT std_logic_vector(47 downto 0);
|
||||
PORT2_Q : OUT std_logic_vector(47 downto 0);
|
||||
REF_I : OUT std_logic_vector(47 downto 0);
|
||||
REF_Q : OUT std_logic_vector(47 downto 0);
|
||||
ACTIVE : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal CLK : std_logic := '0';
|
||||
signal RESET : std_logic := '0';
|
||||
signal PORT1 : std_logic_vector(17 downto 0) := (others => '0');
|
||||
signal PORT2 : std_logic_vector(17 downto 0) := (others => '0');
|
||||
signal REF : std_logic_vector(17 downto 0) := (others => '0');
|
||||
signal NEW_SAMPLE : std_logic := '0';
|
||||
signal START : std_logic := '0';
|
||||
signal SAMPLES : std_logic_vector(12 downto 0) := (others => '0');
|
||||
signal ADC_PRESCALER : std_logic_vector(7 downto 0);
|
||||
signal PHASEINC : std_logic_vector(11 downto 0);
|
||||
--Outputs
|
||||
signal ADC_START : std_logic;
|
||||
signal DONE : std_logic;
|
||||
signal PRE_DONE : std_logic;
|
||||
signal PORT1_I : std_logic_vector(47 downto 0);
|
||||
signal PORT1_Q : std_logic_vector(47 downto 0);
|
||||
signal PORT2_I : std_logic_vector(47 downto 0);
|
||||
signal PORT2_Q : std_logic_vector(47 downto 0);
|
||||
signal REF_I : std_logic_vector(47 downto 0);
|
||||
signal REF_Q : std_logic_vector(47 downto 0);
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 6.25 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: Sampling
|
||||
Generic MAP(CLK_CYCLES_PRE_DONE => 0)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
ADC_PRESCALER => ADC_PRESCALER,
|
||||
PHASEINC => PHASEINC,
|
||||
PORT1 => PORT1,
|
||||
PORT2 => PORT2,
|
||||
REF => REF,
|
||||
NEW_SAMPLE => NEW_SAMPLE,
|
||||
START => START,
|
||||
SAMPLES => SAMPLES,
|
||||
ADC_START => ADC_START,
|
||||
DONE => DONE,
|
||||
PRE_DONE => PRE_DONE,
|
||||
PORT1_I => PORT1_I,
|
||||
PORT1_Q => PORT1_Q,
|
||||
PORT2_I => PORT2_I,
|
||||
PORT2_Q => PORT2_Q,
|
||||
REF_I => REF_I,
|
||||
REF_Q => REF_Q,
|
||||
ACTIVE => open
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
RESET <= '1';
|
||||
wait for 100 ns;
|
||||
RESET <= '0';
|
||||
wait for CLK_period*10;
|
||||
|
||||
-- insert stimulus here
|
||||
ADC_PRESCALER <= "011110000";
|
||||
PHASEINC <= "010001100000";
|
||||
PORT1 <= "000001111111111111";
|
||||
PORT2 <= "000011111111111111";
|
||||
REF <= "000111111111111111";
|
||||
SAMPLES <= "0000000000001";
|
||||
START <= '1';
|
||||
while True loop
|
||||
wait until ADC_START = '1';
|
||||
START <= '0';
|
||||
wait for CLK_period * 110;
|
||||
NEW_SAMPLE <= '1';
|
||||
wait for CLK_period;
|
||||
NEW_SAMPLE <= '0';
|
||||
end loop;
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,104 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09:16:15 05/14/2020
|
||||
-- Design Name:
|
||||
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SinCos.vhd
|
||||
-- Project Name: VNA
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: SinCos
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY Test_SinCos IS
|
||||
END Test_SinCos;
|
||||
|
||||
ARCHITECTURE behavior OF Test_SinCos IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT SinCos
|
||||
PORT(
|
||||
clk : IN std_logic;
|
||||
phase_in : IN std_logic_vector(11 downto 0);
|
||||
cosine : OUT std_logic_vector(15 downto 0);
|
||||
sine : OUT std_logic_vector(15 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal clk : std_logic := '0';
|
||||
signal phase_in : std_logic_vector(11 downto 0) := (others => '0');
|
||||
|
||||
--Outputs
|
||||
signal cosine : std_logic_vector(15 downto 0);
|
||||
signal sine : std_logic_vector(15 downto 0);
|
||||
|
||||
-- Clock period definitions
|
||||
constant clk_period : time := 10 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: SinCos PORT MAP (
|
||||
clk => clk,
|
||||
phase_in => phase_in,
|
||||
cosine => cosine,
|
||||
sine => sine
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
clk_process :process
|
||||
begin
|
||||
clk <= '0';
|
||||
wait for clk_period/2;
|
||||
clk <= '1';
|
||||
wait for clk_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
wait for 100 ns;
|
||||
|
||||
wait for clk_period*10;
|
||||
|
||||
-- insert stimulus here
|
||||
phase_in <= "000000000000";
|
||||
wait for clk_period*10;
|
||||
phase_in <= "000000000001";
|
||||
wait for clk_period*10;
|
||||
phase_in <= "000000000010";
|
||||
wait for clk_period*10;
|
||||
phase_in <= "000000000011";
|
||||
wait for clk_period*10;
|
||||
phase_in <= "000000000100";
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,106 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 13:39:25 09/16/2020
|
||||
-- Design Name:
|
||||
-- Module Name: /home/jan/Projekte/VNA2/FPGA/VNA/Test_Window.vhd
|
||||
-- Project Name: VNA
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: window
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY Test_Window IS
|
||||
END Test_Window;
|
||||
|
||||
ARCHITECTURE behavior OF Test_Window IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT window
|
||||
PORT(
|
||||
CLK : IN std_logic;
|
||||
INDEX : IN std_logic_vector(6 downto 0);
|
||||
WINDOW_TYPE : IN std_logic_vector(1 downto 0);
|
||||
VALUE : OUT std_logic_vector(15 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal CLK : std_logic := '0';
|
||||
signal INDEX : std_logic_vector(6 downto 0) := (others => '0');
|
||||
signal WINDOW_TYPE : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
--Outputs
|
||||
signal VALUE : std_logic_vector(15 downto 0);
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 10 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: window PORT MAP (
|
||||
CLK => CLK,
|
||||
INDEX => INDEX,
|
||||
WINDOW_TYPE => WINDOW_TYPE,
|
||||
VALUE => VALUE
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
wait for 100 ns;
|
||||
WINDOW_TYPE <= "00";
|
||||
INDEX <= "0000000";
|
||||
wait for CLK_period*10;
|
||||
|
||||
WINDOW_TYPE <= "10";
|
||||
-- insert stimulus here
|
||||
wait for CLK_period*10;
|
||||
INDEX <= "0000001";
|
||||
wait for CLK_period*10;
|
||||
INDEX <= "0000010";
|
||||
wait for CLK_period*10;
|
||||
INDEX <= "0000011";
|
||||
wait for CLK_period*10;
|
||||
INDEX <= "0000100";
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
+135
@@ -0,0 +1,135 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 18:37:51 11/06/2020
|
||||
-- Design Name:
|
||||
-- Module Name: /home/jan/Projekte/VNA2/FPGA/VNA/Test_Windowing.vhd
|
||||
-- Project Name: VNA
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: Windowing
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY Test_Windowing IS
|
||||
END Test_Windowing;
|
||||
|
||||
ARCHITECTURE behavior OF Test_Windowing IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT Windowing
|
||||
PORT(
|
||||
CLK : IN std_logic;
|
||||
RESET : IN std_logic;
|
||||
WINDOW_TYPE : IN std_logic_vector(1 downto 0);
|
||||
PORT1_RAW : IN std_logic_vector(15 downto 0);
|
||||
PORT2_RAW : IN std_logic_vector(15 downto 0);
|
||||
REF_RAW : IN std_logic_vector(15 downto 0);
|
||||
ADC_READY : IN std_logic;
|
||||
PORT1_WINDOWED : OUT std_logic_vector(17 downto 0);
|
||||
PORT2_WINDOWED : OUT std_logic_vector(17 downto 0);
|
||||
REF_WINDOWED : OUT std_logic_vector(17 downto 0);
|
||||
WINDOWING_DONE : OUT std_logic;
|
||||
NSAMPLES : IN std_logic_vector(12 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal CLK : std_logic := '0';
|
||||
signal RESET : std_logic := '0';
|
||||
signal WINDOW_TYPE : std_logic_vector(1 downto 0) := (others => '0');
|
||||
signal PORT1_RAW : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal PORT2_RAW : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal REF_RAW : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal ADC_READY : std_logic := '0';
|
||||
signal NSAMPLES : std_logic_vector(12 downto 0) := (others => '0');
|
||||
|
||||
--Outputs
|
||||
signal PORT1_WINDOWED : std_logic_vector(17 downto 0);
|
||||
signal PORT2_WINDOWED : std_logic_vector(17 downto 0);
|
||||
signal REF_WINDOWED : std_logic_vector(17 downto 0);
|
||||
signal WINDOWING_DONE : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 10 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: Windowing PORT MAP (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
WINDOW_TYPE => WINDOW_TYPE,
|
||||
PORT1_RAW => PORT1_RAW,
|
||||
PORT2_RAW => PORT2_RAW,
|
||||
REF_RAW => REF_RAW,
|
||||
ADC_READY => ADC_READY,
|
||||
PORT1_WINDOWED => PORT1_WINDOWED,
|
||||
PORT2_WINDOWED => PORT2_WINDOWED,
|
||||
REF_WINDOWED => REF_WINDOWED,
|
||||
WINDOWING_DONE => WINDOWING_DONE,
|
||||
NSAMPLES => NSAMPLES
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
wait for 100 ns;
|
||||
|
||||
wait for CLK_period*10;
|
||||
|
||||
-- insert stimulus here
|
||||
WINDOW_TYPE <= "10";
|
||||
NSAMPLES <= "0000000010001";
|
||||
PORT1_RAW <= "0000000010000000";
|
||||
PORT2_RAW <= "0000000100000000";
|
||||
REF_RAW <= "0000001000000000";
|
||||
ADC_READY <= '0';
|
||||
RESET <= '1';
|
||||
wait for CLK_period;
|
||||
RESET <= '0';
|
||||
for i in 0 to 271 loop
|
||||
wait for CLK_period*111;
|
||||
ADC_READY <= '1';
|
||||
wait for CLK_period;
|
||||
ADC_READY <= '0';
|
||||
end loop;
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,413 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="VNA.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="DFT.vhi"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="MAX2871.vhi"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="MCP33131.vhi"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="ResetDelay.vhi"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="SPICommands.vhi"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="SPICommands_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Sampling.cmd_log"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Sampling.lso"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Sampling.prj"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="Sampling.syr"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Sampling.vhi"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="Sampling.xst"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Sampling_envsettings.html"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Sampling_summary.html"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Sampling_xst.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Sweep.vhi"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Synchronizer.vhi"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_DFT_isim_beh.exe"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX2871_isim_beh.exe"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_SPICommands_beh.prj"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_SPICommands_isim_beh.wdb"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Sync_beh.prj"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sync_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_Sync_isim_beh.wdb"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Window_isim_beh.exe"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Windowing_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Windowing_stx_beh.prj"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_top_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Windowing.vhi"/>
|
||||
<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impactbatch.log"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="dft_result.vhi"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
|
||||
<file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_4"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="spi_slave.vhi"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:fileType="FILE_BIN" xil_pn:name="top.bin"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="top.bit" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="top.bld"/>
|
||||
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="top.cmd_log"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="top.drc" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="top.lso"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top.ncd" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="top.ngc"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="top.ngd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="top.ngr"/>
|
||||
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="top.pad"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="top.par" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="top.pcf" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="top.prj"/>
|
||||
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="top.ptwx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="top.stx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="top.syr"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="top.twr" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="top.twx" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="top.unroutes" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="top.ut" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:fileType="FILE_XPI" xil_pn:name="top.xpi"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="top.xst"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="top_envsettings.html"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="top_fpga_editor.log"/>
|
||||
<file xil_pn:fileType="FILE_NCD" xil_pn:name="top_guide.ncd" xil_pn:origination="imported"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="top_isim_beh.exe"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_map.map" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_map.mrp" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top_map.ncd" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="top_map.ngm" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_map.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_ngdbuild.xrpt"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="top_pad.csv" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="top_pad.txt" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_par.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="top_summary.html"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="top_summary.xml"/>
|
||||
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="top_usage.xml"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_xst.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="window.vhi"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="window_beh.prj"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="window_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="window_isim_beh.wdb"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1588688858" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1588688858">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735897915" xil_pn:in_ck="-3235419683908193302" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1735897915">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="DFT.vhd"/>
|
||||
<outfile xil_pn:name="MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="MCP33131.vhd"/>
|
||||
<outfile xil_pn:name="ResetDelay.vhd"/>
|
||||
<outfile xil_pn:name="SPIConfig.vhd"/>
|
||||
<outfile xil_pn:name="Sampling.vhd"/>
|
||||
<outfile xil_pn:name="Sweep.vhd"/>
|
||||
<outfile xil_pn:name="Synchronizer.vhd"/>
|
||||
<outfile xil_pn:name="Test_DFT.vhd"/>
|
||||
<outfile xil_pn:name="Test_MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="Test_MCP33131.vhd"/>
|
||||
<outfile xil_pn:name="Test_PLL.vhd"/>
|
||||
<outfile xil_pn:name="Test_SPI.vhd"/>
|
||||
<outfile xil_pn:name="Test_SPICommands.vhd"/>
|
||||
<outfile xil_pn:name="Test_Sampling.vhd"/>
|
||||
<outfile xil_pn:name="Test_SinCos.vhd"/>
|
||||
<outfile xil_pn:name="Test_Window.vhd"/>
|
||||
<outfile xil_pn:name="Test_Windowing.vhd"/>
|
||||
<outfile xil_pn:name="Windowing.vhd"/>
|
||||
<outfile xil_pn:name="spi_slave.vhd"/>
|
||||
<outfile xil_pn:name="top.vhd"/>
|
||||
<outfile xil_pn:name="window.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735898132" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="9011583378592605907" xil_pn:start_ts="1735898132">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735898132" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="2919554697640690001" xil_pn:start_ts="1735898132">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735887598" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1735887598">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735897915" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1735897915">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="DFT.vhd"/>
|
||||
<outfile xil_pn:name="MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="MCP33131.vhd"/>
|
||||
<outfile xil_pn:name="ResetDelay.vhd"/>
|
||||
<outfile xil_pn:name="SPIConfig.vhd"/>
|
||||
<outfile xil_pn:name="Sampling.vhd"/>
|
||||
<outfile xil_pn:name="Sweep.vhd"/>
|
||||
<outfile xil_pn:name="Synchronizer.vhd"/>
|
||||
<outfile xil_pn:name="Test_DFT.vhd"/>
|
||||
<outfile xil_pn:name="Test_MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="Test_MCP33131.vhd"/>
|
||||
<outfile xil_pn:name="Test_PLL.vhd"/>
|
||||
<outfile xil_pn:name="Test_SPI.vhd"/>
|
||||
<outfile xil_pn:name="Test_SPICommands.vhd"/>
|
||||
<outfile xil_pn:name="Test_Sampling.vhd"/>
|
||||
<outfile xil_pn:name="Test_SinCos.vhd"/>
|
||||
<outfile xil_pn:name="Test_Window.vhd"/>
|
||||
<outfile xil_pn:name="Test_Windowing.vhd"/>
|
||||
<outfile xil_pn:name="Windowing.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
|
||||
<outfile xil_pn:name="spi_slave.vhd"/>
|
||||
<outfile xil_pn:name="top.vhd"/>
|
||||
<outfile xil_pn:name="window.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735898134" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8439971377188504826" xil_pn:start_ts="1735898132">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="Test_SPICommands_beh.prj"/>
|
||||
<outfile xil_pn:name="Test_SPICommands_isim_beh.exe"/>
|
||||
<outfile xil_pn:name="fuse.log"/>
|
||||
<outfile xil_pn:name="isim"/>
|
||||
<outfile xil_pn:name="isim.log"/>
|
||||
<outfile xil_pn:name="xilinxsim.ini"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735898134" xil_pn:in_ck="4191604156099045257" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6574364550222252173" xil_pn:start_ts="1735898134">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="Test_SPICommands_isim_beh.wdb"/>
|
||||
<outfile xil_pn:name="isim.cmd"/>
|
||||
<outfile xil_pn:name="isim.log"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735835257" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1735835257">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735835257" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6623951845608321876" xil_pn:start_ts="1735835257">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1736097035" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1736097035">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735835257" xil_pn:in_ck="-2664127494180108140" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1735835257">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735835257" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9042377951913232490" xil_pn:start_ts="1735835257">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735835257" xil_pn:in_ck="-2664127494180108140" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1735835257">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1735835257" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="6527189854873920525" xil_pn:start_ts="1735835257">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1736097046" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1736097035">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="top.lso"/>
|
||||
<outfile xil_pn:name="top.ngc"/>
|
||||
<outfile xil_pn:name="top.ngr"/>
|
||||
<outfile xil_pn:name="top.prj"/>
|
||||
<outfile xil_pn:name="top.stx"/>
|
||||
<outfile xil_pn:name="top.syr"/>
|
||||
<outfile xil_pn:name="top.xst"/>
|
||||
<outfile xil_pn:name="top_xst.xrpt"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1736097046" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1736097046">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1736097050" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1736097046">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<outfile xil_pn:name="top.bld"/>
|
||||
<outfile xil_pn:name="top.ngd"/>
|
||||
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1736097131" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1736097050">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<outfile xil_pn:name="top.pcf"/>
|
||||
<outfile xil_pn:name="top_map.map"/>
|
||||
<outfile xil_pn:name="top_map.mrp"/>
|
||||
<outfile xil_pn:name="top_map.ncd"/>
|
||||
<outfile xil_pn:name="top_map.ngm"/>
|
||||
<outfile xil_pn:name="top_map.xrpt"/>
|
||||
<outfile xil_pn:name="top_summary.xml"/>
|
||||
<outfile xil_pn:name="top_usage.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1736097154" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1736097131">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<outfile xil_pn:name="top.ncd"/>
|
||||
<outfile xil_pn:name="top.pad"/>
|
||||
<outfile xil_pn:name="top.par"/>
|
||||
<outfile xil_pn:name="top.ptwx"/>
|
||||
<outfile xil_pn:name="top.unroutes"/>
|
||||
<outfile xil_pn:name="top.xpi"/>
|
||||
<outfile xil_pn:name="top_pad.csv"/>
|
||||
<outfile xil_pn:name="top_pad.txt"/>
|
||||
<outfile xil_pn:name="top_par.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1736097164" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1736097154">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<outfile xil_pn:name="top.bgn"/>
|
||||
<outfile xil_pn:name="top.bin"/>
|
||||
<outfile xil_pn:name="top.bit"/>
|
||||
<outfile xil_pn:name="top.drc"/>
|
||||
<outfile xil_pn:name="top.ut"/>
|
||||
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
|
||||
<outfile xil_pn:name="webtalk.log"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1591357065" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="-2382555676865099342" xil_pn:start_ts="1591357065">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1591357024" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="-8856759851099153863" xil_pn:start_ts="1591357024">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1591357058" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="7381105705363676227" xil_pn:start_ts="1591357058">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604431776" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1604431776">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1736097154" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1736097149">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<outfile xil_pn:name="top.twr"/>
|
||||
<outfile xil_pn:name="top.twx"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
@@ -0,0 +1,513 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="BuildConfig.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
|
||||
</file>
|
||||
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
|
||||
</file>
|
||||
<file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="MCP33131.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_MCP33131.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="MAX2871.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SweepConfigMem.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
|
||||
</file>
|
||||
<file xil_pn:name="Sampling.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SinCos.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_Sampling.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="49"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="49"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="49"/>
|
||||
</file>
|
||||
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
|
||||
</file>
|
||||
<file xil_pn:name="Sweep.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_MAX2871.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="77"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="77"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="77"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_SPICommands.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="115"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="115"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="115"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_PLL.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="124"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="124"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="124"/>
|
||||
</file>
|
||||
<file xil_pn:name="ResetDelay.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_SinCos.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="20"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="20"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="20"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_SPI.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="133"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="133"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="133"/>
|
||||
</file>
|
||||
<file xil_pn:name="Synchronizer.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="window.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_Window.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="139"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="139"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="139"/>
|
||||
</file>
|
||||
<file xil_pn:name="DFT.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_DFT.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="144"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="144"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="144"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/result_bram.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/DSP_SLICE.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="Windowing.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_Windowing.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="176"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="176"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="176"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SweepConfigMem.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SinCos.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PLL.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/result_bram.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/DSP_SLICE.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|Behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="top.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="top" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="top_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="top" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_SPICommands" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_SPICommands" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_SPICommands" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target UCF File Name" xil_pn:value="top.ucf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="For Packing Only" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="iMPACT Project File" xil_pn:value="auto_project.ipf" xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_SPICommands|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-05-05T15:40:10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6048ACB2C5F0FA1D2E943FFD4590C880" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/top" xil_pn:name="top.ucf"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
+513
@@ -0,0 +1,513 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="BuildConfig_external_lo_slave.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
|
||||
</file>
|
||||
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
|
||||
</file>
|
||||
<file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="MCP33131.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_MCP33131.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="MAX2871.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SweepConfigMem.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
|
||||
</file>
|
||||
<file xil_pn:name="Sampling.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SinCos.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_Sampling.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="49"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="49"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="49"/>
|
||||
</file>
|
||||
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
|
||||
</file>
|
||||
<file xil_pn:name="Sweep.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_MAX2871.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="77"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="77"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="77"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_SPICommands.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="115"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="115"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="115"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_PLL.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="124"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="124"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="124"/>
|
||||
</file>
|
||||
<file xil_pn:name="ResetDelay.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_SinCos.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="20"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="20"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="20"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_SPI.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="133"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="133"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="133"/>
|
||||
</file>
|
||||
<file xil_pn:name="Synchronizer.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="window.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_Window.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="139"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="139"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="139"/>
|
||||
</file>
|
||||
<file xil_pn:name="DFT.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_DFT.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="144"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="144"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="144"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/result_bram.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/DSP_SLICE.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="Windowing.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_Windowing.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="176"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="176"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="176"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SweepConfigMem.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SinCos.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PLL.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/result_bram.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/DSP_SLICE.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|Behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="top.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="top" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="top_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="top" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_SPICommands" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_SPICommands" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_SPICommands" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target UCF File Name" xil_pn:value="top.ucf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="For Packing Only" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="iMPACT Project File" xil_pn:value="auto_project.ipf" xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_SPICommands|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-05-05T15:40:10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6048ACB2C5F0FA1D2E943FFD4590C880" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/top" xil_pn:name="top.ucf"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@@ -0,0 +1,201 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 18:18:17 11/06/2020
|
||||
-- Design Name:
|
||||
-- Module Name: Windowing - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Windowing is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
RESET : in STD_LOGIC;
|
||||
WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
|
||||
PORT1_RAW : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
PORT2_RAW : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
REF_RAW : in STD_LOGIC_VECTOR (15 downto 0);
|
||||
ADC_READY : in STD_LOGIC;
|
||||
PORT1_WINDOWED : out STD_LOGIC_VECTOR (17 downto 0);
|
||||
PORT2_WINDOWED : out STD_LOGIC_VECTOR (17 downto 0);
|
||||
REF_WINDOWED : out STD_LOGIC_VECTOR (17 downto 0);
|
||||
WINDOWING_DONE : out STD_LOGIC;
|
||||
NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0));
|
||||
end Windowing;
|
||||
|
||||
architecture Behavioral of Windowing is
|
||||
COMPONENT window
|
||||
PORT(
|
||||
CLK : IN std_logic;
|
||||
INDEX : IN std_logic_vector(6 downto 0);
|
||||
WINDOW_TYPE : IN std_logic_vector(1 downto 0);
|
||||
VALUE : OUT std_logic_vector(15 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT DSP_SLICE
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
ce : IN STD_LOGIC;
|
||||
sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||
p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
signal window_index : std_logic_vector(6 downto 0);
|
||||
signal window_value : std_logic_vector(15 downto 0);
|
||||
signal window_sample_cnt : integer range -8 to 8191;
|
||||
signal window_index_inc : integer range 0 to 8;
|
||||
signal window_sample_compare : integer range 0 to 8191;
|
||||
signal window_sample_cnt_inc : integer range 0 to 8;
|
||||
|
||||
signal mult_a : std_logic_vector(17 downto 0);
|
||||
signal mult_b : std_logic_vector(17 downto 0);
|
||||
signal mult_p : std_logic_vector(47 downto 0);
|
||||
signal mult_enable : std_logic;
|
||||
|
||||
type states is (CalcWindowInc, WaitingForADC, CalcPort1, CalcPort2, CalcRef, MultDelay1, MultDelay2, StorePort1, StorePort2, StoreRef);
|
||||
signal state : states;
|
||||
begin
|
||||
|
||||
Mult : DSP_SLICE
|
||||
PORT MAP (
|
||||
clk => CLK,
|
||||
ce => mult_enable,
|
||||
sel => "0",
|
||||
a => mult_a,
|
||||
b => mult_b,
|
||||
c => (others => '0'),
|
||||
p => mult_p
|
||||
);
|
||||
WindowROM: window PORT MAP(
|
||||
CLK => CLK,
|
||||
INDEX => window_index,
|
||||
WINDOW_TYPE => WINDOW_TYPE,
|
||||
VALUE => window_value
|
||||
);
|
||||
-- sign extend multiplier inputs
|
||||
mult_a(17 downto 16) <= mult_a(15) & mult_a(15);
|
||||
mult_b(17 downto 16) <= mult_b(15) & mult_b(15);
|
||||
|
||||
mult_a(15 downto 0) <= window_value;
|
||||
|
||||
process(CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RESET = '1' then
|
||||
WINDOWING_DONE <= '0';
|
||||
state <= CalcWindowInc;
|
||||
mult_enable <= '0';
|
||||
mult_b(15 downto 0) <= (others => '0');
|
||||
window_index <= (others => '0');
|
||||
window_sample_cnt <= 0;
|
||||
window_sample_compare <= to_integer(unsigned(NSAMPLES));
|
||||
else
|
||||
case state is
|
||||
when CalcWindowInc =>
|
||||
case window_sample_compare is
|
||||
when 1 =>
|
||||
-- 16 samples, increment on every sample by 8
|
||||
window_sample_cnt_inc <= 1;
|
||||
window_index_inc <= 8;
|
||||
when 2 to 3 =>
|
||||
-- 32-48 samples, increment by 4
|
||||
window_sample_cnt_inc <= 2;
|
||||
window_index_inc <= 4;
|
||||
when 4 to 7 =>
|
||||
-- 64-112 samples, increment by 2
|
||||
window_sample_cnt_inc <= 4;
|
||||
window_index_inc <= 2;
|
||||
when others =>
|
||||
-- 128 or more samples, increment by 1
|
||||
window_sample_cnt_inc <= 8;
|
||||
window_index_inc <= 1;
|
||||
end case;
|
||||
state <= WaitingForADC;
|
||||
when WaitingForADC =>
|
||||
WINDOWING_DONE <= '0';
|
||||
mult_enable <= '0';
|
||||
mult_b(15 downto 0) <= (others => '0');
|
||||
if ADC_READY = '1' then
|
||||
state <= CalcPort1;
|
||||
end if;
|
||||
when CalcPort1 =>
|
||||
WINDOWING_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
mult_b(15 downto 0) <= PORT1_RAW;
|
||||
state <= CalcPort2;
|
||||
when CalcPort2 =>
|
||||
WINDOWING_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
mult_b(15 downto 0) <= PORT2_RAW;
|
||||
state <= CalcRef;
|
||||
when CalcRef =>
|
||||
WINDOWING_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
mult_b(15 downto 0) <= REF_RAW;
|
||||
state <= MultDelay1;
|
||||
when MultDelay1 =>
|
||||
WINDOWING_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
mult_b(15 downto 0) <= (others => '0');
|
||||
state <= MultDelay2;
|
||||
when MultDelay2 =>
|
||||
WINDOWING_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
mult_b(15 downto 0) <= (others => '0');
|
||||
state <= StorePort1;
|
||||
when StorePort1 =>
|
||||
WINDOWING_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
mult_b(15 downto 0) <= (others => '0');
|
||||
PORT1_WINDOWED <= mult_p(30 downto 13);
|
||||
state <= StorePort2;
|
||||
when StorePort2 =>
|
||||
WINDOWING_DONE <= '0';
|
||||
mult_enable <= '1';
|
||||
mult_b(15 downto 0) <= (others => '0');
|
||||
PORT2_WINDOWED <= mult_p(30 downto 13);
|
||||
state <= StoreRef;
|
||||
when StoreRef =>
|
||||
WINDOWING_DONE <= '1';
|
||||
mult_enable <= '0';
|
||||
mult_b(15 downto 0) <= (others => '0');
|
||||
REF_WINDOWED <= mult_p(30 downto 13);
|
||||
-- update window increment
|
||||
if window_sample_cnt + window_sample_cnt_inc < window_sample_compare then
|
||||
window_sample_cnt <= window_sample_cnt + window_sample_cnt_inc;
|
||||
else
|
||||
window_sample_cnt <= window_sample_cnt + window_sample_cnt_inc - window_sample_compare;
|
||||
window_index <= std_logic_vector( unsigned(window_index) + window_index_inc );
|
||||
end if;
|
||||
state <= WaitingForADC;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
*
|
||||
*/*
|
||||
!.gitignore
|
||||
!*.xco
|
||||
!*.xise
|
||||
|
||||
+136
@@ -0,0 +1,136 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.6
|
||||
# Date: Fri Nov 6 13:56:17 2020
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:xbip_dsp48_macro:2.1
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc6slx9
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = tqg144
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT DSP48_Macro xilinx.com:ip:xbip_dsp48_macro:2.1
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET a_binarywidth=0
|
||||
CSET a_width=18
|
||||
CSET areg_1=false
|
||||
CSET areg_2=false
|
||||
CSET areg_3=true
|
||||
CSET areg_4=true
|
||||
CSET b_binarywidth=0
|
||||
CSET b_width=18
|
||||
CSET breg_1=false
|
||||
CSET breg_2=false
|
||||
CSET breg_3=true
|
||||
CSET breg_4=true
|
||||
CSET c_binarywidth=0
|
||||
CSET c_width=48
|
||||
CSET cinreg_1=false
|
||||
CSET cinreg_2=false
|
||||
CSET cinreg_3=false
|
||||
CSET cinreg_4=false
|
||||
CSET cinreg_5=false
|
||||
CSET component_name=DSP48
|
||||
CSET concat_binarywidth=0
|
||||
CSET concat_width=48
|
||||
CSET concatreg_3=false
|
||||
CSET concatreg_4=false
|
||||
CSET concatreg_5=false
|
||||
CSET creg_1=false
|
||||
CSET creg_2=false
|
||||
CSET creg_3=true
|
||||
CSET creg_4=true
|
||||
CSET creg_5=true
|
||||
CSET d_binarywidth=0
|
||||
CSET d_width=18
|
||||
CSET dreg_1=false
|
||||
CSET dreg_2=false
|
||||
CSET dreg_3=false
|
||||
CSET gui_behaviour=Coregen
|
||||
CSET has_a_ce=false
|
||||
CSET has_a_sclr=false
|
||||
CSET has_acout=false
|
||||
CSET has_b_ce=false
|
||||
CSET has_b_sclr=false
|
||||
CSET has_bcout=false
|
||||
CSET has_c_ce=false
|
||||
CSET has_c_sclr=false
|
||||
CSET has_carrycascout=false
|
||||
CSET has_carryout=false
|
||||
CSET has_ce=true
|
||||
CSET has_concat_ce=false
|
||||
CSET has_concat_sclr=false
|
||||
CSET has_d_ce=false
|
||||
CSET has_d_sclr=false
|
||||
CSET has_m_ce=false
|
||||
CSET has_m_sclr=false
|
||||
CSET has_p_ce=false
|
||||
CSET has_p_sclr=false
|
||||
CSET has_pcout=false
|
||||
CSET has_sclr=false
|
||||
CSET has_sel_ce=false
|
||||
CSET has_sel_sclr=false
|
||||
CSET instruction1=A*B
|
||||
CSET instruction2=A*B+C
|
||||
CSET instruction3=#
|
||||
CSET instruction4=#
|
||||
CSET instruction5=#
|
||||
CSET instruction6=#
|
||||
CSET instruction7=#
|
||||
CSET instruction8=#
|
||||
CSET instruction_list=#
|
||||
CSET mreg_5=true
|
||||
CSET opreg_1=false
|
||||
CSET opreg_2=false
|
||||
CSET opreg_3=true
|
||||
CSET opreg_4=true
|
||||
CSET opreg_5=true
|
||||
CSET output_properties=Full_Precision
|
||||
CSET p_binarywidth=0
|
||||
CSET p_full_width=48
|
||||
CSET p_width=48
|
||||
CSET pcin_binarywidth=0
|
||||
CSET pipeline_options=Automatic
|
||||
CSET preg_6=true
|
||||
CSET show_filtered=false
|
||||
CSET tier_1=false
|
||||
CSET tier_2=false
|
||||
CSET tier_3=false
|
||||
CSET tier_4=false
|
||||
CSET tier_5=false
|
||||
CSET tier_6=false
|
||||
CSET use_dsp48=true
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-11-05T14:23:53Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 2ca4f824
|
||||
+73
@@ -0,0 +1,73 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="DSP48.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="DSP48.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|DSP48|DSP48_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="DSP48.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/DSP48" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="DSP48" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-11-06T14:56:38" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="134E6A8E8B8A97C235E2A00FC956CC90" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
+136
@@ -0,0 +1,136 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.6
|
||||
# Date: Fri Nov 6 13:57:46 2020
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:xbip_dsp48_macro:2.1
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc6slx9
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = tqg144
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT DSP48_Macro xilinx.com:ip:xbip_dsp48_macro:2.1
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET a_binarywidth=0
|
||||
CSET a_width=18
|
||||
CSET areg_1=false
|
||||
CSET areg_2=false
|
||||
CSET areg_3=true
|
||||
CSET areg_4=true
|
||||
CSET b_binarywidth=0
|
||||
CSET b_width=18
|
||||
CSET breg_1=false
|
||||
CSET breg_2=false
|
||||
CSET breg_3=true
|
||||
CSET breg_4=true
|
||||
CSET c_binarywidth=0
|
||||
CSET c_width=48
|
||||
CSET cinreg_1=false
|
||||
CSET cinreg_2=false
|
||||
CSET cinreg_3=false
|
||||
CSET cinreg_4=false
|
||||
CSET cinreg_5=false
|
||||
CSET component_name=DSP_SLICE
|
||||
CSET concat_binarywidth=0
|
||||
CSET concat_width=48
|
||||
CSET concatreg_3=false
|
||||
CSET concatreg_4=false
|
||||
CSET concatreg_5=false
|
||||
CSET creg_1=false
|
||||
CSET creg_2=false
|
||||
CSET creg_3=true
|
||||
CSET creg_4=true
|
||||
CSET creg_5=true
|
||||
CSET d_binarywidth=0
|
||||
CSET d_width=18
|
||||
CSET dreg_1=false
|
||||
CSET dreg_2=false
|
||||
CSET dreg_3=false
|
||||
CSET gui_behaviour=Coregen
|
||||
CSET has_a_ce=false
|
||||
CSET has_a_sclr=false
|
||||
CSET has_acout=false
|
||||
CSET has_b_ce=false
|
||||
CSET has_b_sclr=false
|
||||
CSET has_bcout=false
|
||||
CSET has_c_ce=false
|
||||
CSET has_c_sclr=false
|
||||
CSET has_carrycascout=false
|
||||
CSET has_carryout=false
|
||||
CSET has_ce=true
|
||||
CSET has_concat_ce=false
|
||||
CSET has_concat_sclr=false
|
||||
CSET has_d_ce=false
|
||||
CSET has_d_sclr=false
|
||||
CSET has_m_ce=false
|
||||
CSET has_m_sclr=false
|
||||
CSET has_p_ce=false
|
||||
CSET has_p_sclr=false
|
||||
CSET has_pcout=false
|
||||
CSET has_sclr=false
|
||||
CSET has_sel_ce=false
|
||||
CSET has_sel_sclr=false
|
||||
CSET instruction1=A*B
|
||||
CSET instruction2=A*B+C
|
||||
CSET instruction3=#
|
||||
CSET instruction4=#
|
||||
CSET instruction5=#
|
||||
CSET instruction6=#
|
||||
CSET instruction7=#
|
||||
CSET instruction8=#
|
||||
CSET instruction_list=#
|
||||
CSET mreg_5=true
|
||||
CSET opreg_1=false
|
||||
CSET opreg_2=false
|
||||
CSET opreg_3=true
|
||||
CSET opreg_4=true
|
||||
CSET opreg_5=true
|
||||
CSET output_properties=Full_Precision
|
||||
CSET p_binarywidth=0
|
||||
CSET p_full_width=48
|
||||
CSET p_width=48
|
||||
CSET pcin_binarywidth=0
|
||||
CSET pipeline_options=Automatic
|
||||
CSET preg_6=true
|
||||
CSET show_filtered=false
|
||||
CSET tier_1=false
|
||||
CSET tier_2=false
|
||||
CSET tier_3=false
|
||||
CSET tier_4=false
|
||||
CSET tier_5=false
|
||||
CSET tier_6=false
|
||||
CSET use_dsp48=true
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-11-05T14:23:53Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 57648294
|
||||
+73
@@ -0,0 +1,73 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="DSP_SLICE.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="DSP_SLICE.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|DSP_SLICE|DSP_SLICE_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="DSP_SLICE.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/DSP_SLICE" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="DSP_SLICE" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-11-06T14:58:06" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E54C6A9B0DFD393EEACC284C7E05AF9E" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
+269
@@ -0,0 +1,269 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.6
|
||||
# Date: Thu May 14 06:56:00 2020
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:clk_wiz:3.6
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc6slx9
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = tqg144
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET calc_done=DONE
|
||||
CSET clk_in_sel_port=CLK_IN_SEL
|
||||
CSET clk_out1_port=CLK_OUT1
|
||||
CSET clk_out1_use_fine_ps_gui=false
|
||||
CSET clk_out2_port=CLK_OUT2
|
||||
CSET clk_out2_use_fine_ps_gui=false
|
||||
CSET clk_out3_port=CLK_OUT3
|
||||
CSET clk_out3_use_fine_ps_gui=false
|
||||
CSET clk_out4_port=CLK_OUT4
|
||||
CSET clk_out4_use_fine_ps_gui=false
|
||||
CSET clk_out5_port=CLK_OUT5
|
||||
CSET clk_out5_use_fine_ps_gui=false
|
||||
CSET clk_out6_port=CLK_OUT6
|
||||
CSET clk_out6_use_fine_ps_gui=false
|
||||
CSET clk_out7_port=CLK_OUT7
|
||||
CSET clk_out7_use_fine_ps_gui=false
|
||||
CSET clk_valid_port=CLK_VALID
|
||||
CSET clkfb_in_n_port=CLKFB_IN_N
|
||||
CSET clkfb_in_p_port=CLKFB_IN_P
|
||||
CSET clkfb_in_port=CLKFB_IN
|
||||
CSET clkfb_in_signaling=SINGLE
|
||||
CSET clkfb_out_n_port=CLKFB_OUT_N
|
||||
CSET clkfb_out_p_port=CLKFB_OUT_P
|
||||
CSET clkfb_out_port=CLKFB_OUT
|
||||
CSET clkfb_stopped_port=CLKFB_STOPPED
|
||||
CSET clkin1_jitter_ps=625.0
|
||||
CSET clkin1_ui_jitter=0.010
|
||||
CSET clkin2_jitter_ps=100.0
|
||||
CSET clkin2_ui_jitter=0.010
|
||||
CSET clkout1_drives=BUFG
|
||||
CSET clkout1_requested_duty_cycle=50.000
|
||||
CSET clkout1_requested_out_freq=102.4
|
||||
CSET clkout1_requested_phase=0.000
|
||||
CSET clkout2_drives=BUFG
|
||||
CSET clkout2_requested_duty_cycle=50.000
|
||||
CSET clkout2_requested_out_freq=100.000
|
||||
CSET clkout2_requested_phase=0.000
|
||||
CSET clkout2_used=false
|
||||
CSET clkout3_drives=BUFG
|
||||
CSET clkout3_requested_duty_cycle=50.000
|
||||
CSET clkout3_requested_out_freq=100.000
|
||||
CSET clkout3_requested_phase=0.000
|
||||
CSET clkout3_used=false
|
||||
CSET clkout4_drives=BUFG
|
||||
CSET clkout4_requested_duty_cycle=50.000
|
||||
CSET clkout4_requested_out_freq=100.000
|
||||
CSET clkout4_requested_phase=0.000
|
||||
CSET clkout4_used=false
|
||||
CSET clkout5_drives=BUFG
|
||||
CSET clkout5_requested_duty_cycle=50.000
|
||||
CSET clkout5_requested_out_freq=100.000
|
||||
CSET clkout5_requested_phase=0.000
|
||||
CSET clkout5_used=false
|
||||
CSET clkout6_drives=BUFG
|
||||
CSET clkout6_requested_duty_cycle=50.000
|
||||
CSET clkout6_requested_out_freq=100.000
|
||||
CSET clkout6_requested_phase=0.000
|
||||
CSET clkout6_used=false
|
||||
CSET clkout7_drives=BUFG
|
||||
CSET clkout7_requested_duty_cycle=50.000
|
||||
CSET clkout7_requested_out_freq=100.000
|
||||
CSET clkout7_requested_phase=0.000
|
||||
CSET clkout7_used=false
|
||||
CSET clock_mgr_type=AUTO
|
||||
CSET component_name=PLL
|
||||
CSET daddr_port=DADDR
|
||||
CSET dclk_port=DCLK
|
||||
CSET dcm_clk_feedback=1X
|
||||
CSET dcm_clk_out1_port=CLKFX
|
||||
CSET dcm_clk_out2_port=CLK0
|
||||
CSET dcm_clk_out3_port=CLK0
|
||||
CSET dcm_clk_out4_port=CLK0
|
||||
CSET dcm_clk_out5_port=CLK0
|
||||
CSET dcm_clk_out6_port=CLK0
|
||||
CSET dcm_clkdv_divide=2.0
|
||||
CSET dcm_clkfx_divide=5
|
||||
CSET dcm_clkfx_multiply=32
|
||||
CSET dcm_clkgen_clk_out1_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out2_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out3_port=CLKFX
|
||||
CSET dcm_clkgen_clkfx_divide=1
|
||||
CSET dcm_clkgen_clkfx_md_max=0.000
|
||||
CSET dcm_clkgen_clkfx_multiply=4
|
||||
CSET dcm_clkgen_clkfxdv_divide=2
|
||||
CSET dcm_clkgen_clkin_period=10.000
|
||||
CSET dcm_clkgen_notes=None
|
||||
CSET dcm_clkgen_spread_spectrum=NONE
|
||||
CSET dcm_clkgen_startup_wait=false
|
||||
CSET dcm_clkin_divide_by_2=false
|
||||
CSET dcm_clkin_period=62.500
|
||||
CSET dcm_clkout_phase_shift=NONE
|
||||
CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
|
||||
CSET dcm_notes=None
|
||||
CSET dcm_phase_shift=0
|
||||
CSET dcm_pll_cascade=NONE
|
||||
CSET dcm_startup_wait=false
|
||||
CSET den_port=DEN
|
||||
CSET din_port=DIN
|
||||
CSET dout_port=DOUT
|
||||
CSET drdy_port=DRDY
|
||||
CSET dwe_port=DWE
|
||||
CSET feedback_source=FDBK_AUTO
|
||||
CSET in_freq_units=Units_MHz
|
||||
CSET in_jitter_units=Units_UI
|
||||
CSET input_clk_stopped_port=INPUT_CLK_STOPPED
|
||||
CSET jitter_options=UI
|
||||
CSET jitter_sel=No_Jitter
|
||||
CSET locked_port=LOCKED
|
||||
CSET mmcm_bandwidth=OPTIMIZED
|
||||
CSET mmcm_clkfbout_mult_f=4.000
|
||||
CSET mmcm_clkfbout_phase=0.000
|
||||
CSET mmcm_clkfbout_use_fine_ps=false
|
||||
CSET mmcm_clkin1_period=10.000
|
||||
CSET mmcm_clkin2_period=10.000
|
||||
CSET mmcm_clkout0_divide_f=4.000
|
||||
CSET mmcm_clkout0_duty_cycle=0.500
|
||||
CSET mmcm_clkout0_phase=0.000
|
||||
CSET mmcm_clkout0_use_fine_ps=false
|
||||
CSET mmcm_clkout1_divide=1
|
||||
CSET mmcm_clkout1_duty_cycle=0.500
|
||||
CSET mmcm_clkout1_phase=0.000
|
||||
CSET mmcm_clkout1_use_fine_ps=false
|
||||
CSET mmcm_clkout2_divide=1
|
||||
CSET mmcm_clkout2_duty_cycle=0.500
|
||||
CSET mmcm_clkout2_phase=0.000
|
||||
CSET mmcm_clkout2_use_fine_ps=false
|
||||
CSET mmcm_clkout3_divide=1
|
||||
CSET mmcm_clkout3_duty_cycle=0.500
|
||||
CSET mmcm_clkout3_phase=0.000
|
||||
CSET mmcm_clkout3_use_fine_ps=false
|
||||
CSET mmcm_clkout4_cascade=false
|
||||
CSET mmcm_clkout4_divide=1
|
||||
CSET mmcm_clkout4_duty_cycle=0.500
|
||||
CSET mmcm_clkout4_phase=0.000
|
||||
CSET mmcm_clkout4_use_fine_ps=false
|
||||
CSET mmcm_clkout5_divide=1
|
||||
CSET mmcm_clkout5_duty_cycle=0.500
|
||||
CSET mmcm_clkout5_phase=0.000
|
||||
CSET mmcm_clkout5_use_fine_ps=false
|
||||
CSET mmcm_clkout6_divide=1
|
||||
CSET mmcm_clkout6_duty_cycle=0.500
|
||||
CSET mmcm_clkout6_phase=0.000
|
||||
CSET mmcm_clkout6_use_fine_ps=false
|
||||
CSET mmcm_clock_hold=false
|
||||
CSET mmcm_compensation=ZHOLD
|
||||
CSET mmcm_divclk_divide=1
|
||||
CSET mmcm_notes=None
|
||||
CSET mmcm_ref_jitter1=0.010
|
||||
CSET mmcm_ref_jitter2=0.010
|
||||
CSET mmcm_startup_wait=false
|
||||
CSET num_out_clks=1
|
||||
CSET override_dcm=false
|
||||
CSET override_dcm_clkgen=false
|
||||
CSET override_mmcm=false
|
||||
CSET override_pll=false
|
||||
CSET platform=lin64
|
||||
CSET pll_bandwidth=OPTIMIZED
|
||||
CSET pll_clk_feedback=CLKFBOUT
|
||||
CSET pll_clkfbout_mult=16
|
||||
CSET pll_clkfbout_phase=0.000
|
||||
CSET pll_clkin_period=31.250
|
||||
CSET pll_clkout0_divide=5
|
||||
CSET pll_clkout0_duty_cycle=0.500
|
||||
CSET pll_clkout0_phase=0.000
|
||||
CSET pll_clkout1_divide=1
|
||||
CSET pll_clkout1_duty_cycle=0.500
|
||||
CSET pll_clkout1_phase=0.000
|
||||
CSET pll_clkout2_divide=1
|
||||
CSET pll_clkout2_duty_cycle=0.500
|
||||
CSET pll_clkout2_phase=0.000
|
||||
CSET pll_clkout3_divide=1
|
||||
CSET pll_clkout3_duty_cycle=0.500
|
||||
CSET pll_clkout3_phase=0.000
|
||||
CSET pll_clkout4_divide=1
|
||||
CSET pll_clkout4_duty_cycle=0.500
|
||||
CSET pll_clkout4_phase=0.000
|
||||
CSET pll_clkout5_divide=1
|
||||
CSET pll_clkout5_duty_cycle=0.500
|
||||
CSET pll_clkout5_phase=0.000
|
||||
CSET pll_compensation=SYSTEM_SYNCHRONOUS
|
||||
CSET pll_divclk_divide=1
|
||||
CSET pll_notes=None
|
||||
CSET pll_ref_jitter=0.010
|
||||
CSET power_down_port=POWER_DOWN
|
||||
CSET prim_in_freq=16
|
||||
CSET prim_in_jitter=0.010
|
||||
CSET prim_source=Single_ended_clock_capable_pin
|
||||
CSET primary_port=CLK_IN1
|
||||
CSET primitive=MMCM
|
||||
CSET primtype_sel=PLL_BASE
|
||||
CSET psclk_port=PSCLK
|
||||
CSET psdone_port=PSDONE
|
||||
CSET psen_port=PSEN
|
||||
CSET psincdec_port=PSINCDEC
|
||||
CSET relative_inclk=REL_PRIMARY
|
||||
CSET reset_port=RESET
|
||||
CSET secondary_in_freq=100.000
|
||||
CSET secondary_in_jitter=0.010
|
||||
CSET secondary_port=CLK_IN2
|
||||
CSET secondary_source=Single_ended_clock_capable_pin
|
||||
CSET ss_mod_freq=250
|
||||
CSET ss_mode=CENTER_HIGH
|
||||
CSET status_port=STATUS
|
||||
CSET summary_strings=empty
|
||||
CSET use_clk_valid=false
|
||||
CSET use_clkfb_stopped=false
|
||||
CSET use_dyn_phase_shift=false
|
||||
CSET use_dyn_reconfig=false
|
||||
CSET use_freeze=false
|
||||
CSET use_freq_synth=true
|
||||
CSET use_inclk_stopped=false
|
||||
CSET use_inclk_switchover=false
|
||||
CSET use_locked=true
|
||||
CSET use_max_i_jitter=false
|
||||
CSET use_min_o_jitter=false
|
||||
CSET use_min_power=false
|
||||
CSET use_phase_alignment=true
|
||||
CSET use_power_down=false
|
||||
CSET use_reset=true
|
||||
CSET use_spread_spectrum=false
|
||||
CSET use_spread_spectrum_1=false
|
||||
CSET use_status=false
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-05-10T12:44:55Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 2c6bfa8c
|
||||
+74
@@ -0,0 +1,74 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="PLL.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="PLL.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|PLL|xilinx" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="PLL.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/PLL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="PLL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-05-14T08:56:17" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2C473EAB241BB5DC7E5AB6450BAFACB9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/PLL" xil_pn:name="PLL.ucf"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
+142
@@ -0,0 +1,142 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.6
|
||||
# Date: Tue May 5 15:36:58 2020
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:dds_compiler:4.0
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc6slx9
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = tqg144
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT DDS_Compiler xilinx.com:ip:dds_compiler:4.0
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET amplitude_mode=Full_Range
|
||||
CSET channel_pin=false
|
||||
CSET channels=1
|
||||
CSET clock_enable=false
|
||||
CSET component_name=SinCos
|
||||
CSET dds_clock_rate=100
|
||||
CSET dsp48_use=Minimal
|
||||
CSET explicit_period=false
|
||||
CSET frequency_resolution=0.4
|
||||
CSET gui_behaviour=Coregen
|
||||
CSET has_phase_out=false
|
||||
CSET latency=6
|
||||
CSET latency_configuration=Auto
|
||||
CSET memory_type=Auto
|
||||
CSET negative_cosine=false
|
||||
CSET negative_sine=false
|
||||
CSET noise_shaping=None
|
||||
CSET optimization_goal=Auto
|
||||
CSET output_frequency1=0
|
||||
CSET output_frequency10=0
|
||||
CSET output_frequency11=0
|
||||
CSET output_frequency12=0
|
||||
CSET output_frequency13=0
|
||||
CSET output_frequency14=0
|
||||
CSET output_frequency15=0
|
||||
CSET output_frequency16=0
|
||||
CSET output_frequency2=0
|
||||
CSET output_frequency3=0
|
||||
CSET output_frequency4=0
|
||||
CSET output_frequency5=0
|
||||
CSET output_frequency6=0
|
||||
CSET output_frequency7=0
|
||||
CSET output_frequency8=0
|
||||
CSET output_frequency9=0
|
||||
CSET output_selection=Sine_and_Cosine
|
||||
CSET output_width=16
|
||||
CSET parameter_entry=Hardware_Parameters
|
||||
CSET partspresent=SIN_COS_LUT_only
|
||||
CSET period=1
|
||||
CSET phase_increment=Fixed
|
||||
CSET phase_offset=None
|
||||
CSET phase_offset_angles1=0
|
||||
CSET phase_offset_angles10=0
|
||||
CSET phase_offset_angles11=0
|
||||
CSET phase_offset_angles12=0
|
||||
CSET phase_offset_angles13=0
|
||||
CSET phase_offset_angles14=0
|
||||
CSET phase_offset_angles15=0
|
||||
CSET phase_offset_angles16=0
|
||||
CSET phase_offset_angles2=0
|
||||
CSET phase_offset_angles3=0
|
||||
CSET phase_offset_angles4=0
|
||||
CSET phase_offset_angles5=0
|
||||
CSET phase_offset_angles6=0
|
||||
CSET phase_offset_angles7=0
|
||||
CSET phase_offset_angles8=0
|
||||
CSET phase_offset_angles9=0
|
||||
CSET phase_width=12
|
||||
CSET pinc1=0
|
||||
CSET pinc10=0
|
||||
CSET pinc11=0
|
||||
CSET pinc12=0
|
||||
CSET pinc13=0
|
||||
CSET pinc14=0
|
||||
CSET pinc15=0
|
||||
CSET pinc16=0
|
||||
CSET pinc2=0
|
||||
CSET pinc3=0
|
||||
CSET pinc4=0
|
||||
CSET pinc5=0
|
||||
CSET pinc6=0
|
||||
CSET pinc7=0
|
||||
CSET pinc8=0
|
||||
CSET pinc9=0
|
||||
CSET poff1=0
|
||||
CSET poff10=0
|
||||
CSET poff11=0
|
||||
CSET poff12=0
|
||||
CSET poff13=0
|
||||
CSET poff14=0
|
||||
CSET poff15=0
|
||||
CSET poff16=0
|
||||
CSET poff2=0
|
||||
CSET poff3=0
|
||||
CSET poff4=0
|
||||
CSET poff5=0
|
||||
CSET poff6=0
|
||||
CSET poff7=0
|
||||
CSET poff8=0
|
||||
CSET poff9=0
|
||||
CSET por_mode=false
|
||||
CSET rdy=false
|
||||
CSET rfd=false
|
||||
CSET sclr_pin=false
|
||||
CSET spurious_free_dynamic_range=36
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-08-28T14:48:35Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: dc69a097
|
||||
+73
@@ -0,0 +1,73 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="SinCos.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="SinCos.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|SinCos|SinCos_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="SinCos.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/SinCos" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="SinCos" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-05-05T17:37:39" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="204D41E577D960FB03F2E48F18ECFBB4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
+108
@@ -0,0 +1,108 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.6
|
||||
# Date: Mon Sep 14 08:50:12 2020
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc6slx9
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = tqg144
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET additional_inputs_for_power_estimation=false
|
||||
CSET algorithm=Minimum_Area
|
||||
CSET assume_synchronous_clk=false
|
||||
CSET axi_id_width=4
|
||||
CSET axi_slave_type=Memory_Slave
|
||||
CSET axi_type=AXI4_Full
|
||||
CSET byte_size=9
|
||||
CSET coe_file=no_coe_file_loaded
|
||||
CSET collision_warnings=ALL
|
||||
CSET component_name=SweepConfigMem
|
||||
CSET disable_collision_warnings=false
|
||||
CSET disable_out_of_range_warnings=false
|
||||
CSET ecc=false
|
||||
CSET ecctype=No_ECC
|
||||
CSET enable_32bit_address=false
|
||||
CSET enable_a=Use_ENA_Pin
|
||||
CSET enable_b=Always_Enabled
|
||||
CSET error_injection_type=Single_Bit_Error_Injection
|
||||
CSET fill_remaining_memory_locations=false
|
||||
CSET interface_type=Native
|
||||
CSET load_init_file=false
|
||||
CSET mem_file=no_Mem_file_loaded
|
||||
CSET memory_type=Simple_Dual_Port_RAM
|
||||
CSET operating_mode_a=WRITE_FIRST
|
||||
CSET operating_mode_b=WRITE_FIRST
|
||||
CSET output_reset_value_a=0
|
||||
CSET output_reset_value_b=0
|
||||
CSET pipeline_stages=0
|
||||
CSET port_a_clock=100
|
||||
CSET port_a_enable_rate=100
|
||||
CSET port_a_write_rate=50
|
||||
CSET port_b_clock=100
|
||||
CSET port_b_enable_rate=100
|
||||
CSET port_b_write_rate=0
|
||||
CSET primitive=8kx2
|
||||
CSET read_width_a=96
|
||||
CSET read_width_b=96
|
||||
CSET register_porta_input_of_softecc=false
|
||||
CSET register_porta_output_of_memory_core=false
|
||||
CSET register_porta_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_memory_core=false
|
||||
CSET register_portb_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_softecc=false
|
||||
CSET remaining_memory_locations=0
|
||||
CSET reset_memory_latch_a=false
|
||||
CSET reset_memory_latch_b=false
|
||||
CSET reset_priority_a=CE
|
||||
CSET reset_priority_b=CE
|
||||
CSET reset_type=SYNC
|
||||
CSET softecc=false
|
||||
CSET use_axi_id=false
|
||||
CSET use_bram_block=Stand_Alone
|
||||
CSET use_byte_write_enable=false
|
||||
CSET use_error_injection_pins=false
|
||||
CSET use_regcea_pin=false
|
||||
CSET use_regceb_pin=false
|
||||
CSET use_rsta_pin=false
|
||||
CSET use_rstb_pin=false
|
||||
CSET write_depth_a=4501
|
||||
CSET write_width_a=96
|
||||
CSET write_width_b=96
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-11-19T16:22:25Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: e7b4a756
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user