diff --git a/.gitignore b/.gitignore
index 4eec6a8..d93038f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -239,4 +239,12 @@ device_firmware/cart_firmware/captures/
device_firmware/cart_firmware/.vscode/c_cpp_properties.json
device_firmware/cart_firmware/.vscode/launch.json
device_firmware/cart_firmware/.vscode/ipch/
-device_firmware/cart_firmware/.vscode/.browse.c_cpp.db*
\ No newline at end of file
+device_firmware/cart_firmware/.vscode/.browse.c_cpp.db*
+# --- device_firmware: комплект воспроизведения прошивок LibreVNA ---
+# Корневые `build*` / `build/` иначе молча выбрасывают сам build.sh и эталонные
+# прошивки STM32, на которые ссылается reproduce/SHA256SUMS. Каталог сборки
+# приходится разыгнорить целиком: git не умеет возвращать файл, у которого
+# исключён родительский каталог.
+!device_firmware/multi_libreVNA_firmware/reproduce/build.sh
+!device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/VNA_embedded/build/
+!device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/VNA_embedded/build_external_lo_slave/
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/.gitignore b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/.gitignore
new file mode 100644
index 0000000..dd882c6
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/.gitignore
@@ -0,0 +1,15 @@
+*.s#*
+*.b#*
+*.log
+*.net
+*.op.raw
+*.raw
+*.vnafw
+*.aux
+*.log
+*.synctex.gz
+*.xcf
+*.out
+*.toc
+*.pyc
+Hardware/Renderings
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/AssembleFirmware.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/AssembleFirmware.py
new file mode 100755
index 0000000..ee35885
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/AssembleFirmware.py
@@ -0,0 +1,118 @@
+#!/usr/bin/env python3
+
+import argparse
+import binascii
+from pathlib import Path
+
+
+DEFAULT_FPGA_BITSTREAM = "FPGA/VNA/top.bin"
+DEFAULT_OUTPUT = "combined.vnafw"
+DEFAULT_MCU_CANDIDATES = [
+ "Software/VNA_embedded/Debug/VNA_embedded.bin",
+ "Software/VNA_embedded/Release/VNA_embedded.bin",
+ "Software/VNA_embedded/build/VNA_embedded.bin",
+]
+
+HEADER_SIZE = 24
+
+
+def parse_args() -> argparse.Namespace:
+ parser = argparse.ArgumentParser(
+ description="Assemble a combined LibreVNA firmware image.",
+ )
+ parser.add_argument(
+ "--bitstream",
+ default=DEFAULT_FPGA_BITSTREAM,
+ help=f"FPGA bitstream to package (default: {DEFAULT_FPGA_BITSTREAM})",
+ )
+ parser.add_argument(
+ "--output",
+ default=DEFAULT_OUTPUT,
+ help=f"Output firmware image path (default: {DEFAULT_OUTPUT})",
+ )
+ parser.add_argument(
+ "--mcu",
+ help="Explicit MCU firmware .bin path. If omitted, the newest known build is used.",
+ )
+ return parser.parse_args()
+
+
+def select_mcu_firmware(explicit_path: str | None) -> Path:
+ if explicit_path is not None:
+ path = Path(explicit_path)
+ if not path.is_file():
+ raise FileNotFoundError(f"MCU firmware not found: {path}")
+ return path
+
+ latest_modification = 0.0
+ newest_mcu: Path | None = None
+ for candidate in DEFAULT_MCU_CANDIDATES:
+ path = Path(candidate)
+ if not path.is_file():
+ continue
+ modified_time = path.stat().st_mtime
+ if modified_time >= latest_modification:
+ latest_modification = modified_time
+ newest_mcu = path
+
+ if newest_mcu is None:
+ raise FileNotFoundError("Couldn't find MCU firmware file")
+ return newest_mcu
+
+
+def crc32_from_file(filename: Path, initial_crc: int) -> int:
+ buffer = filename.read_bytes()
+ return binascii.crc32(buffer, initial_crc) & 0xFFFFFFFF
+
+
+def main() -> int:
+ args = parse_args()
+
+ bitstream_path = Path(args.bitstream)
+ if not bitstream_path.is_file():
+ raise FileNotFoundError(f"FPGA bitstream not found: {bitstream_path}")
+
+ mcu_firmware_path = select_mcu_firmware(args.mcu)
+ output_path = Path(args.output)
+
+ print(f"Using {mcu_firmware_path} as MCU firmware")
+
+ size_fpga = bitstream_path.stat().st_size
+ size_mcu = mcu_firmware_path.stat().st_size
+ print(f"Got FPGA bitstream of size {size_fpga}")
+ print(f"Got MCU firmware of size {size_mcu}")
+
+ crc = crc32_from_file(bitstream_path, 0xFFFFFFFF)
+ crc = crc32_from_file(mcu_firmware_path, crc)
+ print(f"Calculating CRC...:{hex(crc)}")
+
+ output_path.parent.mkdir(parents=True, exist_ok=True)
+ with output_path.open("wb") as firmware_image:
+ firmware_image.write(b"VNA!")
+ firmware_image.write((HEADER_SIZE).to_bytes(4, byteorder="little"))
+ firmware_image.write(size_fpga.to_bytes(4, byteorder="little"))
+ firmware_image.write((HEADER_SIZE + size_fpga).to_bytes(4, byteorder="little"))
+ firmware_image.write(size_mcu.to_bytes(4, byteorder="little"))
+ firmware_image.write(crc.to_bytes(4, byteorder="little"))
+
+ if firmware_image.tell() != HEADER_SIZE:
+ raise RuntimeError(
+ "Incorrect header size "
+ f"(defined as {HEADER_SIZE} but actual header is {firmware_image.tell()})"
+ )
+
+ firmware_image.write(bitstream_path.read_bytes())
+ firmware_image.write(mcu_firmware_path.read_bytes())
+
+ if firmware_image.tell() % 256 != 0:
+ padding = 256 - firmware_image.tell() % 256
+ firmware_image.write(bytearray(padding))
+
+ final_size = firmware_image.tell()
+
+ print(f"Created combined firmware file at {output_path} with size {final_size}")
+ return 0
+
+
+if __name__ == "__main__":
+ raise SystemExit(main())
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/EmbeddedFirmware-hw-rev-B-v1.6.5-2026-04-08-18-04-39/VNA_embedded.elf b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/EmbeddedFirmware-hw-rev-B-v1.6.5-2026-04-08-18-04-39/VNA_embedded.elf
new file mode 100644
index 0000000..9e3ee43
Binary files /dev/null and b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/EmbeddedFirmware-hw-rev-B-v1.6.5-2026-04-08-18-04-39/VNA_embedded.elf differ
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/EmbeddedFirmware-hw-rev-B-v1.6.5-2026-04-08-18-04-39/combined.vnafw b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/EmbeddedFirmware-hw-rev-B-v1.6.5-2026-04-08-18-04-39/combined.vnafw
new file mode 100644
index 0000000..942500d
Binary files /dev/null and b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/EmbeddedFirmware-hw-rev-B-v1.6.5-2026-04-08-18-04-39/combined.vnafw differ
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/.gitignore b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/.gitignore
new file mode 100644
index 0000000..b9cf525
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/.gitignore
@@ -0,0 +1,12 @@
+*
+!.gitignore
+!*/
+!*.vhd
+!*.ucf
+!*.ipf
+!*.gise
+!*.xise
+!*.py
+!*.bin
+!VNA/*.dat
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/AMAttenuationCalculator.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/AMAttenuationCalculator.py
new file mode 100755
index 0000000..b97047e
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/AMAttenuationCalculator.py
@@ -0,0 +1,45 @@
+#!/usr/bin/env python3
+
+import math
+
+# Adapt these constants to the step attenuator
+BITS_OF_ATTENUATION = 7
+LSB_ATTENUATOR_DB = 0.25
+NUMBER_LINEAR_ATTENUATION_STEPS = 128
+
+file = open("AMdepth.dat", "w")
+
+def bindigits(n, bits):
+ s = bin(n & int("1"*bits, 2))[2:]
+ return ("{0:0>%s}" % (bits)).format(s)
+
+for i in range(NUMBER_LINEAR_ATTENUATION_STEPS):
+ # calculate percentage of attenuation
+ percent = float(i) / (NUMBER_LINEAR_ATTENUATION_STEPS - 1)
+ # calculate attenuation in dB
+ if percent < 1:
+ required_dB = -20*math.log10(1 - percent)
+ else:
+ required_dB = 999
+ # round to attenuator steps
+ attenuator_dB = round(required_dB / LSB_ATTENUATOR_DB) * LSB_ATTENUATOR_DB
+ # convert to digital attenuator value
+ attenuator_step = int(attenuator_dB / LSB_ATTENUATOR_DB)
+ # constrain
+ if attenuator_step < 0:
+ attenuator_step = 0
+ elif attenuator_step >= pow(2, BITS_OF_ATTENUATION):
+ attenuator_step = pow(2, BITS_OF_ATTENUATION) - 1
+ output = bindigits(attenuator_step, BITS_OF_ATTENUATION)
+ file.write(output+"\n")
+
+ # Calculate actual attenuation
+ actual_dB = attenuator_step * LSB_ATTENUATOR_DB
+ actual_percent = 1 - pow(10, -actual_dB/20)
+
+ percent_desired = round(percent*100, 2)
+ percent_actual = round(actual_percent*100, 2)
+
+ print(f'Target modulation: {percent_desired:.2f}, target dB: {required_dB:.2f}, attenuator setting: {attenuator_step}, achieved dB: {actual_dB}, achieved modulation: {percent_actual:.2f}')
+
+file.close()
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/AMMult.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/AMMult.gise
new file mode 100644
index 0000000..f5c03b0
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/AMMult.gise
@@ -0,0 +1,53 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/AMMult.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/AMMult.vhd
new file mode 100644
index 0000000..4354992
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/AMMult.vhd
@@ -0,0 +1,102 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2022 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file AMMult.vhd when simulating
+-- the core, AMMult. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY AMMult IS
+ PORT (
+ clk : IN STD_LOGIC;
+ a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+ ce : IN STD_LOGIC;
+ p : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
+ );
+END AMMult;
+
+ARCHITECTURE AMMult_a OF AMMult IS
+-- synthesis translate_off
+COMPONENT wrapped_AMMult
+ PORT (
+ clk : IN STD_LOGIC;
+ a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+ ce : IN STD_LOGIC;
+ p : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_AMMult USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
+ GENERIC MAP (
+ c_a_type => 1,
+ c_a_width => 8,
+ c_b_type => 1,
+ c_b_value => "10000001",
+ c_b_width => 7,
+ c_ccm_imp => 0,
+ c_ce_overrides_sclr => 0,
+ c_has_ce => 1,
+ c_has_sclr => 0,
+ c_has_zero_detect => 0,
+ c_latency => 1,
+ c_model_type => 0,
+ c_mult_type => 1,
+ c_optimize_goal => 1,
+ c_out_high => 14,
+ c_out_low => 0,
+ c_round_output => 0,
+ c_round_pt => 0,
+ c_verbosity => 0,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_AMMult
+ PORT MAP (
+ clk => clk,
+ a => a,
+ b => b,
+ ce => ce,
+ p => p
+ );
+-- synthesis translate_on
+
+END AMMult_a;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK.gise
new file mode 100644
index 0000000..6042a80
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK.gise
@@ -0,0 +1,31 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK.ucf b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK.ucf
new file mode 100644
index 0000000..f3c5cec
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK.ucf
@@ -0,0 +1,59 @@
+# file: DFT_CLK.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps;
+
+
+# FALSE PATH constraints
+PIN "RESET" TIG;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK.vhd
new file mode 100644
index 0000000..0f40de0
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK.vhd
@@ -0,0 +1,169 @@
+-- file: DFT_CLK.vhd
+--
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output Output Phase Duty Pk-to-Pk Phase"
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1___160.000______0.000______50.0______336.927____150.000
+--
+------------------------------------------------------------------------------
+-- "Input Clock Freq (MHz) Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary______________16____________0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity DFT_CLK is
+port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Clock out ports
+ CLK_OUT1 : out std_logic;
+ -- Status and control signals
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end DFT_CLK;
+
+architecture xilinx of DFT_CLK is
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of xilinx : architecture is "DFT_CLK,clk_wiz_v3_6,{component_name=DFT_CLK,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=62.5,clkin2_period=62.5,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
+ -- Input clock buffering / unused connectors
+ signal clkin1 : std_logic;
+ -- Output clock buffering
+ signal clkfb : std_logic;
+ signal clk0 : std_logic;
+ signal clkfx : std_logic;
+ signal clkfbout : std_logic;
+ signal locked_internal : std_logic;
+ signal status_internal : std_logic_vector(7 downto 0);
+begin
+
+
+ -- Input buffering
+ --------------------------------------
+ clkin1 <= CLK_IN1;
+
+
+ -- Clocking primitive
+ --------------------------------------
+
+ -- Instantiation of the DCM primitive
+ -- * Unused inputs are tied off
+ -- * Unused outputs are labeled unused
+ dcm_sp_inst: DCM_SP
+ generic map
+ (CLKDV_DIVIDE => 2.000,
+ CLKFX_DIVIDE => 1,
+ CLKFX_MULTIPLY => 10,
+ CLKIN_DIVIDE_BY_2 => FALSE,
+ CLKIN_PERIOD => 62.5,
+ CLKOUT_PHASE_SHIFT => "NONE",
+ CLK_FEEDBACK => "1X",
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+ PHASE_SHIFT => 0,
+ STARTUP_WAIT => FALSE)
+ port map
+ -- Input clock
+ (CLKIN => clkin1,
+ CLKFB => clkfb,
+ -- Output clocks
+ CLK0 => clk0,
+ CLK90 => open,
+ CLK180 => open,
+ CLK270 => open,
+ CLK2X => open,
+ CLK2X180 => open,
+ CLKFX => clkfx,
+ CLKFX180 => open,
+ CLKDV => open,
+ -- Ports for dynamic phase shift
+ PSCLK => '0',
+ PSEN => '0',
+ PSINCDEC => '0',
+ PSDONE => open,
+ -- Other control and status signals
+ LOCKED => locked_internal,
+ STATUS => status_internal,
+ RST => RESET,
+ -- Unused pin, tie low
+ DSSEN => '0');
+
+ LOCKED <= locked_internal;
+
+
+
+ -- Output buffering
+ -------------------------------------
+ clkf_buf : BUFG
+ port map
+ (O => clkfb,
+ I => clk0);
+
+
+ clkout1_buf : BUFG
+ port map
+ (O => CLK_OUT1,
+ I => clkfx);
+
+
+
+end xilinx;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK/example_design/DFT_CLK_exdes.ucf b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK/example_design/DFT_CLK_exdes.ucf
new file mode 100644
index 0000000..bacff37
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK/example_design/DFT_CLK_exdes.ucf
@@ -0,0 +1,60 @@
+# file: DFT_CLK_exdes.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps;
+
+
+# FALSE PATH constraints
+PIN "COUNTER_RESET" TIG;
+PIN "RESET" TIG;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK/example_design/DFT_CLK_exdes.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK/example_design/DFT_CLK_exdes.vhd
new file mode 100644
index 0000000..ed2c2d6
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK/example_design/DFT_CLK_exdes.vhd
@@ -0,0 +1,192 @@
+-- file: DFT_CLK_exdes.vhd
+--
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+
+------------------------------------------------------------------------------
+-- Clocking wizard example design
+------------------------------------------------------------------------------
+-- This example design instantiates the created clocking network, where each
+-- output clock drives a counter. The high bit of each counter is ported.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity DFT_CLK_exdes is
+generic (
+ TCQ : in time := 100 ps);
+port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Reset that only drives logic in example design
+ COUNTER_RESET : in std_logic;
+ CLK_OUT : out std_logic_vector(1 downto 1) ;
+ -- High bits of counters driven by clocks
+ COUNT : out std_logic;
+ -- Status and control signals
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end DFT_CLK_exdes;
+
+architecture xilinx of DFT_CLK_exdes is
+
+ -- Parameters for the counters
+ ---------------------------------
+ -- Counter width
+ constant C_W : integer := 16;
+
+
+ -- When the clock goes out of lock, reset the counters
+ signal locked_int : std_logic;
+ signal reset_int : std_logic := '0';
+
+ -- Declare the clocks and counter
+ signal clk : std_logic;
+ signal clk_int : std_logic;
+ signal clk_n : std_logic;
+ signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
+
+ -- Need to buffer input clocks that aren't already buffered
+ signal clk_in1_buf : std_logic;
+ signal rst_sync : std_logic;
+ signal rst_sync_int : std_logic;
+ signal rst_sync_int1 : std_logic;
+ signal rst_sync_int2 : std_logic;
+
+
+component DFT_CLK is
+port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Clock out ports
+ CLK_OUT1 : out std_logic;
+ -- Status and control signals
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+begin
+ -- Alias output to internally used signal
+ LOCKED <= locked_int;
+
+ -- When the clock goes out of lock, reset the counters
+ reset_int <= (not locked_int) or RESET or COUNTER_RESET;
+
+
+ process (clk, reset_int) begin
+ if (reset_int = '1') then
+ rst_sync <= '1';
+ rst_sync_int <= '1';
+ rst_sync_int1 <= '1';
+ rst_sync_int2 <= '1';
+ elsif (clk 'event and clk='1') then
+ rst_sync <= '0';
+ rst_sync_int <= rst_sync;
+ rst_sync_int1 <= rst_sync_int;
+ rst_sync_int2 <= rst_sync_int1;
+ end if;
+ end process;
+
+
+ -- Insert BUFGs on all input clocks that don't already have them
+ ----------------------------------------------------------------
+ clkin1_buf : BUFG
+ port map
+ (O => clk_in1_buf,
+ I => CLK_IN1);
+
+ -- Instantiation of the clocking network
+ ----------------------------------------
+ clknetwork : DFT_CLK
+ port map
+ (-- Clock in ports
+ CLK_IN1 => clk_in1_buf,
+ -- Clock out ports
+ CLK_OUT1 => clk_int,
+ -- Status and control signals
+ RESET => RESET,
+ LOCKED => locked_int);
+
+ clk_n <= not clk;
+ clkout_oddr : ODDR2
+ port map
+ (Q => CLK_OUT(1),
+ C0 => clk,
+ C1 => clk_n,
+ CE => '1',
+ D0 => '1',
+ D1 => '0',
+ R => '0',
+ S => '0');
+
+ -- Connect the output clocks to the design
+ -------------------------------------------
+ clk <= clk_int;
+
+ -- Output clock sampling
+ -------------------------------------
+ process (clk, rst_sync_int2) begin
+ if (rst_sync_int2 = '1') then
+ counter <= (others => '0') after TCQ;
+ elsif (rising_edge(clk)) then
+ counter <= counter + 1 after TCQ;
+ end if;
+ end process;
+ -- alias the high bit to the output
+ COUNT <= counter(C_W-1);
+
+
+end xilinx;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK/simulation/DFT_CLK_tb.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK/simulation/DFT_CLK_tb.vhd
new file mode 100644
index 0000000..d425375
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK/simulation/DFT_CLK_tb.vhd
@@ -0,0 +1,197 @@
+-- file: DFT_CLK_tb.vhd
+--
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+
+------------------------------------------------------------------------------
+-- Clocking wizard demonstration testbench
+------------------------------------------------------------------------------
+-- This demonstration testbench instantiates the example design for the
+-- clocking wizard. Input clocks are toggled, which cause the clocking
+-- network to lock and the counters to increment.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+
+library std;
+use std.textio.all;
+
+library work;
+use work.all;
+
+entity DFT_CLK_tb is
+end DFT_CLK_tb;
+
+architecture test of DFT_CLK_tb is
+
+ -- Clock to Q delay of 100 ps
+ constant TCQ : time := 100 ps;
+ -- timescale is 1ps
+ constant ONE_NS : time := 1 ns;
+ -- how many cycles to run
+ constant COUNT_PHASE : integer := 1024 + 1;
+
+
+ -- we'll be using the period in many locations
+ constant PER1 : time := 62.5 ns;
+
+
+ -- Declare the input clock signals
+ signal CLK_IN1 : std_logic := '1';
+ -- The high bit of the sampling counter
+ signal COUNT : std_logic;
+ -- Status and control signals
+ signal RESET : std_logic := '0';
+ signal LOCKED : std_logic;
+ signal COUNTER_RESET : std_logic := '0';
+-- signal defined to stop mti simulation without severity failure in the report
+ signal end_of_sim : std_logic := '0';
+ signal CLK_OUT : std_logic_vector(1 downto 1);
+--Freq Check using the M & D values setting and actual Frequency generated
+
+component DFT_CLK_exdes
+generic (
+ TCQ : in time := 100 ps);
+port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Reset that only drives logic in example design
+ COUNTER_RESET : in std_logic;
+ CLK_OUT : out std_logic_vector(1 downto 1) ;
+ -- High bits of counters driven by clocks
+ COUNT : out std_logic;
+ -- Status and control signals
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+begin
+
+ -- Input clock generation
+ --------------------------------------
+ process begin
+ CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
+ end process;
+
+ -- Test sequence
+ process
+
+ procedure simtimeprint is
+ variable outline : line;
+ begin
+ write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
+ write(outline, NOW/PER1);
+ write(outline, string'(" ns"));
+ writeline(output,outline);
+ end simtimeprint;
+
+ procedure simfreqprint (period : time; clk_num : integer) is
+ variable outputline : LINE;
+ variable str1 : string(1 to 16);
+ variable str2 : integer;
+ variable str3 : string(1 to 2);
+ variable str4 : integer;
+ variable str5 : string(1 to 4);
+ begin
+ str1 := "Freq of CLK_OUT(";
+ str2 := clk_num;
+ str3 := ") ";
+ str4 := 1000000 ps/period ;
+ str5 := " MHz" ;
+ write(outputline, str1 );
+ write(outputline, str2);
+ write(outputline, str3);
+ write(outputline, str4);
+ write(outputline, str5);
+ writeline(output, outputline);
+ end simfreqprint;
+
+ begin
+ RESET <= '1';
+ wait for (PER1*6);
+ RESET <= '0';
+ wait until LOCKED = '1';
+ COUNTER_RESET <= '1';
+ wait for (PER1*20);
+ COUNTER_RESET <= '0';
+ wait for (PER1*COUNT_PHASE);
+
+
+ simtimeprint;
+ end_of_sim <= '1';
+ wait for 1 ps;
+ report "Simulation Stopped." severity failure;
+ wait;
+ end process;
+
+ -- Instantiation of the example design containing the clock
+ -- network and sampling counters
+ -----------------------------------------------------------
+ dut : DFT_CLK_exdes
+ generic map (
+ TCQ => TCQ)
+ port map
+ (-- Clock in ports
+ CLK_IN1 => CLK_IN1,
+ -- Reset for logic in example design
+ COUNTER_RESET => COUNTER_RESET,
+ CLK_OUT => CLK_OUT,
+ -- High bits of the counters
+ COUNT => COUNT,
+ -- Status and control signals
+ RESET => RESET,
+ LOCKED => LOCKED);
+
+-- Freq Check
+
+end test;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK/simulation/timing/DFT_CLK_tb.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK/simulation/timing/DFT_CLK_tb.vhd
new file mode 100644
index 0000000..7d7055c
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DFT_CLK/simulation/timing/DFT_CLK_tb.vhd
@@ -0,0 +1,220 @@
+-- file: DFT_CLK_tb.vhd
+--
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+
+------------------------------------------------------------------------------
+-- Clocking wizard demonstration testbench
+------------------------------------------------------------------------------
+-- This demonstration testbench instantiates the example design for the
+-- clocking wizard. Input clocks are toggled, which cause the clocking
+-- network to lock and the counters to increment.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+
+library std;
+use std.textio.all;
+
+library work;
+use work.all;
+
+entity DFT_CLK_tb is
+end DFT_CLK_tb;
+
+architecture test of DFT_CLK_tb is
+
+ -- Clock to Q delay of 100 ps
+ constant TCQ : time := 100 ps;
+ -- timescale is 1ps
+ constant ONE_NS : time := 1 ns;
+ -- how many cycles to run
+ constant COUNT_PHASE : integer := 1024 + 1;
+
+
+ -- we'll be using the period in many locations
+ constant PER1 : time := 62.5 ns;
+
+
+ -- Declare the input clock signals
+ signal CLK_IN1 : std_logic := '1';
+ -- The high bit of the sampling counter
+ signal COUNT : std_logic;
+ -- Status and control signals
+ signal RESET : std_logic := '0';
+ signal LOCKED : std_logic;
+ signal COUNTER_RESET : std_logic := '0';
+ signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
+-- signal defined to stop mti simulation without severity failure in the report
+ signal end_of_sim : std_logic := '0';
+ signal CLK_OUT : std_logic_vector(1 downto 1);
+--Freq Check using the M & D values setting and actual Frequency generated
+
+component DFT_CLK_exdes
+port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Reset that only drives logic in example design
+ COUNTER_RESET : in std_logic;
+ CLK_OUT : out std_logic_vector(1 downto 1) ;
+ -- High bits of counters driven by clocks
+ COUNT : out std_logic;
+ -- Status and control signals
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+begin
+
+ -- Input clock generation
+ --------------------------------------
+ process begin
+ CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
+ end process;
+
+ -- Test sequence
+ process
+
+ procedure simtimeprint is
+ variable outline : line;
+ begin
+ write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
+ write(outline, NOW/PER1);
+ write(outline, string'(" ns"));
+ writeline(output,outline);
+ end simtimeprint;
+
+ procedure simfreqprint (period : time; clk_num : integer) is
+ variable outputline : LINE;
+ variable str1 : string(1 to 16);
+ variable str2 : integer;
+ variable str3 : string(1 to 2);
+ variable str4 : integer;
+ variable str5 : string(1 to 4);
+ begin
+ str1 := "Freq of CLK_OUT(";
+ str2 := clk_num;
+ str3 := ") ";
+ str4 := 1000000 ps/period ;
+ str5 := " MHz" ;
+ write(outputline, str1 );
+ write(outputline, str2);
+ write(outputline, str3);
+ write(outputline, str4);
+ write(outputline, str5);
+ writeline(output, outputline);
+ end simfreqprint;
+
+ begin
+ report "Timing checks are not valid" severity note;
+ RESET <= '1';
+ wait for (PER1*6);
+ RESET <= '0';
+ wait until LOCKED = '1';
+ wait for (PER1*20);
+ COUNTER_RESET <= '1';
+ wait for (PER1*19.5);
+ COUNTER_RESET <= '0';
+ wait for (PER1*1);
+ report "Timing checks are valid" severity note;
+ wait for (PER1*COUNT_PHASE);
+
+
+ simtimeprint;
+ end_of_sim <= '1';
+ wait for 1 ps;
+ report "Simulation Stopped." severity failure;
+ wait;
+ end process;
+
+ process (CLK_IN1)
+ procedure simtimeprint is
+ variable outline : line;
+ begin
+ write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
+ write(outline, NOW/PER1);
+ write(outline, string'(" ns"));
+ writeline(output,outline);
+ end simtimeprint;
+ begin
+ if (CLK_IN1'event and CLK_IN1='1') then
+ timeout_counter <= timeout_counter + '1';
+ if (timeout_counter = "10000000000000") then
+ if (LOCKED /= '1') then
+ simtimeprint;
+ report "NO LOCK signal" severity failure;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ -- Instantiation of the example design containing the clock
+ -- network and sampling counters
+ -----------------------------------------------------------
+ dut : DFT_CLK_exdes
+ port map
+ (-- Clock in ports
+ CLK_IN1 => CLK_IN1,
+ -- Reset for logic in example design
+ COUNTER_RESET => COUNTER_RESET,
+ CLK_OUT => CLK_OUT,
+ -- High bits of the counters
+ COUNT => COUNT,
+ -- Status and control signals
+ RESET => RESET,
+ LOCKED => LOCKED);
+
+-- Freq Check
+
+end test;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DSP48.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DSP48.gise
new file mode 100644
index 0000000..93248ea
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DSP48.gise
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DSP48.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DSP48.vhd
new file mode 100644
index 0000000..5895fe1
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DSP48.vhd
@@ -0,0 +1,139 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2020 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file DSP48.vhd when simulating
+-- the core, DSP48. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY DSP48 IS
+ PORT (
+ clk : IN STD_LOGIC;
+ ce : IN STD_LOGIC;
+ sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+ p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+ );
+END DSP48;
+
+ARCHITECTURE DSP48_a OF DSP48 IS
+-- synthesis translate_off
+COMPONENT wrapped_DSP48
+ PORT (
+ clk : IN STD_LOGIC;
+ ce : IN STD_LOGIC;
+ sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+ p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_DSP48 USE ENTITY XilinxCoreLib.xbip_dsp48_macro_v2_1(behavioral)
+ GENERIC MAP (
+ c_a_width => 18,
+ c_b_width => 18,
+ c_c_width => 48,
+ c_concat_width => 48,
+ c_constant_1 => 1,
+ c_d_width => 18,
+ c_has_a => 1,
+ c_has_acin => 0,
+ c_has_acout => 0,
+ c_has_b => 1,
+ c_has_bcin => 0,
+ c_has_bcout => 0,
+ c_has_c => 1,
+ c_has_carrycascin => 0,
+ c_has_carrycascout => 0,
+ c_has_carryin => 0,
+ c_has_carryout => 0,
+ c_has_ce => 1,
+ c_has_cea => 0,
+ c_has_ceb => 0,
+ c_has_cec => 0,
+ c_has_ceconcat => 0,
+ c_has_ced => 0,
+ c_has_cem => 0,
+ c_has_cep => 0,
+ c_has_cesel => 0,
+ c_has_concat => 0,
+ c_has_d => 0,
+ c_has_indep_ce => 0,
+ c_has_indep_sclr => 0,
+ c_has_pcin => 0,
+ c_has_pcout => 0,
+ c_has_sclr => 0,
+ c_has_sclra => 0,
+ c_has_sclrb => 0,
+ c_has_sclrc => 0,
+ c_has_sclrconcat => 0,
+ c_has_sclrd => 0,
+ c_has_sclrm => 0,
+ c_has_sclrp => 0,
+ c_has_sclrsel => 0,
+ c_latency => -1,
+ c_model_type => 0,
+ c_opmodes => "0000000000010000000,0000001100010000000",
+ c_p_lsb => 0,
+ c_p_msb => 47,
+ c_reg_config => "00000000000011100111100111100100",
+ c_sel_width => 1,
+ c_test_core => 0,
+ c_verbosity => 0,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_DSP48
+ PORT MAP (
+ clk => clk,
+ ce => ce,
+ sel => sel,
+ a => a,
+ b => b,
+ c => c,
+ p => p
+ );
+-- synthesis translate_on
+
+END DSP48_a;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DSP_SLICE.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DSP_SLICE.gise
new file mode 100644
index 0000000..edc3d0f
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DSP_SLICE.gise
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DSP_SLICE.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DSP_SLICE.vhd
new file mode 100644
index 0000000..c378c8c
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/DSP_SLICE.vhd
@@ -0,0 +1,139 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2020 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file DSP_SLICE.vhd when simulating
+-- the core, DSP_SLICE. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY DSP_SLICE IS
+ PORT (
+ clk : IN STD_LOGIC;
+ ce : IN STD_LOGIC;
+ sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+ p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+ );
+END DSP_SLICE;
+
+ARCHITECTURE DSP_SLICE_a OF DSP_SLICE IS
+-- synthesis translate_off
+COMPONENT wrapped_DSP_SLICE
+ PORT (
+ clk : IN STD_LOGIC;
+ ce : IN STD_LOGIC;
+ sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+ p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_DSP_SLICE USE ENTITY XilinxCoreLib.xbip_dsp48_macro_v2_1(behavioral)
+ GENERIC MAP (
+ c_a_width => 18,
+ c_b_width => 18,
+ c_c_width => 48,
+ c_concat_width => 48,
+ c_constant_1 => 1,
+ c_d_width => 18,
+ c_has_a => 1,
+ c_has_acin => 0,
+ c_has_acout => 0,
+ c_has_b => 1,
+ c_has_bcin => 0,
+ c_has_bcout => 0,
+ c_has_c => 1,
+ c_has_carrycascin => 0,
+ c_has_carrycascout => 0,
+ c_has_carryin => 0,
+ c_has_carryout => 0,
+ c_has_ce => 1,
+ c_has_cea => 0,
+ c_has_ceb => 0,
+ c_has_cec => 0,
+ c_has_ceconcat => 0,
+ c_has_ced => 0,
+ c_has_cem => 0,
+ c_has_cep => 0,
+ c_has_cesel => 0,
+ c_has_concat => 0,
+ c_has_d => 0,
+ c_has_indep_ce => 0,
+ c_has_indep_sclr => 0,
+ c_has_pcin => 0,
+ c_has_pcout => 0,
+ c_has_sclr => 0,
+ c_has_sclra => 0,
+ c_has_sclrb => 0,
+ c_has_sclrc => 0,
+ c_has_sclrconcat => 0,
+ c_has_sclrd => 0,
+ c_has_sclrm => 0,
+ c_has_sclrp => 0,
+ c_has_sclrsel => 0,
+ c_latency => -1,
+ c_model_type => 0,
+ c_opmodes => "0000000000010000000,0000001100010000000",
+ c_p_lsb => 0,
+ c_p_msb => 47,
+ c_reg_config => "00000000000011100111100111100100",
+ c_sel_width => 1,
+ c_test_core => 0,
+ c_verbosity => 0,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_DSP_SLICE
+ PORT MAP (
+ clk => clk,
+ ce => ce,
+ sel => sel,
+ a => a,
+ b => b,
+ c => c,
+ p => p
+ );
+-- synthesis translate_on
+
+END DSP_SLICE_a;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/ModulationMemory.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/ModulationMemory.gise
new file mode 100644
index 0000000..f652c16
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/ModulationMemory.gise
@@ -0,0 +1,53 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/ModulationMemory.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/ModulationMemory.vhd
new file mode 100644
index 0000000..0c4ec46
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/ModulationMemory.vhd
@@ -0,0 +1,149 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2022 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file ModulationMemory.vhd when simulating
+-- the core, ModulationMemory. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY ModulationMemory IS
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(143 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(143 DOWNTO 0)
+ );
+END ModulationMemory;
+
+ARCHITECTURE ModulationMemory_a OF ModulationMemory IS
+-- synthesis translate_off
+COMPONENT wrapped_ModulationMemory
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(143 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(143 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_ModulationMemory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
+ GENERIC MAP (
+ c_addra_width => 8,
+ c_addrb_width => 8,
+ c_algorithm => 1,
+ c_axi_id_width => 4,
+ c_axi_slave_type => 0,
+ c_axi_type => 1,
+ c_byte_size => 9,
+ c_common_clk => 0,
+ c_default_data => "0",
+ c_disable_warn_bhv_coll => 0,
+ c_disable_warn_bhv_range => 0,
+ c_enable_32bit_address => 0,
+ c_family => "spartan6",
+ c_has_axi_id => 0,
+ c_has_ena => 0,
+ c_has_enb => 0,
+ c_has_injecterr => 0,
+ c_has_mem_output_regs_a => 0,
+ c_has_mem_output_regs_b => 0,
+ c_has_mux_output_regs_a => 0,
+ c_has_mux_output_regs_b => 0,
+ c_has_regcea => 0,
+ c_has_regceb => 0,
+ c_has_rsta => 0,
+ c_has_rstb => 0,
+ c_has_softecc_input_regs_a => 0,
+ c_has_softecc_output_regs_b => 0,
+ c_init_file => "BlankString",
+ c_init_file_name => "no_coe_file_loaded",
+ c_inita_val => "0",
+ c_initb_val => "0",
+ c_interface_type => 0,
+ c_load_init_file => 0,
+ c_mem_type => 1,
+ c_mux_pipeline_stages => 0,
+ c_prim_type => 1,
+ c_read_depth_a => 256,
+ c_read_depth_b => 256,
+ c_read_width_a => 144,
+ c_read_width_b => 144,
+ c_rst_priority_a => "CE",
+ c_rst_priority_b => "CE",
+ c_rst_type => "SYNC",
+ c_rstram_a => 0,
+ c_rstram_b => 0,
+ c_sim_collision_check => "ALL",
+ c_use_bram_block => 0,
+ c_use_byte_wea => 0,
+ c_use_byte_web => 0,
+ c_use_default_data => 0,
+ c_use_ecc => 0,
+ c_use_softecc => 0,
+ c_wea_width => 1,
+ c_web_width => 1,
+ c_write_depth_a => 256,
+ c_write_depth_b => 256,
+ c_write_mode_a => "WRITE_FIRST",
+ c_write_mode_b => "WRITE_FIRST",
+ c_write_width_a => 144,
+ c_write_width_b => 144,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_ModulationMemory
+ PORT MAP (
+ clka => clka,
+ wea => wea,
+ addra => addra,
+ dina => dina,
+ clkb => clkb,
+ addrb => addrb,
+ doutb => doutb
+ );
+-- synthesis translate_on
+
+END ModulationMemory_a;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL.gise
new file mode 100644
index 0000000..2143394
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL.gise
@@ -0,0 +1,52 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL.ucf b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL.ucf
new file mode 100644
index 0000000..609adfb
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL.ucf
@@ -0,0 +1,59 @@
+# file: PLL.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps;
+
+
+# FALSE PATH constraints
+PIN "RESET" TIG;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL.vhd
new file mode 100644
index 0000000..5b1fe31
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL.vhd
@@ -0,0 +1,172 @@
+-- file: PLL.vhd
+--
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output Output Phase Duty Pk-to-Pk Phase"
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1___102.400______0.000______50.0_____1274.405____150.000
+--
+------------------------------------------------------------------------------
+-- "Input Clock Freq (MHz) Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary______________16____________0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity PLL is
+port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Clock out ports
+ CLK_OUT1 : out std_logic;
+ -- Status and control signals
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end PLL;
+
+architecture xilinx of PLL is
+ attribute CORE_GENERATION_INFO : string;
+ attribute CORE_GENERATION_INFO of xilinx : architecture is "PLL,clk_wiz_v3_6,{component_name=PLL,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=62.5,clkin2_period=62.5,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
+ -- Input clock buffering / unused connectors
+ signal clkin1 : std_logic;
+ -- Output clock buffering
+ signal clkfb : std_logic;
+ signal clk0 : std_logic;
+ signal clkfx : std_logic;
+ signal clkfbout : std_logic;
+ signal locked_internal : std_logic;
+ signal status_internal : std_logic_vector(7 downto 0);
+begin
+
+
+ -- Input buffering
+ --------------------------------------
+ clkin1_buf : IBUFG
+ port map
+ (O => clkin1,
+ I => CLK_IN1);
+
+
+ -- Clocking primitive
+ --------------------------------------
+
+ -- Instantiation of the DCM primitive
+ -- * Unused inputs are tied off
+ -- * Unused outputs are labeled unused
+ dcm_sp_inst: DCM_SP
+ generic map
+ (CLKDV_DIVIDE => 2.000,
+ CLKFX_DIVIDE => 5,
+ CLKFX_MULTIPLY => 32,
+ CLKIN_DIVIDE_BY_2 => FALSE,
+ CLKIN_PERIOD => 62.5,
+ CLKOUT_PHASE_SHIFT => "NONE",
+ CLK_FEEDBACK => "1X",
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+ PHASE_SHIFT => 0,
+ STARTUP_WAIT => FALSE)
+ port map
+ -- Input clock
+ (CLKIN => clkin1,
+ CLKFB => clkfb,
+ -- Output clocks
+ CLK0 => clk0,
+ CLK90 => open,
+ CLK180 => open,
+ CLK270 => open,
+ CLK2X => open,
+ CLK2X180 => open,
+ CLKFX => clkfx,
+ CLKFX180 => open,
+ CLKDV => open,
+ -- Ports for dynamic phase shift
+ PSCLK => '0',
+ PSEN => '0',
+ PSINCDEC => '0',
+ PSDONE => open,
+ -- Other control and status signals
+ LOCKED => locked_internal,
+ STATUS => status_internal,
+ RST => RESET,
+ -- Unused pin, tie low
+ DSSEN => '0');
+
+ LOCKED <= locked_internal;
+
+
+
+ -- Output buffering
+ -------------------------------------
+ clkf_buf : BUFG
+ port map
+ (O => clkfb,
+ I => clk0);
+
+
+ clkout1_buf : BUFG
+ port map
+ (O => CLK_OUT1,
+ I => clkfx);
+
+
+
+end xilinx;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL/example_design/PLL_exdes.ucf b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL/example_design/PLL_exdes.ucf
new file mode 100644
index 0000000..7b69c75
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL/example_design/PLL_exdes.ucf
@@ -0,0 +1,60 @@
+# file: PLL_exdes.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps;
+
+
+# FALSE PATH constraints
+PIN "COUNTER_RESET" TIG;
+PIN "RESET" TIG;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL/example_design/PLL_exdes.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL/example_design/PLL_exdes.vhd
new file mode 100644
index 0000000..7feb2bc
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL/example_design/PLL_exdes.vhd
@@ -0,0 +1,182 @@
+-- file: PLL_exdes.vhd
+--
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+
+------------------------------------------------------------------------------
+-- Clocking wizard example design
+------------------------------------------------------------------------------
+-- This example design instantiates the created clocking network, where each
+-- output clock drives a counter. The high bit of each counter is ported.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity PLL_exdes is
+generic (
+ TCQ : in time := 100 ps);
+port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Reset that only drives logic in example design
+ COUNTER_RESET : in std_logic;
+ CLK_OUT : out std_logic_vector(1 downto 1) ;
+ -- High bits of counters driven by clocks
+ COUNT : out std_logic;
+ -- Status and control signals
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end PLL_exdes;
+
+architecture xilinx of PLL_exdes is
+
+ -- Parameters for the counters
+ ---------------------------------
+ -- Counter width
+ constant C_W : integer := 16;
+
+
+ -- When the clock goes out of lock, reset the counters
+ signal locked_int : std_logic;
+ signal reset_int : std_logic := '0';
+
+ -- Declare the clocks and counter
+ signal clk : std_logic;
+ signal clk_int : std_logic;
+ signal clk_n : std_logic;
+ signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
+ signal rst_sync : std_logic;
+ signal rst_sync_int : std_logic;
+ signal rst_sync_int1 : std_logic;
+ signal rst_sync_int2 : std_logic;
+
+
+component PLL is
+port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Clock out ports
+ CLK_OUT1 : out std_logic;
+ -- Status and control signals
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+begin
+ -- Alias output to internally used signal
+ LOCKED <= locked_int;
+
+ -- When the clock goes out of lock, reset the counters
+ reset_int <= (not locked_int) or RESET or COUNTER_RESET;
+
+
+ process (clk, reset_int) begin
+ if (reset_int = '1') then
+ rst_sync <= '1';
+ rst_sync_int <= '1';
+ rst_sync_int1 <= '1';
+ rst_sync_int2 <= '1';
+ elsif (clk 'event and clk='1') then
+ rst_sync <= '0';
+ rst_sync_int <= rst_sync;
+ rst_sync_int1 <= rst_sync_int;
+ rst_sync_int2 <= rst_sync_int1;
+ end if;
+ end process;
+
+
+ -- Instantiation of the clocking network
+ ----------------------------------------
+ clknetwork : PLL
+ port map
+ (-- Clock in ports
+ CLK_IN1 => CLK_IN1,
+ -- Clock out ports
+ CLK_OUT1 => clk_int,
+ -- Status and control signals
+ RESET => RESET,
+ LOCKED => locked_int);
+
+ clk_n <= not clk;
+ clkout_oddr : ODDR2
+ port map
+ (Q => CLK_OUT(1),
+ C0 => clk,
+ C1 => clk_n,
+ CE => '1',
+ D0 => '1',
+ D1 => '0',
+ R => '0',
+ S => '0');
+
+ -- Connect the output clocks to the design
+ -------------------------------------------
+ clk <= clk_int;
+
+ -- Output clock sampling
+ -------------------------------------
+ process (clk, rst_sync_int2) begin
+ if (rst_sync_int2 = '1') then
+ counter <= (others => '0') after TCQ;
+ elsif (rising_edge(clk)) then
+ counter <= counter + 1 after TCQ;
+ end if;
+ end process;
+ -- alias the high bit to the output
+ COUNT <= counter(C_W-1);
+
+
+end xilinx;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL/simulation/PLL_tb.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL/simulation/PLL_tb.vhd
new file mode 100644
index 0000000..3448143
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL/simulation/PLL_tb.vhd
@@ -0,0 +1,197 @@
+-- file: PLL_tb.vhd
+--
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+
+------------------------------------------------------------------------------
+-- Clocking wizard demonstration testbench
+------------------------------------------------------------------------------
+-- This demonstration testbench instantiates the example design for the
+-- clocking wizard. Input clocks are toggled, which cause the clocking
+-- network to lock and the counters to increment.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+
+library std;
+use std.textio.all;
+
+library work;
+use work.all;
+
+entity PLL_tb is
+end PLL_tb;
+
+architecture test of PLL_tb is
+
+ -- Clock to Q delay of 100 ps
+ constant TCQ : time := 100 ps;
+ -- timescale is 1ps
+ constant ONE_NS : time := 1 ns;
+ -- how many cycles to run
+ constant COUNT_PHASE : integer := 1024 + 1;
+
+
+ -- we'll be using the period in many locations
+ constant PER1 : time := 62.5 ns;
+
+
+ -- Declare the input clock signals
+ signal CLK_IN1 : std_logic := '1';
+ -- The high bit of the sampling counter
+ signal COUNT : std_logic;
+ -- Status and control signals
+ signal RESET : std_logic := '0';
+ signal LOCKED : std_logic;
+ signal COUNTER_RESET : std_logic := '0';
+-- signal defined to stop mti simulation without severity failure in the report
+ signal end_of_sim : std_logic := '0';
+ signal CLK_OUT : std_logic_vector(1 downto 1);
+--Freq Check using the M & D values setting and actual Frequency generated
+
+component PLL_exdes
+generic (
+ TCQ : in time := 100 ps);
+port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Reset that only drives logic in example design
+ COUNTER_RESET : in std_logic;
+ CLK_OUT : out std_logic_vector(1 downto 1) ;
+ -- High bits of counters driven by clocks
+ COUNT : out std_logic;
+ -- Status and control signals
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+begin
+
+ -- Input clock generation
+ --------------------------------------
+ process begin
+ CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
+ end process;
+
+ -- Test sequence
+ process
+
+ procedure simtimeprint is
+ variable outline : line;
+ begin
+ write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
+ write(outline, NOW/PER1);
+ write(outline, string'(" ns"));
+ writeline(output,outline);
+ end simtimeprint;
+
+ procedure simfreqprint (period : time; clk_num : integer) is
+ variable outputline : LINE;
+ variable str1 : string(1 to 16);
+ variable str2 : integer;
+ variable str3 : string(1 to 2);
+ variable str4 : integer;
+ variable str5 : string(1 to 4);
+ begin
+ str1 := "Freq of CLK_OUT(";
+ str2 := clk_num;
+ str3 := ") ";
+ str4 := 1000000 ps/period ;
+ str5 := " MHz" ;
+ write(outputline, str1 );
+ write(outputline, str2);
+ write(outputline, str3);
+ write(outputline, str4);
+ write(outputline, str5);
+ writeline(output, outputline);
+ end simfreqprint;
+
+ begin
+ RESET <= '1';
+ wait for (PER1*6);
+ RESET <= '0';
+ wait until LOCKED = '1';
+ COUNTER_RESET <= '1';
+ wait for (PER1*20);
+ COUNTER_RESET <= '0';
+ wait for (PER1*COUNT_PHASE);
+
+
+ simtimeprint;
+ end_of_sim <= '1';
+ wait for 1 ps;
+ report "Simulation Stopped." severity failure;
+ wait;
+ end process;
+
+ -- Instantiation of the example design containing the clock
+ -- network and sampling counters
+ -----------------------------------------------------------
+ dut : PLL_exdes
+ generic map (
+ TCQ => TCQ)
+ port map
+ (-- Clock in ports
+ CLK_IN1 => CLK_IN1,
+ -- Reset for logic in example design
+ COUNTER_RESET => COUNTER_RESET,
+ CLK_OUT => CLK_OUT,
+ -- High bits of the counters
+ COUNT => COUNT,
+ -- Status and control signals
+ RESET => RESET,
+ LOCKED => LOCKED);
+
+-- Freq Check
+
+end test;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL/simulation/timing/PLL_tb.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL/simulation/timing/PLL_tb.vhd
new file mode 100644
index 0000000..e04f5b6
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/PLL/simulation/timing/PLL_tb.vhd
@@ -0,0 +1,220 @@
+-- file: PLL_tb.vhd
+--
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+
+------------------------------------------------------------------------------
+-- Clocking wizard demonstration testbench
+------------------------------------------------------------------------------
+-- This demonstration testbench instantiates the example design for the
+-- clocking wizard. Input clocks are toggled, which cause the clocking
+-- network to lock and the counters to increment.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+
+library std;
+use std.textio.all;
+
+library work;
+use work.all;
+
+entity PLL_tb is
+end PLL_tb;
+
+architecture test of PLL_tb is
+
+ -- Clock to Q delay of 100 ps
+ constant TCQ : time := 100 ps;
+ -- timescale is 1ps
+ constant ONE_NS : time := 1 ns;
+ -- how many cycles to run
+ constant COUNT_PHASE : integer := 1024 + 1;
+
+
+ -- we'll be using the period in many locations
+ constant PER1 : time := 62.5 ns;
+
+
+ -- Declare the input clock signals
+ signal CLK_IN1 : std_logic := '1';
+ -- The high bit of the sampling counter
+ signal COUNT : std_logic;
+ -- Status and control signals
+ signal RESET : std_logic := '0';
+ signal LOCKED : std_logic;
+ signal COUNTER_RESET : std_logic := '0';
+ signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
+-- signal defined to stop mti simulation without severity failure in the report
+ signal end_of_sim : std_logic := '0';
+ signal CLK_OUT : std_logic_vector(1 downto 1);
+--Freq Check using the M & D values setting and actual Frequency generated
+
+component PLL_exdes
+port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Reset that only drives logic in example design
+ COUNTER_RESET : in std_logic;
+ CLK_OUT : out std_logic_vector(1 downto 1) ;
+ -- High bits of counters driven by clocks
+ COUNT : out std_logic;
+ -- Status and control signals
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end component;
+
+begin
+
+ -- Input clock generation
+ --------------------------------------
+ process begin
+ CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
+ end process;
+
+ -- Test sequence
+ process
+
+ procedure simtimeprint is
+ variable outline : line;
+ begin
+ write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
+ write(outline, NOW/PER1);
+ write(outline, string'(" ns"));
+ writeline(output,outline);
+ end simtimeprint;
+
+ procedure simfreqprint (period : time; clk_num : integer) is
+ variable outputline : LINE;
+ variable str1 : string(1 to 16);
+ variable str2 : integer;
+ variable str3 : string(1 to 2);
+ variable str4 : integer;
+ variable str5 : string(1 to 4);
+ begin
+ str1 := "Freq of CLK_OUT(";
+ str2 := clk_num;
+ str3 := ") ";
+ str4 := 1000000 ps/period ;
+ str5 := " MHz" ;
+ write(outputline, str1 );
+ write(outputline, str2);
+ write(outputline, str3);
+ write(outputline, str4);
+ write(outputline, str5);
+ writeline(output, outputline);
+ end simfreqprint;
+
+ begin
+ report "Timing checks are not valid" severity note;
+ RESET <= '1';
+ wait for (PER1*6);
+ RESET <= '0';
+ wait until LOCKED = '1';
+ wait for (PER1*20);
+ COUNTER_RESET <= '1';
+ wait for (PER1*19.5);
+ COUNTER_RESET <= '0';
+ wait for (PER1*1);
+ report "Timing checks are valid" severity note;
+ wait for (PER1*COUNT_PHASE);
+
+
+ simtimeprint;
+ end_of_sim <= '1';
+ wait for 1 ps;
+ report "Simulation Stopped." severity failure;
+ wait;
+ end process;
+
+ process (CLK_IN1)
+ procedure simtimeprint is
+ variable outline : line;
+ begin
+ write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
+ write(outline, NOW/PER1);
+ write(outline, string'(" ns"));
+ writeline(output,outline);
+ end simtimeprint;
+ begin
+ if (CLK_IN1'event and CLK_IN1='1') then
+ timeout_counter <= timeout_counter + '1';
+ if (timeout_counter = "10000000000000") then
+ if (LOCKED /= '1') then
+ simtimeprint;
+ report "NO LOCK signal" severity failure;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ -- Instantiation of the example design containing the clock
+ -- network and sampling counters
+ -----------------------------------------------------------
+ dut : PLL_exdes
+ port map
+ (-- Clock in ports
+ CLK_IN1 => CLK_IN1,
+ -- Reset for logic in example design
+ COUNTER_RESET => COUNTER_RESET,
+ CLK_OUT => CLK_OUT,
+ -- High bits of the counters
+ COUNT => COUNT,
+ -- Status and control signals
+ RESET => RESET,
+ LOCKED => LOCKED);
+
+-- Freq Check
+
+end test;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SampleMemory.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SampleMemory.gise
new file mode 100644
index 0000000..1b9c9e1
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SampleMemory.gise
@@ -0,0 +1,53 @@
+
+
+
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SampleMemory.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SampleMemory.vhd
new file mode 100644
index 0000000..8f6e7e1
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SampleMemory.vhd
@@ -0,0 +1,149 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2022 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file SampleMemory.vhd when simulating
+-- the core, SampleMemory. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY SampleMemory IS
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+ );
+END SampleMemory;
+
+ARCHITECTURE SampleMemory_a OF SampleMemory IS
+-- synthesis translate_off
+COMPONENT wrapped_SampleMemory
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_SampleMemory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
+ GENERIC MAP (
+ c_addra_width => 11,
+ c_addrb_width => 11,
+ c_algorithm => 1,
+ c_axi_id_width => 4,
+ c_axi_slave_type => 0,
+ c_axi_type => 1,
+ c_byte_size => 9,
+ c_common_clk => 0,
+ c_default_data => "0",
+ c_disable_warn_bhv_coll => 0,
+ c_disable_warn_bhv_range => 0,
+ c_enable_32bit_address => 0,
+ c_family => "spartan6",
+ c_has_axi_id => 0,
+ c_has_ena => 0,
+ c_has_enb => 0,
+ c_has_injecterr => 0,
+ c_has_mem_output_regs_a => 0,
+ c_has_mem_output_regs_b => 0,
+ c_has_mux_output_regs_a => 0,
+ c_has_mux_output_regs_b => 0,
+ c_has_regcea => 0,
+ c_has_regceb => 0,
+ c_has_rsta => 0,
+ c_has_rstb => 0,
+ c_has_softecc_input_regs_a => 0,
+ c_has_softecc_output_regs_b => 0,
+ c_init_file => "BlankString",
+ c_init_file_name => "no_coe_file_loaded",
+ c_inita_val => "0",
+ c_initb_val => "0",
+ c_interface_type => 0,
+ c_load_init_file => 0,
+ c_mem_type => 1,
+ c_mux_pipeline_stages => 0,
+ c_prim_type => 1,
+ c_read_depth_a => 2048,
+ c_read_depth_b => 2048,
+ c_read_width_a => 8,
+ c_read_width_b => 8,
+ c_rst_priority_a => "CE",
+ c_rst_priority_b => "CE",
+ c_rst_type => "SYNC",
+ c_rstram_a => 0,
+ c_rstram_b => 0,
+ c_sim_collision_check => "ALL",
+ c_use_bram_block => 0,
+ c_use_byte_wea => 0,
+ c_use_byte_web => 0,
+ c_use_default_data => 0,
+ c_use_ecc => 0,
+ c_use_softecc => 0,
+ c_wea_width => 1,
+ c_web_width => 1,
+ c_write_depth_a => 2048,
+ c_write_depth_b => 2048,
+ c_write_mode_a => "WRITE_FIRST",
+ c_write_mode_b => "WRITE_FIRST",
+ c_write_width_a => 8,
+ c_write_width_b => 8,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_SampleMemory
+ PORT MAP (
+ clka => clka,
+ wea => wea,
+ addra => addra,
+ dina => dina,
+ clkb => clkb,
+ addrb => addrb,
+ doutb => doutb
+ );
+-- synthesis translate_on
+
+END SampleMemory_a;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SinCos.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SinCos.gise
new file mode 100644
index 0000000..f561140
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SinCos.gise
@@ -0,0 +1,53 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
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+
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SinCos.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SinCos.vhd
new file mode 100644
index 0000000..77f6c2b
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SinCos.vhd
@@ -0,0 +1,106 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2020 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file SinCos.vhd when simulating
+-- the core, SinCos. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY SinCos IS
+ PORT (
+ clk : IN STD_LOGIC;
+ phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+ cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+ );
+END SinCos;
+
+ARCHITECTURE SinCos_a OF SinCos IS
+-- synthesis translate_off
+COMPONENT wrapped_SinCos
+ PORT (
+ clk : IN STD_LOGIC;
+ phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+ cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_SinCos USE ENTITY XilinxCoreLib.dds_compiler_v4_0(behavioral)
+ GENERIC MAP (
+ c_accumulator_width => 12,
+ c_amplitude => 0,
+ c_channels => 1,
+ c_has_ce => 0,
+ c_has_channel_index => 0,
+ c_has_phase_out => 0,
+ c_has_phasegen => 0,
+ c_has_rdy => 0,
+ c_has_rfd => 0,
+ c_has_sclr => 0,
+ c_has_sincos => 1,
+ c_latency => -1,
+ c_mem_type => 1,
+ c_negative_cosine => 0,
+ c_negative_sine => 0,
+ c_noise_shaping => 0,
+ c_optimise_goal => 0,
+ c_output_width => 16,
+ c_outputs_required => 2,
+ c_phase_angle_width => 12,
+ c_phase_increment => 2,
+ c_phase_increment_value => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
+ c_phase_offset => 0,
+ c_phase_offset_value => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
+ c_por_mode => 0,
+ c_use_dsp48 => 0,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_SinCos
+ PORT MAP (
+ clk => clk,
+ phase_in => phase_in,
+ cosine => cosine,
+ sine => sine
+ );
+-- synthesis translate_on
+
+END SinCos_a;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem.gise
new file mode 100644
index 0000000..faea9f1
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem.gise
@@ -0,0 +1,53 @@
+
+
+
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem.vhd
new file mode 100644
index 0000000..78c5afa
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem.vhd
@@ -0,0 +1,152 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2020 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file SweepConfigMem.vhd when simulating
+-- the core, SweepConfigMem. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY SweepConfigMem IS
+ PORT (
+ clka : IN STD_LOGIC;
+ ena : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
+ );
+END SweepConfigMem;
+
+ARCHITECTURE SweepConfigMem_a OF SweepConfigMem IS
+-- synthesis translate_off
+COMPONENT wrapped_SweepConfigMem
+ PORT (
+ clka : IN STD_LOGIC;
+ ena : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_SweepConfigMem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
+ GENERIC MAP (
+ c_addra_width => 13,
+ c_addrb_width => 13,
+ c_algorithm => 1,
+ c_axi_id_width => 4,
+ c_axi_slave_type => 0,
+ c_axi_type => 1,
+ c_byte_size => 9,
+ c_common_clk => 0,
+ c_default_data => "0",
+ c_disable_warn_bhv_coll => 0,
+ c_disable_warn_bhv_range => 0,
+ c_enable_32bit_address => 0,
+ c_family => "spartan6",
+ c_has_axi_id => 0,
+ c_has_ena => 1,
+ c_has_enb => 0,
+ c_has_injecterr => 0,
+ c_has_mem_output_regs_a => 0,
+ c_has_mem_output_regs_b => 0,
+ c_has_mux_output_regs_a => 0,
+ c_has_mux_output_regs_b => 0,
+ c_has_regcea => 0,
+ c_has_regceb => 0,
+ c_has_rsta => 0,
+ c_has_rstb => 0,
+ c_has_softecc_input_regs_a => 0,
+ c_has_softecc_output_regs_b => 0,
+ c_init_file => "BlankString",
+ c_init_file_name => "no_coe_file_loaded",
+ c_inita_val => "0",
+ c_initb_val => "0",
+ c_interface_type => 0,
+ c_load_init_file => 0,
+ c_mem_type => 1,
+ c_mux_pipeline_stages => 0,
+ c_prim_type => 1,
+ c_read_depth_a => 4501,
+ c_read_depth_b => 4501,
+ c_read_width_a => 96,
+ c_read_width_b => 96,
+ c_rst_priority_a => "CE",
+ c_rst_priority_b => "CE",
+ c_rst_type => "SYNC",
+ c_rstram_a => 0,
+ c_rstram_b => 0,
+ c_sim_collision_check => "ALL",
+ c_use_bram_block => 0,
+ c_use_byte_wea => 0,
+ c_use_byte_web => 0,
+ c_use_default_data => 0,
+ c_use_ecc => 0,
+ c_use_softecc => 0,
+ c_wea_width => 1,
+ c_web_width => 1,
+ c_write_depth_a => 4501,
+ c_write_depth_b => 4501,
+ c_write_mode_a => "WRITE_FIRST",
+ c_write_mode_b => "WRITE_FIRST",
+ c_write_width_a => 96,
+ c_write_width_b => 96,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_SweepConfigMem
+ PORT MAP (
+ clka => clka,
+ ena => ena,
+ wea => wea,
+ addra => addra,
+ dina => dina,
+ clkb => clkb,
+ addrb => addrb,
+ doutb => doutb
+ );
+-- synthesis translate_on
+
+END SweepConfigMem_a;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_exdes.ucf b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_exdes.ucf
new file mode 100644
index 0000000..3762632
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_exdes.ucf
@@ -0,0 +1,61 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Tx Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+NET "CLKA" TNM_NET = "CLKA";
+
+NET "CLKB" TNM_NET = "CLKB";
+
+TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ;
+
+TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ;
+
+################################################################################
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_exdes.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_exdes.vhd
new file mode 100644
index 0000000..e9cbba1
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_exdes.vhd
@@ -0,0 +1,182 @@
+
+
+
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7.1 Core - Top-level core wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: SweepConfigMem_exdes.vhd
+--
+-- Description:
+-- This is the actual BMG core wrapper.
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY SweepConfigMem_exdes IS
+ PORT (
+ --Inputs - Port A
+ ENA : IN STD_LOGIC; --opt port
+
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+
+ DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+
+ CLKA : IN STD_LOGIC;
+
+
+ --Inputs - Port B
+ ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
+ CLKB : IN STD_LOGIC
+
+ );
+
+END SweepConfigMem_exdes;
+
+
+ARCHITECTURE xilinx OF SweepConfigMem_exdes IS
+
+ COMPONENT BUFG IS
+ PORT (
+ I : IN STD_ULOGIC;
+ O : OUT STD_ULOGIC
+ );
+ END COMPONENT;
+
+ COMPONENT SweepConfigMem IS
+ PORT (
+ --Port A
+ ENA : IN STD_LOGIC; --opt port
+
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+
+ DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+
+
+ CLKA : IN STD_LOGIC;
+
+
+ --Port B
+ ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
+ CLKB : IN STD_LOGIC
+
+
+ );
+ END COMPONENT;
+
+ SIGNAL CLKA_buf : STD_LOGIC;
+ SIGNAL CLKB_buf : STD_LOGIC;
+ SIGNAL S_ACLK_buf : STD_LOGIC;
+
+BEGIN
+
+ bufg_A : BUFG
+ PORT MAP (
+ I => CLKA,
+ O => CLKA_buf
+ );
+
+ bufg_B : BUFG
+ PORT MAP (
+ I => CLKB,
+ O => CLKB_buf
+ );
+
+
+ bmg0 : SweepConfigMem
+ PORT MAP (
+ --Port A
+ ENA => ENA,
+
+ WEA => WEA,
+ ADDRA => ADDRA,
+
+ DINA => DINA,
+
+ CLKA => CLKA_buf,
+
+
+ --Port B
+ ADDRB => ADDRB,
+ DOUTB => DOUTB,
+ CLKB => CLKB_buf
+
+ );
+
+END xilinx;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_prod.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_prod.vhd
new file mode 100644
index 0000000..246b568
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_prod.vhd
@@ -0,0 +1,277 @@
+
+
+
+
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7.1 Core - Top-level wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--------------------------------------------------------------------------------
+--
+-- Filename: SweepConfigMem_prod.vhd
+--
+-- Description:
+-- This is the top-level BMG wrapper (over BMG core).
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+-- Configured Core Parameter Values:
+-- (Refer to the SIM Parameters table in the datasheet for more information on
+-- the these parameters.)
+-- C_FAMILY : spartan6
+-- C_XDEVICEFAMILY : spartan6
+-- C_INTERFACE_TYPE : 0
+-- C_ENABLE_32BIT_ADDRESS : 0
+-- C_AXI_TYPE : 1
+-- C_AXI_SLAVE_TYPE : 0
+-- C_AXI_ID_WIDTH : 4
+-- C_MEM_TYPE : 1
+-- C_BYTE_SIZE : 9
+-- C_ALGORITHM : 1
+-- C_PRIM_TYPE : 1
+-- C_LOAD_INIT_FILE : 0
+-- C_INIT_FILE_NAME : no_coe_file_loaded
+-- C_USE_DEFAULT_DATA : 0
+-- C_DEFAULT_DATA : 0
+-- C_RST_TYPE : SYNC
+-- C_HAS_RSTA : 0
+-- C_RST_PRIORITY_A : CE
+-- C_RSTRAM_A : 0
+-- C_INITA_VAL : 0
+-- C_HAS_ENA : 1
+-- C_HAS_REGCEA : 0
+-- C_USE_BYTE_WEA : 0
+-- C_WEA_WIDTH : 1
+-- C_WRITE_MODE_A : WRITE_FIRST
+-- C_WRITE_WIDTH_A : 96
+-- C_READ_WIDTH_A : 96
+-- C_WRITE_DEPTH_A : 4501
+-- C_READ_DEPTH_A : 4501
+-- C_ADDRA_WIDTH : 13
+-- C_HAS_RSTB : 0
+-- C_RST_PRIORITY_B : CE
+-- C_RSTRAM_B : 0
+-- C_INITB_VAL : 0
+-- C_HAS_ENB : 0
+-- C_HAS_REGCEB : 0
+-- C_USE_BYTE_WEB : 0
+-- C_WEB_WIDTH : 1
+-- C_WRITE_MODE_B : WRITE_FIRST
+-- C_WRITE_WIDTH_B : 96
+-- C_READ_WIDTH_B : 96
+-- C_WRITE_DEPTH_B : 4501
+-- C_READ_DEPTH_B : 4501
+-- C_ADDRB_WIDTH : 13
+-- C_HAS_MEM_OUTPUT_REGS_A : 0
+-- C_HAS_MEM_OUTPUT_REGS_B : 0
+-- C_HAS_MUX_OUTPUT_REGS_A : 0
+-- C_HAS_MUX_OUTPUT_REGS_B : 0
+-- C_HAS_SOFTECC_INPUT_REGS_A : 0
+-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
+-- C_MUX_PIPELINE_STAGES : 0
+-- C_USE_ECC : 0
+-- C_USE_SOFTECC : 0
+-- C_HAS_INJECTERR : 0
+-- C_SIM_COLLISION_CHECK : ALL
+-- C_COMMON_CLK : 0
+-- C_DISABLE_WARN_BHV_COLL : 0
+-- C_DISABLE_WARN_BHV_RANGE : 0
+
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY SweepConfigMem_prod IS
+ PORT (
+ --Port A
+ CLKA : IN STD_LOGIC;
+ RSTA : IN STD_LOGIC; --opt port
+ ENA : IN STD_LOGIC; --optional port
+ REGCEA : IN STD_LOGIC; --optional port
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+ DOUTA : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
+
+ --Port B
+ CLKB : IN STD_LOGIC;
+ RSTB : IN STD_LOGIC; --opt port
+ ENB : IN STD_LOGIC; --optional port
+ REGCEB : IN STD_LOGIC; --optional port
+ WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ DINB : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+ DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
+
+ --ECC
+ INJECTSBITERR : IN STD_LOGIC; --optional port
+ INJECTDBITERR : IN STD_LOGIC; --optional port
+ SBITERR : OUT STD_LOGIC; --optional port
+ DBITERR : OUT STD_LOGIC; --optional port
+ RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
+ -- AXI BMG Input and Output Port Declarations
+
+ -- AXI Global Signals
+ S_ACLK : IN STD_LOGIC;
+ S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ S_AXI_AWVALID : IN STD_LOGIC;
+ S_AXI_AWREADY : OUT STD_LOGIC;
+ S_AXI_WDATA : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+ S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ S_AXI_WLAST : IN STD_LOGIC;
+ S_AXI_WVALID : IN STD_LOGIC;
+ S_AXI_WREADY : OUT STD_LOGIC;
+ S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
+ S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ S_AXI_BVALID : OUT STD_LOGIC;
+ S_AXI_BREADY : IN STD_LOGIC;
+
+ -- AXI Full/Lite Slave Read (Write side)
+ S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ S_AXI_ARVALID : IN STD_LOGIC;
+ S_AXI_ARREADY : OUT STD_LOGIC;
+ S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
+ S_AXI_RDATA : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
+ S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ S_AXI_RLAST : OUT STD_LOGIC;
+ S_AXI_RVALID : OUT STD_LOGIC;
+ S_AXI_RREADY : IN STD_LOGIC;
+
+ -- AXI Full/Lite Sideband Signals
+ S_AXI_INJECTSBITERR : IN STD_LOGIC;
+ S_AXI_INJECTDBITERR : IN STD_LOGIC;
+ S_AXI_SBITERR : OUT STD_LOGIC;
+ S_AXI_DBITERR : OUT STD_LOGIC;
+ S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
+ S_ARESETN : IN STD_LOGIC
+
+
+ );
+
+END SweepConfigMem_prod;
+
+
+ARCHITECTURE xilinx OF SweepConfigMem_prod IS
+
+ COMPONENT SweepConfigMem_exdes IS
+ PORT (
+ --Port A
+ ENA : IN STD_LOGIC; --opt port
+
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+
+ DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+
+
+ CLKA : IN STD_LOGIC;
+
+
+ --Port B
+ ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
+ CLKB : IN STD_LOGIC
+
+
+
+ );
+ END COMPONENT;
+
+BEGIN
+
+ bmg0 : SweepConfigMem_exdes
+ PORT MAP (
+ --Port A
+ ENA => ENA,
+
+ WEA => WEA,
+ ADDRA => ADDRA,
+
+ DINA => DINA,
+
+ CLKA => CLKA,
+
+ --Port B
+ ADDRB => ADDRB,
+ DOUTB => DOUTB,
+ CLKB => CLKB
+
+
+
+ );
+END xilinx;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/SweepConfigMem_synth.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/SweepConfigMem_synth.vhd
new file mode 100644
index 0000000..9404e23
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/SweepConfigMem_synth.vhd
@@ -0,0 +1,329 @@
+
+
+
+
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: SweepConfigMem_synth.vhd
+--
+-- Description:
+-- Synthesizable Testbench
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY STD;
+USE STD.TEXTIO.ALL;
+
+--LIBRARY unisim;
+--USE unisim.vcomponents.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY SweepConfigMem_synth IS
+PORT(
+ CLK_IN : IN STD_LOGIC;
+ CLKB_IN : IN STD_LOGIC;
+ RESET_IN : IN STD_LOGIC;
+ STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
+ );
+END ENTITY;
+
+ARCHITECTURE SweepConfigMem_synth_ARCH OF SweepConfigMem_synth IS
+
+
+COMPONENT SweepConfigMem_exdes
+ PORT (
+ --Inputs - Port A
+ ENA : IN STD_LOGIC; --opt port
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+ CLKA : IN STD_LOGIC;
+
+ --Inputs - Port B
+ ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
+ CLKB : IN STD_LOGIC
+
+ );
+
+END COMPONENT;
+
+
+ SIGNAL CLKA: STD_LOGIC := '0';
+ SIGNAL RSTA: STD_LOGIC := '0';
+ SIGNAL ENA: STD_LOGIC := '0';
+ SIGNAL ENA_R: STD_LOGIC := '0';
+ SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DINA: STD_LOGIC_VECTOR(95 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DINA_R: STD_LOGIC_VECTOR(95 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL CLKB: STD_LOGIC := '0';
+ SIGNAL RSTB: STD_LOGIC := '0';
+ SIGNAL ADDRB: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ADDRB_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DOUTB: STD_LOGIC_VECTOR(95 DOWNTO 0);
+ SIGNAL CHECKER_EN : STD_LOGIC:='0';
+ SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
+ SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
+ SIGNAL clk_in_i: STD_LOGIC;
+
+ SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
+ SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
+ SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
+
+ SIGNAL clkb_in_i: STD_LOGIC;
+ SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
+ SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
+ SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
+ SIGNAL ITER_R0 : STD_LOGIC := '0';
+ SIGNAL ITER_R1 : STD_LOGIC := '0';
+ SIGNAL ITER_R2 : STD_LOGIC := '0';
+
+ SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+
+ BEGIN
+
+-- clk_buf: bufg
+-- PORT map(
+-- i => CLK_IN,
+-- o => clk_in_i
+-- );
+ clk_in_i <= CLK_IN;
+ CLKA <= clk_in_i;
+
+-- clkb_buf: bufg
+-- PORT map(
+-- i => CLKB_IN,
+-- o => clkb_in_i
+-- );
+ clkb_in_i <= CLKB_IN;
+ CLKB <= clkb_in_i;
+ RSTA <= RESET_SYNC_R3 AFTER 50 ns;
+
+
+ PROCESS(clk_in_i)
+ BEGIN
+ IF(RISING_EDGE(clk_in_i)) THEN
+ RESET_SYNC_R1 <= RESET_IN;
+ RESET_SYNC_R2 <= RESET_SYNC_R1;
+ RESET_SYNC_R3 <= RESET_SYNC_R2;
+ END IF;
+ END PROCESS;
+
+ RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
+
+ PROCESS(clkb_in_i)
+ BEGIN
+ IF(RISING_EDGE(clkb_in_i)) THEN
+ RESETB_SYNC_R1 <= RESET_IN;
+ RESETB_SYNC_R2 <= RESETB_SYNC_R1;
+ RESETB_SYNC_R3 <= RESETB_SYNC_R2;
+ END IF;
+ END PROCESS;
+
+PROCESS(CLKA)
+BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ ISSUE_FLAG_STATUS<= (OTHERS => '0');
+ ELSE
+ ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
+ END IF;
+ END IF;
+END PROCESS;
+
+STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
+
+
+
+
+ BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
+ GENERIC MAP (
+ WRITE_WIDTH => 96,
+ READ_WIDTH => 96 )
+ PORT MAP (
+ CLK => clkb_in_i,
+ RST => RSTB,
+ EN => CHECKER_EN_R,
+ DATA_IN => DOUTB,
+ STATUS => ISSUE_FLAG(0)
+ );
+
+ PROCESS(clkb_in_i)
+ BEGIN
+ IF(RISING_EDGE(clkb_in_i)) THEN
+ IF(RSTB='1') THEN
+ CHECKER_EN_R <= '0';
+ ELSE
+ CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
+ PORT MAP(
+ CLKA => clk_in_i,
+ CLKB => clkb_in_i,
+ TB_RST => RSTA,
+ ADDRA => ADDRA,
+ DINA => DINA,
+ ENA => ENA,
+ WEA => WEA,
+ ADDRB => ADDRB,
+ CHECK_DATA => CHECKER_EN
+ );
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ STATUS(8) <= '0';
+ iter_r2 <= '0';
+ iter_r1 <= '0';
+ iter_r0 <= '0';
+ ELSE
+ STATUS(8) <= iter_r2;
+ iter_r2 <= iter_r1;
+ iter_r1 <= iter_r0;
+ iter_r0 <= STIMULUS_FLOW(8);
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ STIMULUS_FLOW <= (OTHERS => '0');
+ ELSIF(WEA(0)='1') THEN
+ STIMULUS_FLOW <= STIMULUS_FLOW+1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ ENA_R <= '0' AFTER 50 ns;
+ WEA_R <= (OTHERS=>'0') AFTER 50 ns;
+ DINA_R <= (OTHERS=>'0') AFTER 50 ns;
+
+
+ ELSE
+ ENA_R <= ENA AFTER 50 ns;
+ WEA_R <= WEA AFTER 50 ns;
+ DINA_R <= DINA AFTER 50 ns;
+
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
+ ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
+ ELSE
+ ADDRA_R <= ADDRA AFTER 50 ns;
+ ADDRB_R <= ADDRB AFTER 50 ns;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ BMG_PORT: SweepConfigMem_exdes PORT MAP (
+ --Port A
+ ENA => ENA_R,
+ WEA => WEA_R,
+ ADDRA => ADDRA_R,
+ DINA => DINA_R,
+ CLKA => CLKA,
+ --Port B
+ ADDRB => ADDRB_R,
+ DOUTB => DOUTB,
+ CLKB => CLKB
+
+ );
+END ARCHITECTURE;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/SweepConfigMem_tb.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/SweepConfigMem_tb.vhd
new file mode 100644
index 0000000..2b09608
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/SweepConfigMem_tb.vhd
@@ -0,0 +1,142 @@
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+-- Filename: SweepConfigMem_tb.vhd
+-- Description:
+-- Testbench Top
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY SweepConfigMem_tb IS
+END ENTITY;
+
+
+ARCHITECTURE SweepConfigMem_tb_ARCH OF SweepConfigMem_tb IS
+ SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
+ SIGNAL CLK : STD_LOGIC := '1';
+ SIGNAL CLKB : STD_LOGIC := '1';
+ SIGNAL RESET : STD_LOGIC;
+
+ BEGIN
+
+
+ CLK_GEN: PROCESS BEGIN
+ CLK <= NOT CLK;
+ WAIT FOR 100 NS;
+ CLK <= NOT CLK;
+ WAIT FOR 100 NS;
+ END PROCESS;
+ CLKB_GEN: PROCESS BEGIN
+ CLKB <= NOT CLKB;
+ WAIT FOR 100 NS;
+ CLKB <= NOT CLKB;
+ WAIT FOR 100 NS;
+ END PROCESS;
+
+ RST_GEN: PROCESS BEGIN
+ RESET <= '1';
+ WAIT FOR 1000 NS;
+ RESET <= '0';
+ WAIT;
+ END PROCESS;
+
+
+--STOP_SIM: PROCESS BEGIN
+-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
+-- ASSERT FALSE
+-- REPORT "END SIMULATION TIME REACHED"
+-- SEVERITY FAILURE;
+--END PROCESS;
+--
+PROCESS BEGIN
+ WAIT UNTIL STATUS(8)='1';
+ IF( STATUS(7 downto 0)/="0") THEN
+ ASSERT false
+ REPORT "Test Completed Successfully"
+ SEVERITY NOTE;
+ REPORT "Simulation Failed"
+ SEVERITY FAILURE;
+ ELSE
+ ASSERT false
+ REPORT "TEST PASS"
+ SEVERITY NOTE;
+ REPORT "Test Completed Successfully"
+ SEVERITY FAILURE;
+ END IF;
+
+END PROCESS;
+
+ SweepConfigMem_synth_inst:ENTITY work.SweepConfigMem_synth
+ PORT MAP(
+ CLK_IN => CLK,
+ CLKB_IN => CLK,
+ RESET_IN => RESET,
+ STATUS => STATUS
+ );
+
+END ARCHITECTURE;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/addr_gen.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/addr_gen.vhd
new file mode 100644
index 0000000..62706ca
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/addr_gen.vhd
@@ -0,0 +1,117 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Address Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: addr_gen.vhd
+--
+-- Description:
+-- Address Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY ADDR_GEN IS
+ GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
+ RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
+ RST_INC : INTEGER := 0);
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ LOAD :IN STD_LOGIC;
+ LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
+ ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
+ );
+END ADDR_GEN;
+
+ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
+ SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
+BEGIN
+ ADDR_OUT <= ADDR_TEMP;
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST='1') THEN
+ ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
+ ELSE
+ IF(EN='1') THEN
+ IF(LOAD='1') THEN
+ ADDR_TEMP <=LOAD_VALUE;
+ ELSE
+ IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
+ ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
+ ELSE
+ ADDR_TEMP <= ADDR_TEMP + '1';
+ END IF;
+ END IF;
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+END ARCHITECTURE;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/bmg_stim_gen.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/bmg_stim_gen.vhd
new file mode 100644
index 0000000..461f496
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/bmg_stim_gen.vhd
@@ -0,0 +1,436 @@
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_stim_gen.vhd
+--
+-- Description:
+-- Stimulus Generation For SDP Configuration
+-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
+-- simulation ends
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+ LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY REGISTER_LOGIC IS
+ PORT(
+ Q : OUT STD_LOGIC;
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ D : IN STD_LOGIC
+ );
+END REGISTER_LOGIC;
+
+ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
+SIGNAL Q_O : STD_LOGIC :='0';
+BEGIN
+ Q <= Q_O;
+ FF_BEH: PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST ='1') THEN
+ Q_O <= '0';
+ ELSE
+ Q_O <= D;
+ END IF;
+ END IF;
+ END PROCESS;
+END REGISTER_ARCH;
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY BMG_STIM_GEN IS
+ PORT (
+ CLKA : IN STD_LOGIC;
+ CLKB : IN STD_LOGIC;
+ TB_RST : IN STD_LOGIC;
+ ADDRA: OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
+ DINA : OUT STD_LOGIC_VECTOR(95 DOWNTO 0) := (OTHERS => '0');
+ ENA : OUT STD_LOGIC :='0';
+ WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
+ ADDRB: OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
+ CHECK_DATA: OUT STD_LOGIC:='0'
+ );
+END BMG_STIM_GEN;
+
+
+ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
+
+CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+SIGNAL DINA_INT : STD_LOGIC_VECTOR(95 DOWNTO 0) := (OTHERS => '0');
+SIGNAL DO_WRITE : STD_LOGIC := '0';
+SIGNAL DO_READ : STD_LOGIC := '0';
+SIGNAL DO_READ_R : STD_LOGIC := '0';
+SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
+SIGNAL PORTA_WR : STD_LOGIC:='0';
+SIGNAL COUNT : INTEGER :=0;
+SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
+SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
+SIGNAL PORTB_RD : STD_LOGIC:='0';
+SIGNAL COUNT_RD : INTEGER :=0;
+SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
+SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
+SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
+SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
+SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
+SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
+SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
+SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
+SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
+SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
+SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
+SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
+SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
+SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
+
+CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
+CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((13 <= 13),WR_RD_DEEP_COUNT,
+ ((96/96)*WR_RD_DEEP_COUNT));
+CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((13 <= 13),WR_RD_DEEP_COUNT,
+ ((96/96)*WR_RD_DEEP_COUNT));
+
+BEGIN
+
+ ADDRA <= WRITE_ADDR(12 DOWNTO 0) ;
+ DINA <= DINA_INT ;
+ ADDRB <= READ_ADDR(12 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
+ CHECK_DATA <= DO_READ;
+
+ RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+ GENERIC MAP(
+ C_MAX_DEPTH => 4501 ,
+ RST_INC => 1 )
+ PORT MAP(
+ CLK => CLKB,
+ RST => TB_RST,
+ EN => DO_READ,
+ LOAD => '0',
+ LOAD_VALUE => ZERO,
+ ADDR_OUT => READ_ADDR
+ );
+
+ WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+ GENERIC MAP(
+ C_MAX_DEPTH => 4501,
+ RST_INC => 1 )
+ PORT MAP(
+ CLK => CLKA,
+ RST => TB_RST,
+ EN => DO_WRITE,
+ LOAD => '0',
+ LOAD_VALUE => ZERO,
+ ADDR_OUT => WRITE_ADDR
+ );
+
+ WR_DATA_GEN_INST:ENTITY work.DATA_GEN
+ GENERIC MAP (
+ DATA_GEN_WIDTH => 96,
+ DOUT_WIDTH => 96 ,
+ DATA_PART_CNT => 1,
+ SEED => 2)
+ PORT MAP (
+ CLK => CLKA,
+ RST => TB_RST,
+ EN => DO_WRITE,
+ DATA_OUT => DINA_INT
+ );
+
+
+ PORTA_WR_PROCESS: PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(TB_RST='1') THEN
+ PORTA_WR<='1';
+ ELSE
+ PORTA_WR<=PORTB_RD_COMPLETE;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PORTB_RD_PROCESS: PROCESS(CLKB)
+ BEGIN
+ IF(RISING_EDGE(CLKB)) THEN
+ IF(TB_RST='1') THEN
+ PORTB_RD<='0';
+ ELSE
+ PORTB_RD<=PORTA_WR_L2;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
+ BEGIN
+ IF(RISING_EDGE(CLKB)) THEN
+ IF(TB_RST='1') THEN
+ LATCH_PORTB_RD_COMPLETE<='0';
+ ELSIF(PORTB_RD_COMPLETE='1') THEN
+ LATCH_PORTB_RD_COMPLETE <='1';
+ ELSIF(PORTA_WR_HAPPENED='1') THEN
+ LATCH_PORTB_RD_COMPLETE<='0';
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(TB_RST='1') THEN
+ PORTB_RD_L1 <='0';
+ PORTB_RD_L2 <='0';
+ ELSE
+ PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
+ PORTB_RD_L2 <= PORTB_RD_L1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PROCESS(CLKB)
+ BEGIN
+ IF(RISING_EDGE(CLKB)) THEN
+ IF(TB_RST='1') THEN
+ PORTA_WR_R1 <='0';
+ PORTA_WR_R2 <='0';
+ ELSE
+ PORTA_WR_R1 <= PORTA_WR;
+ PORTA_WR_R2 <= PORTA_WR_R1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PORTA_WR_HAPPENED <= PORTA_WR_R2;
+
+ PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(TB_RST='1') THEN
+ LATCH_PORTA_WR_COMPLETE<='0';
+ ELSIF(PORTA_WR_COMPLETE='1') THEN
+ LATCH_PORTA_WR_COMPLETE <='1';
+ --ELSIF(PORTB_RD_HAPPENED='1') THEN
+ ELSE
+ LATCH_PORTA_WR_COMPLETE<='0';
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PROCESS(CLKB)
+ BEGIN
+ IF(RISING_EDGE(CLKB)) THEN
+ IF(TB_RST='1') THEN
+ PORTA_WR_L1 <='0';
+ PORTA_WR_L2 <='0';
+ ELSE
+ PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
+ PORTA_WR_L2 <= PORTA_WR_L1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(TB_RST='1') THEN
+ PORTB_RD_R1 <='0';
+ PORTB_RD_R2 <='0';
+ ELSE
+ PORTB_RD_R1 <= PORTB_RD;
+ PORTB_RD_R2 <= PORTB_RD_R1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PORTB_RD_HAPPENED <= PORTB_RD_R2;
+
+ PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
+
+ start_rd_counter: process(clkb)
+ begin
+ if(rising_edge(clkb)) then
+ if(tb_rst='1') then
+ incr_rd_cnt <= '0';
+ elsif(portb_rd ='1') then
+ incr_rd_cnt <='1';
+ elsif(portb_rd_complete='1') then
+ incr_rd_cnt <='0';
+ end if;
+ end if;
+ end process;
+
+ RD_COUNTER: process(clkb)
+ begin
+ if(rising_edge(clkb)) then
+ if(tb_rst='1') then
+ count_rd <= 0;
+ elsif(incr_rd_cnt='1') then
+ count_rd<=count_rd+1;
+ end if;
+ --if(count_rd=(wr_rd_deep_count)) then
+ if(count_rd=(RD_DEEP_COUNT)) then
+ count_rd<=0;
+ end if;
+ end if;
+ end process;
+
+ DO_READ<='1' when (count_rd DO_READ_REG(0),
+ CLK => CLKB,
+ RST => TB_RST,
+ D => DO_READ
+ );
+ END GENERATE DFF_RIGHT;
+
+ DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
+ BEGIN
+ SHIFT_INST: ENTITY work.REGISTER_LOGIC
+ PORT MAP(
+ Q => DO_READ_REG(I),
+ CLK =>CLKB,
+ RST =>TB_RST,
+ D =>DO_READ_REG(I-1)
+ );
+ END GENERATE DFF_OTHERS;
+ END GENERATE BEGIN_SHIFT_REG;
+
+ REGCE_PROCESS: PROCESS(CLKB)
+ BEGIN
+ IF(RISING_EDGE(CLKB)) THEN
+ IF(TB_RST='1') THEN
+ DO_READ_R <= '0';
+ ELSE
+ DO_READ_R <= DO_READ;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ ENA <= DO_WRITE ;
+
+ WEA(0) <= DO_WRITE ;
+
+
+END ARCHITECTURE;
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/bmg_tb_pkg.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/bmg_tb_pkg.vhd
new file mode 100644
index 0000000..4928909
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/bmg_tb_pkg.vhd
@@ -0,0 +1,200 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Testbench Package
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_tb_pkg.vhd
+--
+-- Description:
+-- BMG Testbench Package files
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+PACKAGE BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+ DATA_VALUE : INTEGER;
+ DIVISOR : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC_VECTOR;
+ FALSE_CASE : STD_LOGIC_VECTOR)
+ RETURN STD_LOGIC_VECTOR;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STRING;
+ FALSE_CASE :STRING)
+ RETURN STRING;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC;
+ FALSE_CASE :STD_LOGIC)
+ RETURN STD_LOGIC;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : INTEGER;
+ FALSE_CASE : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION LOG2ROUNDUP (
+ DATA_VALUE : INTEGER)
+ RETURN INTEGER;
+
+END BMG_TB_PKG;
+
+PACKAGE BODY BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+ DATA_VALUE : INTEGER;
+ DIVISOR : INTEGER)
+ RETURN INTEGER IS
+ VARIABLE DIV : INTEGER;
+ BEGIN
+ DIV := DATA_VALUE/DIVISOR;
+ IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
+ DIV := DIV+1;
+ END IF;
+ RETURN DIV;
+ END DIVROUNDUP;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC_VECTOR;
+ FALSE_CASE : STD_LOGIC_VECTOR)
+ RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ IF NOT CONDITION THEN
+ RETURN FALSE_CASE;
+ ELSE
+ RETURN TRUE_CASE;
+ END IF;
+ END IF_THEN_ELSE;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC;
+ FALSE_CASE : STD_LOGIC)
+ RETURN STD_LOGIC IS
+ BEGIN
+ IF NOT CONDITION THEN
+ RETURN FALSE_CASE;
+ ELSE
+ RETURN TRUE_CASE;
+ END IF;
+ END IF_THEN_ELSE;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : INTEGER;
+ FALSE_CASE : INTEGER)
+ RETURN INTEGER IS
+ VARIABLE RETVAL : INTEGER := 0;
+ BEGIN
+ IF CONDITION=FALSE THEN
+ RETVAL:=FALSE_CASE;
+ ELSE
+ RETVAL:=TRUE_CASE;
+ END IF;
+ RETURN RETVAL;
+ END IF_THEN_ELSE;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STRING;
+ FALSE_CASE : STRING)
+ RETURN STRING IS
+ BEGIN
+ IF NOT CONDITION THEN
+ RETURN FALSE_CASE;
+ ELSE
+ RETURN TRUE_CASE;
+ END IF;
+ END IF_THEN_ELSE;
+ -------------------------------
+ FUNCTION LOG2ROUNDUP (
+ DATA_VALUE : INTEGER)
+ RETURN INTEGER IS
+ VARIABLE WIDTH : INTEGER := 0;
+ VARIABLE CNT : INTEGER := 1;
+ BEGIN
+ IF (DATA_VALUE <= 1) THEN
+ WIDTH := 1;
+ ELSE
+ WHILE (CNT < DATA_VALUE) LOOP
+ WIDTH := WIDTH + 1;
+ CNT := CNT *2;
+ END LOOP;
+ END IF;
+ RETURN WIDTH;
+ END LOG2ROUNDUP;
+
+END BMG_TB_PKG;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/checker.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/checker.vhd
new file mode 100644
index 0000000..15a2753
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/checker.vhd
@@ -0,0 +1,161 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Checker
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: checker.vhd
+--
+-- Description:
+-- Checker
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY CHECKER IS
+ GENERIC ( WRITE_WIDTH : INTEGER :=32;
+ READ_WIDTH : INTEGER :=32
+ );
+
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
+ STATUS : OUT STD_LOGIC:= '0'
+ );
+END CHECKER;
+
+ARCHITECTURE CHECKER_ARCH OF CHECKER IS
+ SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
+ SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
+ SIGNAL EN_R : STD_LOGIC := '0';
+ SIGNAL EN_2R : STD_LOGIC := '0';
+--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
+--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
+--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
+ CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
+ CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
+ SIGNAL ERR_HOLD : STD_LOGIC :='0';
+ SIGNAL ERR_DET : STD_LOGIC :='0';
+BEGIN
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST= '1') THEN
+ EN_R <= '0';
+ EN_2R <= '0';
+ DATA_IN_R <= (OTHERS=>'0');
+ ELSE
+ EN_R <= EN;
+ EN_2R <= EN_R;
+ DATA_IN_R <= DATA_IN;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
+ GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
+ DOUT_WIDTH => READ_WIDTH,
+ DATA_PART_CNT => DATA_PART_CNT,
+ SEED => 2
+ )
+ PORT MAP (
+ CLK => CLK,
+ RST => RST,
+ EN => EN_2R,
+ DATA_OUT => EXPECTED_DATA
+ );
+
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(EN_2R='1') THEN
+ IF(EXPECTED_DATA = DATA_IN_R) THEN
+ ERR_DET<='0';
+ ELSE
+ ERR_DET<= '1';
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PROCESS(CLK,RST)
+ BEGIN
+ IF(RST='1') THEN
+ ERR_HOLD <= '0';
+ ELSIF(RISING_EDGE(CLK)) THEN
+ ERR_HOLD <= ERR_HOLD OR ERR_DET ;
+ END IF;
+ END PROCESS;
+
+ STATUS <= ERR_HOLD;
+
+END ARCHITECTURE;
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/data_gen.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/data_gen.vhd
new file mode 100644
index 0000000..fe3dca7
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/data_gen.vhd
@@ -0,0 +1,140 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Data Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: data_gen.vhd
+--
+-- Description:
+-- Data Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY DATA_GEN IS
+ GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
+ DOUT_WIDTH : INTEGER := 32;
+ DATA_PART_CNT : INTEGER := 1;
+ SEED : INTEGER := 2
+ );
+
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
+ );
+END DATA_GEN;
+
+ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
+ CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
+ SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
+ SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
+ SIGNAL LOCAL_CNT : INTEGER :=1;
+ SIGNAL DATA_GEN_I : STD_LOGIC :='0';
+BEGIN
+
+ LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
+ DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
+ DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
+
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE (CLK)) THEN
+ IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
+ LOCAL_CNT <=1;
+ ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
+ IF(LOCAL_CNT = 1) THEN
+ LOCAL_CNT <= LOCAL_CNT+1;
+ ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
+ LOCAL_CNT <= LOCAL_CNT+1;
+ ELSE
+ LOCAL_CNT <= 1;
+ END IF;
+ ELSE
+ LOCAL_CNT <= 1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
+ RAND_GEN_INST:ENTITY work.RANDOM
+ GENERIC MAP(
+ WIDTH => 8,
+ SEED => (SEED+N)
+ )
+ PORT MAP(
+ CLK => CLK,
+ RST => RST,
+ EN => DATA_GEN_I,
+ RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
+ );
+ END GENERATE RAND_GEN;
+
+END ARCHITECTURE;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/random.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/random.vhd
new file mode 100644
index 0000000..b0d417c
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/random.vhd
@@ -0,0 +1,112 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Random Number Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: random.vhd
+--
+-- Description:
+-- Random Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+ENTITY RANDOM IS
+ GENERIC ( WIDTH : INTEGER := 32;
+ SEED : INTEGER :=2
+ );
+
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
+ );
+END RANDOM;
+
+ARCHITECTURE BEHAVIORAL OF RANDOM IS
+BEGIN
+ PROCESS(CLK)
+ VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+ VARIABLE TEMP : STD_LOGIC := '0';
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST='1') THEN
+ RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+ ELSE
+ IF(EN = '1') THEN
+ TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
+ RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
+ RAND_TEMP(0) := TEMP;
+ END IF;
+ END IF;
+ END IF;
+ RANDOM_NUM <= RAND_TEMP;
+ END PROCESS;
+END ARCHITECTURE;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/VCO_Mem.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/VCO_Mem.gise
new file mode 100644
index 0000000..f48f6b8
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/VCO_Mem.gise
@@ -0,0 +1,53 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/VCO_Mem.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/VCO_Mem.vhd
new file mode 100644
index 0000000..007952b
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/VCO_Mem.vhd
@@ -0,0 +1,149 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2022 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file VCO_Mem.vhd when simulating
+-- the core, VCO_Mem. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY VCO_Mem IS
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+ );
+END VCO_Mem;
+
+ARCHITECTURE VCO_Mem_a OF VCO_Mem IS
+-- synthesis translate_off
+COMPONENT wrapped_VCO_Mem
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_VCO_Mem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
+ GENERIC MAP (
+ c_addra_width => 6,
+ c_addrb_width => 6,
+ c_algorithm => 1,
+ c_axi_id_width => 4,
+ c_axi_slave_type => 0,
+ c_axi_type => 1,
+ c_byte_size => 9,
+ c_common_clk => 0,
+ c_default_data => "0",
+ c_disable_warn_bhv_coll => 0,
+ c_disable_warn_bhv_range => 0,
+ c_enable_32bit_address => 0,
+ c_family => "spartan6",
+ c_has_axi_id => 0,
+ c_has_ena => 0,
+ c_has_enb => 0,
+ c_has_injecterr => 0,
+ c_has_mem_output_regs_a => 0,
+ c_has_mem_output_regs_b => 0,
+ c_has_mux_output_regs_a => 0,
+ c_has_mux_output_regs_b => 0,
+ c_has_regcea => 0,
+ c_has_regceb => 0,
+ c_has_rsta => 0,
+ c_has_rstb => 0,
+ c_has_softecc_input_regs_a => 0,
+ c_has_softecc_output_regs_b => 0,
+ c_init_file => "BlankString",
+ c_init_file_name => "no_coe_file_loaded",
+ c_inita_val => "0",
+ c_initb_val => "0",
+ c_interface_type => 0,
+ c_load_init_file => 0,
+ c_mem_type => 1,
+ c_mux_pipeline_stages => 0,
+ c_prim_type => 1,
+ c_read_depth_a => 64,
+ c_read_depth_b => 64,
+ c_read_width_a => 16,
+ c_read_width_b => 16,
+ c_rst_priority_a => "CE",
+ c_rst_priority_b => "CE",
+ c_rst_type => "SYNC",
+ c_rstram_a => 0,
+ c_rstram_b => 0,
+ c_sim_collision_check => "ALL",
+ c_use_bram_block => 0,
+ c_use_byte_wea => 0,
+ c_use_byte_web => 0,
+ c_use_default_data => 0,
+ c_use_ecc => 0,
+ c_use_softecc => 0,
+ c_wea_width => 1,
+ c_web_width => 1,
+ c_write_depth_a => 64,
+ c_write_depth_b => 64,
+ c_write_mode_a => "WRITE_FIRST",
+ c_write_mode_b => "WRITE_FIRST",
+ c_write_width_a => 16,
+ c_write_width_b => 16,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_VCO_Mem
+ PORT MAP (
+ clka => clka,
+ wea => wea,
+ addra => addra,
+ dina => dina,
+ clkb => clkb,
+ addrb => addrb,
+ doutb => doutb
+ );
+-- synthesis translate_on
+
+END VCO_Mem_a;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram.gise
new file mode 100644
index 0000000..68f663b
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram.gise
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram.vhd
new file mode 100644
index 0000000..1aa01e9
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram.vhd
@@ -0,0 +1,149 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2020 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file result_bram.vhd when simulating
+-- the core, result_bram. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY result_bram IS
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(191 DOWNTO 0)
+ );
+END result_bram;
+
+ARCHITECTURE result_bram_a OF result_bram IS
+-- synthesis translate_off
+COMPONENT wrapped_result_bram
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(191 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_result_bram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
+ GENERIC MAP (
+ c_addra_width => 8,
+ c_addrb_width => 8,
+ c_algorithm => 1,
+ c_axi_id_width => 4,
+ c_axi_slave_type => 0,
+ c_axi_type => 1,
+ c_byte_size => 9,
+ c_common_clk => 0,
+ c_default_data => "0",
+ c_disable_warn_bhv_coll => 0,
+ c_disable_warn_bhv_range => 0,
+ c_enable_32bit_address => 0,
+ c_family => "spartan6",
+ c_has_axi_id => 0,
+ c_has_ena => 0,
+ c_has_enb => 0,
+ c_has_injecterr => 0,
+ c_has_mem_output_regs_a => 0,
+ c_has_mem_output_regs_b => 0,
+ c_has_mux_output_regs_a => 0,
+ c_has_mux_output_regs_b => 0,
+ c_has_regcea => 0,
+ c_has_regceb => 0,
+ c_has_rsta => 0,
+ c_has_rstb => 0,
+ c_has_softecc_input_regs_a => 0,
+ c_has_softecc_output_regs_b => 0,
+ c_init_file => "BlankString",
+ c_init_file_name => "no_coe_file_loaded",
+ c_inita_val => "0",
+ c_initb_val => "0",
+ c_interface_type => 0,
+ c_load_init_file => 0,
+ c_mem_type => 1,
+ c_mux_pipeline_stages => 0,
+ c_prim_type => 1,
+ c_read_depth_a => 256,
+ c_read_depth_b => 256,
+ c_read_width_a => 192,
+ c_read_width_b => 192,
+ c_rst_priority_a => "CE",
+ c_rst_priority_b => "CE",
+ c_rst_type => "SYNC",
+ c_rstram_a => 0,
+ c_rstram_b => 0,
+ c_sim_collision_check => "ALL",
+ c_use_bram_block => 0,
+ c_use_byte_wea => 0,
+ c_use_byte_web => 0,
+ c_use_default_data => 0,
+ c_use_ecc => 0,
+ c_use_softecc => 0,
+ c_wea_width => 1,
+ c_web_width => 1,
+ c_write_depth_a => 256,
+ c_write_depth_b => 256,
+ c_write_mode_a => "WRITE_FIRST",
+ c_write_mode_b => "WRITE_FIRST",
+ c_write_width_a => 192,
+ c_write_width_b => 192,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_result_bram
+ PORT MAP (
+ clka => clka,
+ wea => wea,
+ addra => addra,
+ dina => dina,
+ clkb => clkb,
+ addrb => addrb,
+ doutb => doutb
+ );
+-- synthesis translate_on
+
+END result_bram_a;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_exdes.ucf b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_exdes.ucf
new file mode 100644
index 0000000..3762632
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_exdes.ucf
@@ -0,0 +1,61 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Tx Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+NET "CLKA" TNM_NET = "CLKA";
+
+NET "CLKB" TNM_NET = "CLKB";
+
+TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ;
+
+TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ;
+
+################################################################################
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_exdes.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_exdes.vhd
new file mode 100644
index 0000000..8e416e0
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_exdes.vhd
@@ -0,0 +1,179 @@
+
+
+
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7.1 Core - Top-level core wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: result_bram_exdes.vhd
+--
+-- Description:
+-- This is the actual BMG core wrapper.
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY result_bram_exdes IS
+ PORT (
+ --Inputs - Port A
+
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+ DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
+
+ CLKA : IN STD_LOGIC;
+
+
+ --Inputs - Port B
+ ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
+ CLKB : IN STD_LOGIC
+
+ );
+
+END result_bram_exdes;
+
+
+ARCHITECTURE xilinx OF result_bram_exdes IS
+
+ COMPONENT BUFG IS
+ PORT (
+ I : IN STD_ULOGIC;
+ O : OUT STD_ULOGIC
+ );
+ END COMPONENT;
+
+ COMPONENT result_bram IS
+ PORT (
+ --Port A
+
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+ DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
+
+
+ CLKA : IN STD_LOGIC;
+
+
+ --Port B
+ ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
+ CLKB : IN STD_LOGIC
+
+
+ );
+ END COMPONENT;
+
+ SIGNAL CLKA_buf : STD_LOGIC;
+ SIGNAL CLKB_buf : STD_LOGIC;
+ SIGNAL S_ACLK_buf : STD_LOGIC;
+
+BEGIN
+
+ bufg_A : BUFG
+ PORT MAP (
+ I => CLKA,
+ O => CLKA_buf
+ );
+
+ bufg_B : BUFG
+ PORT MAP (
+ I => CLKB,
+ O => CLKB_buf
+ );
+
+
+ bmg0 : result_bram
+ PORT MAP (
+ --Port A
+
+ WEA => WEA,
+ ADDRA => ADDRA,
+
+ DINA => DINA,
+
+ CLKA => CLKA_buf,
+
+
+ --Port B
+ ADDRB => ADDRB,
+ DOUTB => DOUTB,
+ CLKB => CLKB_buf
+
+ );
+
+END xilinx;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_prod.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_prod.vhd
new file mode 100644
index 0000000..6728031
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_prod.vhd
@@ -0,0 +1,275 @@
+
+
+
+
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7.1 Core - Top-level wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--------------------------------------------------------------------------------
+--
+-- Filename: result_bram_prod.vhd
+--
+-- Description:
+-- This is the top-level BMG wrapper (over BMG core).
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+-- Configured Core Parameter Values:
+-- (Refer to the SIM Parameters table in the datasheet for more information on
+-- the these parameters.)
+-- C_FAMILY : spartan6
+-- C_XDEVICEFAMILY : spartan6
+-- C_INTERFACE_TYPE : 0
+-- C_ENABLE_32BIT_ADDRESS : 0
+-- C_AXI_TYPE : 1
+-- C_AXI_SLAVE_TYPE : 0
+-- C_AXI_ID_WIDTH : 4
+-- C_MEM_TYPE : 1
+-- C_BYTE_SIZE : 9
+-- C_ALGORITHM : 1
+-- C_PRIM_TYPE : 1
+-- C_LOAD_INIT_FILE : 0
+-- C_INIT_FILE_NAME : no_coe_file_loaded
+-- C_USE_DEFAULT_DATA : 0
+-- C_DEFAULT_DATA : 0
+-- C_RST_TYPE : SYNC
+-- C_HAS_RSTA : 0
+-- C_RST_PRIORITY_A : CE
+-- C_RSTRAM_A : 0
+-- C_INITA_VAL : 0
+-- C_HAS_ENA : 0
+-- C_HAS_REGCEA : 0
+-- C_USE_BYTE_WEA : 0
+-- C_WEA_WIDTH : 1
+-- C_WRITE_MODE_A : WRITE_FIRST
+-- C_WRITE_WIDTH_A : 192
+-- C_READ_WIDTH_A : 192
+-- C_WRITE_DEPTH_A : 256
+-- C_READ_DEPTH_A : 256
+-- C_ADDRA_WIDTH : 8
+-- C_HAS_RSTB : 0
+-- C_RST_PRIORITY_B : CE
+-- C_RSTRAM_B : 0
+-- C_INITB_VAL : 0
+-- C_HAS_ENB : 0
+-- C_HAS_REGCEB : 0
+-- C_USE_BYTE_WEB : 0
+-- C_WEB_WIDTH : 1
+-- C_WRITE_MODE_B : WRITE_FIRST
+-- C_WRITE_WIDTH_B : 192
+-- C_READ_WIDTH_B : 192
+-- C_WRITE_DEPTH_B : 256
+-- C_READ_DEPTH_B : 256
+-- C_ADDRB_WIDTH : 8
+-- C_HAS_MEM_OUTPUT_REGS_A : 0
+-- C_HAS_MEM_OUTPUT_REGS_B : 0
+-- C_HAS_MUX_OUTPUT_REGS_A : 0
+-- C_HAS_MUX_OUTPUT_REGS_B : 0
+-- C_HAS_SOFTECC_INPUT_REGS_A : 0
+-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
+-- C_MUX_PIPELINE_STAGES : 0
+-- C_USE_ECC : 0
+-- C_USE_SOFTECC : 0
+-- C_HAS_INJECTERR : 0
+-- C_SIM_COLLISION_CHECK : ALL
+-- C_COMMON_CLK : 0
+-- C_DISABLE_WARN_BHV_COLL : 0
+-- C_DISABLE_WARN_BHV_RANGE : 0
+
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY result_bram_prod IS
+ PORT (
+ --Port A
+ CLKA : IN STD_LOGIC;
+ RSTA : IN STD_LOGIC; --opt port
+ ENA : IN STD_LOGIC; --optional port
+ REGCEA : IN STD_LOGIC; --optional port
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
+ DOUTA : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
+
+ --Port B
+ CLKB : IN STD_LOGIC;
+ RSTB : IN STD_LOGIC; --opt port
+ ENB : IN STD_LOGIC; --optional port
+ REGCEB : IN STD_LOGIC; --optional port
+ WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ DINB : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
+ DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
+
+ --ECC
+ INJECTSBITERR : IN STD_LOGIC; --optional port
+ INJECTDBITERR : IN STD_LOGIC; --optional port
+ SBITERR : OUT STD_LOGIC; --optional port
+ DBITERR : OUT STD_LOGIC; --optional port
+ RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
+ -- AXI BMG Input and Output Port Declarations
+
+ -- AXI Global Signals
+ S_ACLK : IN STD_LOGIC;
+ S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ S_AXI_AWVALID : IN STD_LOGIC;
+ S_AXI_AWREADY : OUT STD_LOGIC;
+ S_AXI_WDATA : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
+ S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ S_AXI_WLAST : IN STD_LOGIC;
+ S_AXI_WVALID : IN STD_LOGIC;
+ S_AXI_WREADY : OUT STD_LOGIC;
+ S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
+ S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ S_AXI_BVALID : OUT STD_LOGIC;
+ S_AXI_BREADY : IN STD_LOGIC;
+
+ -- AXI Full/Lite Slave Read (Write side)
+ S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+ S_AXI_ARVALID : IN STD_LOGIC;
+ S_AXI_ARREADY : OUT STD_LOGIC;
+ S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
+ S_AXI_RDATA : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
+ S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ S_AXI_RLAST : OUT STD_LOGIC;
+ S_AXI_RVALID : OUT STD_LOGIC;
+ S_AXI_RREADY : IN STD_LOGIC;
+
+ -- AXI Full/Lite Sideband Signals
+ S_AXI_INJECTSBITERR : IN STD_LOGIC;
+ S_AXI_INJECTDBITERR : IN STD_LOGIC;
+ S_AXI_SBITERR : OUT STD_LOGIC;
+ S_AXI_DBITERR : OUT STD_LOGIC;
+ S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ S_ARESETN : IN STD_LOGIC
+
+
+ );
+
+END result_bram_prod;
+
+
+ARCHITECTURE xilinx OF result_bram_prod IS
+
+ COMPONENT result_bram_exdes IS
+ PORT (
+ --Port A
+
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+ DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
+
+
+ CLKA : IN STD_LOGIC;
+
+
+ --Port B
+ ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
+ CLKB : IN STD_LOGIC
+
+
+
+ );
+ END COMPONENT;
+
+BEGIN
+
+ bmg0 : result_bram_exdes
+ PORT MAP (
+ --Port A
+
+ WEA => WEA,
+ ADDRA => ADDRA,
+
+ DINA => DINA,
+
+ CLKA => CLKA,
+
+ --Port B
+ ADDRB => ADDRB,
+ DOUTB => DOUTB,
+ CLKB => CLKB
+
+
+
+ );
+END xilinx;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/addr_gen.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/addr_gen.vhd
new file mode 100644
index 0000000..62706ca
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/addr_gen.vhd
@@ -0,0 +1,117 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Address Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: addr_gen.vhd
+--
+-- Description:
+-- Address Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY ADDR_GEN IS
+ GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
+ RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
+ RST_INC : INTEGER := 0);
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ LOAD :IN STD_LOGIC;
+ LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
+ ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
+ );
+END ADDR_GEN;
+
+ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
+ SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
+BEGIN
+ ADDR_OUT <= ADDR_TEMP;
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST='1') THEN
+ ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
+ ELSE
+ IF(EN='1') THEN
+ IF(LOAD='1') THEN
+ ADDR_TEMP <=LOAD_VALUE;
+ ELSE
+ IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
+ ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
+ ELSE
+ ADDR_TEMP <= ADDR_TEMP + '1';
+ END IF;
+ END IF;
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+END ARCHITECTURE;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/bmg_stim_gen.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/bmg_stim_gen.vhd
new file mode 100644
index 0000000..6fe0a18
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/bmg_stim_gen.vhd
@@ -0,0 +1,434 @@
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_stim_gen.vhd
+--
+-- Description:
+-- Stimulus Generation For SDP Configuration
+-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
+-- simulation ends
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+ LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY REGISTER_LOGIC IS
+ PORT(
+ Q : OUT STD_LOGIC;
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ D : IN STD_LOGIC
+ );
+END REGISTER_LOGIC;
+
+ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
+SIGNAL Q_O : STD_LOGIC :='0';
+BEGIN
+ Q <= Q_O;
+ FF_BEH: PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST ='1') THEN
+ Q_O <= '0';
+ ELSE
+ Q_O <= D;
+ END IF;
+ END IF;
+ END PROCESS;
+END REGISTER_ARCH;
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY BMG_STIM_GEN IS
+ PORT (
+ CLKA : IN STD_LOGIC;
+ CLKB : IN STD_LOGIC;
+ TB_RST : IN STD_LOGIC;
+ ADDRA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+ DINA : OUT STD_LOGIC_VECTOR(191 DOWNTO 0) := (OTHERS => '0');
+ WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
+ ADDRB: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+ CHECK_DATA: OUT STD_LOGIC:='0'
+ );
+END BMG_STIM_GEN;
+
+
+ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
+
+CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+SIGNAL DINA_INT : STD_LOGIC_VECTOR(191 DOWNTO 0) := (OTHERS => '0');
+SIGNAL DO_WRITE : STD_LOGIC := '0';
+SIGNAL DO_READ : STD_LOGIC := '0';
+SIGNAL DO_READ_R : STD_LOGIC := '0';
+SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
+SIGNAL PORTA_WR : STD_LOGIC:='0';
+SIGNAL COUNT : INTEGER :=0;
+SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
+SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
+SIGNAL PORTB_RD : STD_LOGIC:='0';
+SIGNAL COUNT_RD : INTEGER :=0;
+SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
+SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
+SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
+SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
+SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
+SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
+SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
+SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
+SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
+SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
+SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
+SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
+SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
+SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
+
+CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
+CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((8 <= 8),WR_RD_DEEP_COUNT,
+ ((192/192)*WR_RD_DEEP_COUNT));
+CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((8 <= 8),WR_RD_DEEP_COUNT,
+ ((192/192)*WR_RD_DEEP_COUNT));
+
+BEGIN
+
+ ADDRA <= WRITE_ADDR(7 DOWNTO 0) ;
+ DINA <= DINA_INT ;
+ ADDRB <= READ_ADDR(7 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
+ CHECK_DATA <= DO_READ;
+
+ RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+ GENERIC MAP(
+ C_MAX_DEPTH => 256 ,
+ RST_INC => 1 )
+ PORT MAP(
+ CLK => CLKB,
+ RST => TB_RST,
+ EN => DO_READ,
+ LOAD => '0',
+ LOAD_VALUE => ZERO,
+ ADDR_OUT => READ_ADDR
+ );
+
+ WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+ GENERIC MAP(
+ C_MAX_DEPTH => 256,
+ RST_INC => 1 )
+ PORT MAP(
+ CLK => CLKA,
+ RST => TB_RST,
+ EN => DO_WRITE,
+ LOAD => '0',
+ LOAD_VALUE => ZERO,
+ ADDR_OUT => WRITE_ADDR
+ );
+
+ WR_DATA_GEN_INST:ENTITY work.DATA_GEN
+ GENERIC MAP (
+ DATA_GEN_WIDTH => 192,
+ DOUT_WIDTH => 192 ,
+ DATA_PART_CNT => 1,
+ SEED => 2)
+ PORT MAP (
+ CLK => CLKA,
+ RST => TB_RST,
+ EN => DO_WRITE,
+ DATA_OUT => DINA_INT
+ );
+
+
+ PORTA_WR_PROCESS: PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(TB_RST='1') THEN
+ PORTA_WR<='1';
+ ELSE
+ PORTA_WR<=PORTB_RD_COMPLETE;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PORTB_RD_PROCESS: PROCESS(CLKB)
+ BEGIN
+ IF(RISING_EDGE(CLKB)) THEN
+ IF(TB_RST='1') THEN
+ PORTB_RD<='0';
+ ELSE
+ PORTB_RD<=PORTA_WR_L2;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
+ BEGIN
+ IF(RISING_EDGE(CLKB)) THEN
+ IF(TB_RST='1') THEN
+ LATCH_PORTB_RD_COMPLETE<='0';
+ ELSIF(PORTB_RD_COMPLETE='1') THEN
+ LATCH_PORTB_RD_COMPLETE <='1';
+ ELSIF(PORTA_WR_HAPPENED='1') THEN
+ LATCH_PORTB_RD_COMPLETE<='0';
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(TB_RST='1') THEN
+ PORTB_RD_L1 <='0';
+ PORTB_RD_L2 <='0';
+ ELSE
+ PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
+ PORTB_RD_L2 <= PORTB_RD_L1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PROCESS(CLKB)
+ BEGIN
+ IF(RISING_EDGE(CLKB)) THEN
+ IF(TB_RST='1') THEN
+ PORTA_WR_R1 <='0';
+ PORTA_WR_R2 <='0';
+ ELSE
+ PORTA_WR_R1 <= PORTA_WR;
+ PORTA_WR_R2 <= PORTA_WR_R1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PORTA_WR_HAPPENED <= PORTA_WR_R2;
+
+ PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(TB_RST='1') THEN
+ LATCH_PORTA_WR_COMPLETE<='0';
+ ELSIF(PORTA_WR_COMPLETE='1') THEN
+ LATCH_PORTA_WR_COMPLETE <='1';
+ --ELSIF(PORTB_RD_HAPPENED='1') THEN
+ ELSE
+ LATCH_PORTA_WR_COMPLETE<='0';
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PROCESS(CLKB)
+ BEGIN
+ IF(RISING_EDGE(CLKB)) THEN
+ IF(TB_RST='1') THEN
+ PORTA_WR_L1 <='0';
+ PORTA_WR_L2 <='0';
+ ELSE
+ PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
+ PORTA_WR_L2 <= PORTA_WR_L1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(TB_RST='1') THEN
+ PORTB_RD_R1 <='0';
+ PORTB_RD_R2 <='0';
+ ELSE
+ PORTB_RD_R1 <= PORTB_RD;
+ PORTB_RD_R2 <= PORTB_RD_R1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PORTB_RD_HAPPENED <= PORTB_RD_R2;
+
+ PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
+
+ start_rd_counter: process(clkb)
+ begin
+ if(rising_edge(clkb)) then
+ if(tb_rst='1') then
+ incr_rd_cnt <= '0';
+ elsif(portb_rd ='1') then
+ incr_rd_cnt <='1';
+ elsif(portb_rd_complete='1') then
+ incr_rd_cnt <='0';
+ end if;
+ end if;
+ end process;
+
+ RD_COUNTER: process(clkb)
+ begin
+ if(rising_edge(clkb)) then
+ if(tb_rst='1') then
+ count_rd <= 0;
+ elsif(incr_rd_cnt='1') then
+ count_rd<=count_rd+1;
+ end if;
+ --if(count_rd=(wr_rd_deep_count)) then
+ if(count_rd=(RD_DEEP_COUNT)) then
+ count_rd<=0;
+ end if;
+ end if;
+ end process;
+
+ DO_READ<='1' when (count_rd DO_READ_REG(0),
+ CLK => CLKB,
+ RST => TB_RST,
+ D => DO_READ
+ );
+ END GENERATE DFF_RIGHT;
+
+ DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
+ BEGIN
+ SHIFT_INST: ENTITY work.REGISTER_LOGIC
+ PORT MAP(
+ Q => DO_READ_REG(I),
+ CLK =>CLKB,
+ RST =>TB_RST,
+ D =>DO_READ_REG(I-1)
+ );
+ END GENERATE DFF_OTHERS;
+ END GENERATE BEGIN_SHIFT_REG;
+
+ REGCE_PROCESS: PROCESS(CLKB)
+ BEGIN
+ IF(RISING_EDGE(CLKB)) THEN
+ IF(TB_RST='1') THEN
+ DO_READ_R <= '0';
+ ELSE
+ DO_READ_R <= DO_READ;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+
+ WEA(0) <= DO_WRITE ;
+
+
+END ARCHITECTURE;
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/bmg_tb_pkg.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/bmg_tb_pkg.vhd
new file mode 100644
index 0000000..4928909
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/bmg_tb_pkg.vhd
@@ -0,0 +1,200 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Testbench Package
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_tb_pkg.vhd
+--
+-- Description:
+-- BMG Testbench Package files
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+PACKAGE BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+ DATA_VALUE : INTEGER;
+ DIVISOR : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC_VECTOR;
+ FALSE_CASE : STD_LOGIC_VECTOR)
+ RETURN STD_LOGIC_VECTOR;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STRING;
+ FALSE_CASE :STRING)
+ RETURN STRING;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC;
+ FALSE_CASE :STD_LOGIC)
+ RETURN STD_LOGIC;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : INTEGER;
+ FALSE_CASE : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION LOG2ROUNDUP (
+ DATA_VALUE : INTEGER)
+ RETURN INTEGER;
+
+END BMG_TB_PKG;
+
+PACKAGE BODY BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+ DATA_VALUE : INTEGER;
+ DIVISOR : INTEGER)
+ RETURN INTEGER IS
+ VARIABLE DIV : INTEGER;
+ BEGIN
+ DIV := DATA_VALUE/DIVISOR;
+ IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
+ DIV := DIV+1;
+ END IF;
+ RETURN DIV;
+ END DIVROUNDUP;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC_VECTOR;
+ FALSE_CASE : STD_LOGIC_VECTOR)
+ RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ IF NOT CONDITION THEN
+ RETURN FALSE_CASE;
+ ELSE
+ RETURN TRUE_CASE;
+ END IF;
+ END IF_THEN_ELSE;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STD_LOGIC;
+ FALSE_CASE : STD_LOGIC)
+ RETURN STD_LOGIC IS
+ BEGIN
+ IF NOT CONDITION THEN
+ RETURN FALSE_CASE;
+ ELSE
+ RETURN TRUE_CASE;
+ END IF;
+ END IF_THEN_ELSE;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : INTEGER;
+ FALSE_CASE : INTEGER)
+ RETURN INTEGER IS
+ VARIABLE RETVAL : INTEGER := 0;
+ BEGIN
+ IF CONDITION=FALSE THEN
+ RETVAL:=FALSE_CASE;
+ ELSE
+ RETVAL:=TRUE_CASE;
+ END IF;
+ RETURN RETVAL;
+ END IF_THEN_ELSE;
+ ---------------------------------
+ FUNCTION IF_THEN_ELSE (
+ CONDITION : BOOLEAN;
+ TRUE_CASE : STRING;
+ FALSE_CASE : STRING)
+ RETURN STRING IS
+ BEGIN
+ IF NOT CONDITION THEN
+ RETURN FALSE_CASE;
+ ELSE
+ RETURN TRUE_CASE;
+ END IF;
+ END IF_THEN_ELSE;
+ -------------------------------
+ FUNCTION LOG2ROUNDUP (
+ DATA_VALUE : INTEGER)
+ RETURN INTEGER IS
+ VARIABLE WIDTH : INTEGER := 0;
+ VARIABLE CNT : INTEGER := 1;
+ BEGIN
+ IF (DATA_VALUE <= 1) THEN
+ WIDTH := 1;
+ ELSE
+ WHILE (CNT < DATA_VALUE) LOOP
+ WIDTH := WIDTH + 1;
+ CNT := CNT *2;
+ END LOOP;
+ END IF;
+ RETURN WIDTH;
+ END LOG2ROUNDUP;
+
+END BMG_TB_PKG;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/checker.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/checker.vhd
new file mode 100644
index 0000000..15a2753
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/checker.vhd
@@ -0,0 +1,161 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Checker
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: checker.vhd
+--
+-- Description:
+-- Checker
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY CHECKER IS
+ GENERIC ( WRITE_WIDTH : INTEGER :=32;
+ READ_WIDTH : INTEGER :=32
+ );
+
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
+ STATUS : OUT STD_LOGIC:= '0'
+ );
+END CHECKER;
+
+ARCHITECTURE CHECKER_ARCH OF CHECKER IS
+ SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
+ SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
+ SIGNAL EN_R : STD_LOGIC := '0';
+ SIGNAL EN_2R : STD_LOGIC := '0';
+--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
+--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
+--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
+ CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
+ CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
+ SIGNAL ERR_HOLD : STD_LOGIC :='0';
+ SIGNAL ERR_DET : STD_LOGIC :='0';
+BEGIN
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST= '1') THEN
+ EN_R <= '0';
+ EN_2R <= '0';
+ DATA_IN_R <= (OTHERS=>'0');
+ ELSE
+ EN_R <= EN;
+ EN_2R <= EN_R;
+ DATA_IN_R <= DATA_IN;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
+ GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
+ DOUT_WIDTH => READ_WIDTH,
+ DATA_PART_CNT => DATA_PART_CNT,
+ SEED => 2
+ )
+ PORT MAP (
+ CLK => CLK,
+ RST => RST,
+ EN => EN_2R,
+ DATA_OUT => EXPECTED_DATA
+ );
+
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(EN_2R='1') THEN
+ IF(EXPECTED_DATA = DATA_IN_R) THEN
+ ERR_DET<='0';
+ ELSE
+ ERR_DET<= '1';
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ PROCESS(CLK,RST)
+ BEGIN
+ IF(RST='1') THEN
+ ERR_HOLD <= '0';
+ ELSIF(RISING_EDGE(CLK)) THEN
+ ERR_HOLD <= ERR_HOLD OR ERR_DET ;
+ END IF;
+ END PROCESS;
+
+ STATUS <= ERR_HOLD;
+
+END ARCHITECTURE;
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/data_gen.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/data_gen.vhd
new file mode 100644
index 0000000..fe3dca7
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/data_gen.vhd
@@ -0,0 +1,140 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Data Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: data_gen.vhd
+--
+-- Description:
+-- Data Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY DATA_GEN IS
+ GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
+ DOUT_WIDTH : INTEGER := 32;
+ DATA_PART_CNT : INTEGER := 1;
+ SEED : INTEGER := 2
+ );
+
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
+ );
+END DATA_GEN;
+
+ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
+ CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
+ SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
+ SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
+ SIGNAL LOCAL_CNT : INTEGER :=1;
+ SIGNAL DATA_GEN_I : STD_LOGIC :='0';
+BEGIN
+
+ LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
+ DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
+ DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
+
+ PROCESS(CLK)
+ BEGIN
+ IF(RISING_EDGE (CLK)) THEN
+ IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
+ LOCAL_CNT <=1;
+ ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
+ IF(LOCAL_CNT = 1) THEN
+ LOCAL_CNT <= LOCAL_CNT+1;
+ ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
+ LOCAL_CNT <= LOCAL_CNT+1;
+ ELSE
+ LOCAL_CNT <= 1;
+ END IF;
+ ELSE
+ LOCAL_CNT <= 1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
+ RAND_GEN_INST:ENTITY work.RANDOM
+ GENERIC MAP(
+ WIDTH => 8,
+ SEED => (SEED+N)
+ )
+ PORT MAP(
+ CLK => CLK,
+ RST => RST,
+ EN => DATA_GEN_I,
+ RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
+ );
+ END GENERATE RAND_GEN;
+
+END ARCHITECTURE;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/random.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/random.vhd
new file mode 100644
index 0000000..b0d417c
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/random.vhd
@@ -0,0 +1,112 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Random Number Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: random.vhd
+--
+-- Description:
+-- Random Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+ENTITY RANDOM IS
+ GENERIC ( WIDTH : INTEGER := 32;
+ SEED : INTEGER :=2
+ );
+
+ PORT (
+ CLK : IN STD_LOGIC;
+ RST : IN STD_LOGIC;
+ EN : IN STD_LOGIC;
+ RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
+ );
+END RANDOM;
+
+ARCHITECTURE BEHAVIORAL OF RANDOM IS
+BEGIN
+ PROCESS(CLK)
+ VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+ VARIABLE TEMP : STD_LOGIC := '0';
+ BEGIN
+ IF(RISING_EDGE(CLK)) THEN
+ IF(RST='1') THEN
+ RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+ ELSE
+ IF(EN = '1') THEN
+ TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
+ RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
+ RAND_TEMP(0) := TEMP;
+ END IF;
+ END IF;
+ END IF;
+ RANDOM_NUM <= RAND_TEMP;
+ END PROCESS;
+END ARCHITECTURE;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/result_bram_synth.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/result_bram_synth.vhd
new file mode 100644
index 0000000..b19a76a
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/result_bram_synth.vhd
@@ -0,0 +1,322 @@
+
+
+
+
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: result_bram_synth.vhd
+--
+-- Description:
+-- Synthesizable Testbench
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY STD;
+USE STD.TEXTIO.ALL;
+
+--LIBRARY unisim;
+--USE unisim.vcomponents.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY result_bram_synth IS
+PORT(
+ CLK_IN : IN STD_LOGIC;
+ CLKB_IN : IN STD_LOGIC;
+ RESET_IN : IN STD_LOGIC;
+ STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
+ );
+END ENTITY;
+
+ARCHITECTURE result_bram_synth_ARCH OF result_bram_synth IS
+
+
+COMPONENT result_bram_exdes
+ PORT (
+ --Inputs - Port A
+ WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
+ CLKA : IN STD_LOGIC;
+
+ --Inputs - Port B
+ ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0);
+ CLKB : IN STD_LOGIC
+
+ );
+
+END COMPONENT;
+
+
+ SIGNAL CLKA: STD_LOGIC := '0';
+ SIGNAL RSTA: STD_LOGIC := '0';
+ SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DINA: STD_LOGIC_VECTOR(191 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DINA_R: STD_LOGIC_VECTOR(191 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL CLKB: STD_LOGIC := '0';
+ SIGNAL RSTB: STD_LOGIC := '0';
+ SIGNAL ADDRB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ADDRB_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL DOUTB: STD_LOGIC_VECTOR(191 DOWNTO 0);
+ SIGNAL CHECKER_EN : STD_LOGIC:='0';
+ SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
+ SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
+ SIGNAL clk_in_i: STD_LOGIC;
+
+ SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
+ SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
+ SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
+
+ SIGNAL clkb_in_i: STD_LOGIC;
+ SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
+ SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
+ SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
+ SIGNAL ITER_R0 : STD_LOGIC := '0';
+ SIGNAL ITER_R1 : STD_LOGIC := '0';
+ SIGNAL ITER_R2 : STD_LOGIC := '0';
+
+ SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+
+ BEGIN
+
+-- clk_buf: bufg
+-- PORT map(
+-- i => CLK_IN,
+-- o => clk_in_i
+-- );
+ clk_in_i <= CLK_IN;
+ CLKA <= clk_in_i;
+
+-- clkb_buf: bufg
+-- PORT map(
+-- i => CLKB_IN,
+-- o => clkb_in_i
+-- );
+ clkb_in_i <= CLKB_IN;
+ CLKB <= clkb_in_i;
+ RSTA <= RESET_SYNC_R3 AFTER 50 ns;
+
+
+ PROCESS(clk_in_i)
+ BEGIN
+ IF(RISING_EDGE(clk_in_i)) THEN
+ RESET_SYNC_R1 <= RESET_IN;
+ RESET_SYNC_R2 <= RESET_SYNC_R1;
+ RESET_SYNC_R3 <= RESET_SYNC_R2;
+ END IF;
+ END PROCESS;
+
+ RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
+
+ PROCESS(clkb_in_i)
+ BEGIN
+ IF(RISING_EDGE(clkb_in_i)) THEN
+ RESETB_SYNC_R1 <= RESET_IN;
+ RESETB_SYNC_R2 <= RESETB_SYNC_R1;
+ RESETB_SYNC_R3 <= RESETB_SYNC_R2;
+ END IF;
+ END PROCESS;
+
+PROCESS(CLKA)
+BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ ISSUE_FLAG_STATUS<= (OTHERS => '0');
+ ELSE
+ ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
+ END IF;
+ END IF;
+END PROCESS;
+
+STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
+
+
+
+
+ BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
+ GENERIC MAP (
+ WRITE_WIDTH => 192,
+ READ_WIDTH => 192 )
+ PORT MAP (
+ CLK => clkb_in_i,
+ RST => RSTB,
+ EN => CHECKER_EN_R,
+ DATA_IN => DOUTB,
+ STATUS => ISSUE_FLAG(0)
+ );
+
+ PROCESS(clkb_in_i)
+ BEGIN
+ IF(RISING_EDGE(clkb_in_i)) THEN
+ IF(RSTB='1') THEN
+ CHECKER_EN_R <= '0';
+ ELSE
+ CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
+ PORT MAP(
+ CLKA => clk_in_i,
+ CLKB => clkb_in_i,
+ TB_RST => RSTA,
+ ADDRA => ADDRA,
+ DINA => DINA,
+ WEA => WEA,
+ ADDRB => ADDRB,
+ CHECK_DATA => CHECKER_EN
+ );
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ STATUS(8) <= '0';
+ iter_r2 <= '0';
+ iter_r1 <= '0';
+ iter_r0 <= '0';
+ ELSE
+ STATUS(8) <= iter_r2;
+ iter_r2 <= iter_r1;
+ iter_r1 <= iter_r0;
+ iter_r0 <= STIMULUS_FLOW(8);
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ STIMULUS_FLOW <= (OTHERS => '0');
+ ELSIF(WEA(0)='1') THEN
+ STIMULUS_FLOW <= STIMULUS_FLOW+1;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ WEA_R <= (OTHERS=>'0') AFTER 50 ns;
+ DINA_R <= (OTHERS=>'0') AFTER 50 ns;
+
+
+ ELSE
+ WEA_R <= WEA AFTER 50 ns;
+ DINA_R <= DINA AFTER 50 ns;
+
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ PROCESS(CLKA)
+ BEGIN
+ IF(RISING_EDGE(CLKA)) THEN
+ IF(RESET_SYNC_R3='1') THEN
+ ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
+ ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
+ ELSE
+ ADDRA_R <= ADDRA AFTER 50 ns;
+ ADDRB_R <= ADDRB AFTER 50 ns;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ BMG_PORT: result_bram_exdes PORT MAP (
+ --Port A
+ WEA => WEA_R,
+ ADDRA => ADDRA_R,
+ DINA => DINA_R,
+ CLKA => CLKA,
+ --Port B
+ ADDRB => ADDRB_R,
+ DOUTB => DOUTB,
+ CLKB => CLKB
+
+ );
+END ARCHITECTURE;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/result_bram_tb.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/result_bram_tb.vhd
new file mode 100644
index 0000000..b32aed4
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/result_bram/simulation/result_bram_tb.vhd
@@ -0,0 +1,142 @@
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+-- Filename: result_bram_tb.vhd
+-- Description:
+-- Testbench Top
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY result_bram_tb IS
+END ENTITY;
+
+
+ARCHITECTURE result_bram_tb_ARCH OF result_bram_tb IS
+ SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
+ SIGNAL CLK : STD_LOGIC := '1';
+ SIGNAL CLKB : STD_LOGIC := '1';
+ SIGNAL RESET : STD_LOGIC;
+
+ BEGIN
+
+
+ CLK_GEN: PROCESS BEGIN
+ CLK <= NOT CLK;
+ WAIT FOR 100 NS;
+ CLK <= NOT CLK;
+ WAIT FOR 100 NS;
+ END PROCESS;
+ CLKB_GEN: PROCESS BEGIN
+ CLKB <= NOT CLKB;
+ WAIT FOR 100 NS;
+ CLKB <= NOT CLKB;
+ WAIT FOR 100 NS;
+ END PROCESS;
+
+ RST_GEN: PROCESS BEGIN
+ RESET <= '1';
+ WAIT FOR 1000 NS;
+ RESET <= '0';
+ WAIT;
+ END PROCESS;
+
+
+--STOP_SIM: PROCESS BEGIN
+-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
+-- ASSERT FALSE
+-- REPORT "END SIMULATION TIME REACHED"
+-- SEVERITY FAILURE;
+--END PROCESS;
+--
+PROCESS BEGIN
+ WAIT UNTIL STATUS(8)='1';
+ IF( STATUS(7 downto 0)/="0") THEN
+ ASSERT false
+ REPORT "Test Completed Successfully"
+ SEVERITY NOTE;
+ REPORT "Simulation Failed"
+ SEVERITY FAILURE;
+ ELSE
+ ASSERT false
+ REPORT "TEST PASS"
+ SEVERITY NOTE;
+ REPORT "Test Completed Successfully"
+ SEVERITY FAILURE;
+ END IF;
+
+END PROCESS;
+
+ result_bram_synth_inst:ENTITY work.result_bram_synth
+ PORT MAP(
+ CLK_IN => CLK,
+ CLKB_IN => CLK,
+ RESET_IN => RESET,
+ STATUS => STATUS
+ );
+
+END ARCHITECTURE;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/wide_mult.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/wide_mult.gise
new file mode 100644
index 0000000..3da6a8c
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/wide_mult.gise
@@ -0,0 +1,53 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/wide_mult.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/wide_mult.vhd
new file mode 100644
index 0000000..8879fd9
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/Generator/ipcore_dir/wide_mult.vhd
@@ -0,0 +1,102 @@
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2022 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file wide_mult.vhd when simulating
+-- the core, wide_mult. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY wide_mult IS
+ PORT (
+ clk : IN STD_LOGIC;
+ a : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(26 DOWNTO 0);
+ ce : IN STD_LOGIC;
+ p : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
+ );
+END wide_mult;
+
+ARCHITECTURE wide_mult_a OF wide_mult IS
+-- synthesis translate_off
+COMPONENT wrapped_wide_mult
+ PORT (
+ clk : IN STD_LOGIC;
+ a : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(26 DOWNTO 0);
+ ce : IN STD_LOGIC;
+ p : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_wide_mult USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
+ GENERIC MAP (
+ c_a_type => 1,
+ c_a_width => 13,
+ c_b_type => 1,
+ c_b_value => "10000001",
+ c_b_width => 27,
+ c_ccm_imp => 0,
+ c_ce_overrides_sclr => 0,
+ c_has_ce => 1,
+ c_has_sclr => 0,
+ c_has_zero_detect => 0,
+ c_latency => 5,
+ c_model_type => 0,
+ c_mult_type => 1,
+ c_optimize_goal => 1,
+ c_out_high => 39,
+ c_out_low => 0,
+ c_round_output => 0,
+ c_round_pt => 0,
+ c_verbosity => 0,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_wide_mult
+ PORT MAP (
+ clk => clk,
+ a => a,
+ b => b,
+ ce => ce,
+ p => p
+ );
+-- synthesis translate_on
+
+END wide_mult_a;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/BuildConfig.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/BuildConfig.vhd
new file mode 100644
index 0000000..6f9866f
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/BuildConfig.vhd
@@ -0,0 +1,6 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+package BuildConfig is
+ constant EXTERNAL_MASTER_LO_SLAVE : boolean := false;
+end package BuildConfig;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/BuildConfig_external_lo_slave.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/BuildConfig_external_lo_slave.vhd
new file mode 100644
index 0000000..651341d
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/BuildConfig_external_lo_slave.vhd
@@ -0,0 +1,6 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+package BuildConfig is
+ constant EXTERNAL_MASTER_LO_SLAVE : boolean := true;
+end package BuildConfig;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/DFT.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/DFT.vhd
new file mode 100644
index 0000000..8975b9b
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/DFT.vhd
@@ -0,0 +1,358 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:38:37 09/18/2020
+-- Design Name:
+-- Module Name: DFT - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity DFT is
+ Generic (BINS : integer);
+ Port ( CLK : in STD_LOGIC;
+ RESET : in STD_LOGIC;
+ PORT1 : in STD_LOGIC_VECTOR (17 downto 0);
+ PORT2 : in STD_LOGIC_VECTOR (17 downto 0);
+ NEW_SAMPLE : in STD_LOGIC;
+ NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
+ BIN1_PHASEINC : in STD_LOGIC_VECTOR (15 downto 0);
+ DIFFBIN_PHASEINC : in STD_LOGIC_VECTOR (15 downto 0);
+ RESULT_READY : out STD_LOGIC;
+ OUTPUT : out STD_LOGIC_VECTOR (191 downto 0);
+ NEXT_OUTPUT : in STD_LOGIC);
+end DFT;
+
+architecture Behavioral of DFT is
+COMPONENT result_bram
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(191 DOWNTO 0)
+ );
+END COMPONENT;
+COMPONENT SinCos
+ PORT (
+ clk : IN STD_LOGIC;
+ phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+ cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+ );
+END COMPONENT;
+COMPONENT DSP_SLICE
+ PORT (
+ clk : IN STD_LOGIC;
+ ce : IN STD_LOGIC;
+ sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+ p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+ );
+END COMPONENT;
+COMPONENT window
+PORT(
+ CLK : IN std_logic;
+ INDEX : IN std_logic_vector(6 downto 0);
+ WINDOW_TYPE : IN std_logic_vector(1 downto 0);
+ VALUE : OUT std_logic_vector(15 downto 0)
+ );
+END COMPONENT;
+
+ --type result is array(BINS-1 downto 0) of std_logic_vector(47 downto 0);
+ --signal port1_real : result;
+ --signal port1_imag : result;
+ --signal port2_real : result;
+ --signal port2_imag : result;
+
+ --signal port1_real_read : std_logic_vector(47 downto 0);
+ --signal port1_imag_read : std_logic_vector(47 downto 0);
+ --signal port2_real_read : std_logic_vector(47 downto 0);
+ --signal port2_imag_read : std_logic_vector(47 downto 0);
+
+ signal sample_cnt : integer range 0 to 131072;
+ signal samples_to_take : integer range 0 to 131072;
+ signal bin_cnt : integer range 0 to BINS+2;
+
+ signal read_address : integer range 0 to BINS-1;
+ signal write_address : integer range 0 to BINS-1;
+ signal read_address_vector : std_logic_vector(7 downto 0);
+ signal write_address_vector : std_logic_vector(7 downto 0);
+ signal we : std_logic_vector(0 downto 0);
+ signal ram_in : std_logic_vector(191 downto 0);
+ signal ram_out : std_logic_vector(191 downto 0);
+
+ type States is (WaitingForSample, WaitMult, WaitSinCos, Busy, Ready);
+ signal state : States;
+ signal port1_latch : std_logic_vector(17 downto 0);
+ signal port2_latch : std_logic_vector(17 downto 0);
+
+ signal phase : std_logic_vector(31 downto 0);
+ signal phase_inc : std_logic_vector(31 downto 0);
+ signal sine : std_logic_vector(15 downto 0);
+ signal cosine : std_logic_vector(15 downto 0);
+
+ signal mult1_a : std_logic_vector(17 downto 0);
+ signal mult1_b : std_logic_vector(17 downto 0);
+ signal mult1_c : std_logic_vector(47 downto 0);
+ signal mult1_p : std_logic_vector(47 downto 0);
+
+ signal mult2_a : std_logic_vector(17 downto 0);
+ signal mult2_b : std_logic_vector(17 downto 0);
+ signal mult2_c : std_logic_vector(47 downto 0);
+ signal mult2_p : std_logic_vector(47 downto 0);
+
+ signal mult3_a : std_logic_vector(17 downto 0);
+ signal mult3_b : std_logic_vector(17 downto 0);
+ signal mult3_c : std_logic_vector(47 downto 0);
+ signal mult3_p : std_logic_vector(47 downto 0);
+
+ signal mult4_a : std_logic_vector(17 downto 0);
+ signal mult4_b : std_logic_vector(17 downto 0);
+ signal mult4_c : std_logic_vector(47 downto 0);
+ signal mult4_p : std_logic_vector(47 downto 0);
+
+ signal mult_enable : std_logic;
+ signal mult_accumulate : std_logic_vector(0 downto 0);
+begin
+
+ LookupTable : SinCos
+ PORT MAP (
+ clk => CLK,
+ phase_in => phase(31 downto 20),
+ cosine => cosine,
+ sine => sine
+ );
+ Mult1 : DSP_SLICE
+ PORT MAP (
+ clk => CLK,
+ ce => mult_enable,
+ sel => mult_accumulate,
+ a => mult1_a,
+ b => mult1_b,
+ c => mult1_c,
+ p => mult1_p
+ );
+ Mult2 : DSP_SLICE
+ PORT MAP (
+ clk => CLK,
+ ce => mult_enable,
+ sel => mult_accumulate,
+ a => mult2_a,
+ b => mult2_b,
+ c => mult2_c,
+ p => mult2_p
+ );
+ Mult3 : DSP_SLICE
+ PORT MAP (
+ clk => CLK,
+ ce => mult_enable,
+ sel => mult_accumulate,
+ a => mult3_a,
+ b => mult3_b,
+ c => mult3_c,
+ p => mult3_p
+ );
+ Mult4 : DSP_SLICE
+ PORT MAP (
+ clk => CLK,
+ ce => mult_enable,
+ sel => mult_accumulate,
+ a => mult4_a,
+ b => mult4_b,
+ c => mult4_c,
+ p => mult4_p
+ );
+
+ result_ram: result_bram
+ PORT MAP (
+ clka => CLK,
+ wea => we,
+ addra => write_address_vector,
+ dina => ram_in,
+ clkb => CLK,
+ addrb => read_address_vector,
+ doutb => ram_out
+ );
+
+ read_address_vector <= std_logic_vector(to_unsigned(read_address, 8));
+ write_address_vector <= std_logic_vector(to_unsigned(write_address, 8));
+ OUTPUT <= ram_out;
+
+ mult1_c <= ram_out(191 downto 144);
+ mult2_c <= ram_out(143 downto 96);
+ mult3_c <= ram_out(95 downto 48);
+ mult4_c <= ram_out(47 downto 0);
+
+ ram_in <= mult1_p & mult2_p & mult3_p & mult4_p;
+
+ process(CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ mult_enable <= '0';
+ mult_accumulate <= "0";
+ sample_cnt <= 0;
+ RESULT_READY <= '0';
+ read_address <= 0;
+ write_address <= 0;
+ we <= "0";
+ state <= WaitingForSample;
+ else
+ samples_to_take <= to_integer(unsigned(NSAMPLES & "0000")) - 1;
+ case state is
+ when WaitingForSample =>
+ we <= "0";
+ mult_enable <= '0';
+ mult_accumulate <= "0";
+ read_address <= 0;
+ write_address <= 0;
+ if NEW_SAMPLE = '1' then
+ -- calculate phase for initial bin
+ mult1_a <= std_logic_vector(to_unsigned(sample_cnt, 18));
+ mult1_b <= "00" & BIN1_PHASEINC;
+ mult2_a <= std_logic_vector(to_unsigned(sample_cnt, 18));
+ mult2_b <= "00" & DIFFBIN_PHASEINC;
+ state <= WaitMult;
+ bin_cnt <= 0;
+ mult_enable <= '1';
+ end if;
+ when WaitMult =>
+ RESULT_READY <= '0';
+ we <= "0";
+ mult_enable <= '1';
+ mult_accumulate <= "0";
+ read_address <= 0;
+ write_address <= 0;
+ if bin_cnt < 4 then
+ bin_cnt <= bin_cnt + 1;
+ else
+ bin_cnt <= 0;
+ mult_enable <= '0';
+ state <= WaitSinCos;
+ phase <= mult1_p(15 downto 0) & "0000000000000000";
+ phase_inc <= mult2_p(23 downto 0) & "00000000";
+ port1_latch <= PORT1;
+ port2_latch <= PORT2;
+ end if;
+ when WaitSinCos =>
+ phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
+ RESULT_READY <= '0';
+ we <= "0";
+ mult_enable <= '0';
+ mult_accumulate <= "0";
+ read_address <= 0;
+ write_address <= 0;
+ if bin_cnt < 6 then
+ bin_cnt <= bin_cnt + 1;
+ else
+ bin_cnt <= 0;
+ mult_enable <= '1';
+ read_address <= 1;
+ -- sign extended multiplication
+ mult1_a <= port1_latch;
+ mult1_b <= sine(15) & sine(15) & sine;
+ mult2_a <= port1_latch;
+ mult2_b <= cosine(15) & cosine(15) & cosine;
+ mult3_a <= port2_latch;
+ mult3_b <= sine(15) & sine(15) & sine;
+ mult4_a <= port2_latch;
+ mult4_b <= cosine(15) & cosine(15) & cosine;
+ state <= BUSY;
+ if sample_cnt = 0 then
+ mult_accumulate <= "0";
+ else
+ mult_accumulate <= "1";
+ end if;
+ end if;
+ when BUSY =>
+ mult_enable <= '1';
+ if sample_cnt = 0 then
+ mult_accumulate <= "0";
+ else
+ mult_accumulate <= "1";
+ end if;
+ RESULT_READY <= '0';
+ phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
+ -- sign extended multiplication
+ mult1_a <= port1_latch;
+ mult1_b <= sine(15) & sine(15) & sine;
+ mult2_a <= port1_latch;
+ mult2_b <= cosine(15) & cosine(15) & cosine;
+ mult3_a <= port2_latch;
+ mult3_b <= sine(15) & sine(15) & sine;
+ mult4_a <= port2_latch;
+ mult4_b <= cosine(15) & cosine(15) & cosine;
+ if bin_cnt >= 3 then
+ -- multiplier result is available, advance write address
+ we <= "1";
+ write_address <= bin_cnt - 3;
+ else
+ we <= "0";
+ write_address <= 0;
+ end if;
+ if bin_cnt >= BINS+2 then
+ read_address <= 0;
+ if sample_cnt < samples_to_take then
+ sample_cnt <= sample_cnt + 1;
+ state <= WaitingForSample;
+ else
+ state <= Ready;
+ end if;
+ else
+ bin_cnt <= bin_cnt + 1;
+ if bin_cnt < BINS - 2 then
+ read_address <= bin_cnt + 2;
+ end if;
+ end if;
+ when Ready =>
+ we <= "0";
+ RESULT_READY <= '1';
+ write_address <= 0;
+ if NEXT_OUTPUT = '1' then
+ -- fetch next entry from RAM
+ if read_address < BINS - 1 then
+ read_address <= read_address + 1;
+ else
+ RESULT_READY <= '0';
+ sample_cnt <= 0;
+ mult_enable <= '0';
+ state <= WaitingForSample;
+ read_address <= 0;
+ end if;
+ end if;
+ when others =>
+ state <= WaitingForSample;
+ end case;
+ end if;
+ end if;
+ end process;
+
+
+end Behavioral;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Flattop.dat b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Flattop.dat
new file mode 100644
index 0000000..b84433c
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Flattop.dat
@@ -0,0 +1,128 @@
+1111111111111000
+1111111111110110
+1111111111110001
+1111111111101001
+1111111111011111
+1111111111010001
+1111111110111111
+1111111110101001
+1111111110001110
+1111111101101110
+1111111101001000
+1111111100011100
+1111111011101001
+1111111010101111
+1111111001101111
+1111111000101000
+1111110111011011
+1111110110001000
+1111110100110001
+1111110011011000
+1111110001111101
+1111110000100011
+1111101111001101
+1111101101111101
+1111101100110111
+1111101011111110
+1111101011010111
+1111101011000100
+1111101011001011
+1111101011110001
+1111101100111001
+1111101110101000
+1111110001000011
+1111110100001110
+1111111000001100
+1111111101000001
+0000000010101110
+0000001001011001
+0000010001000000
+0000011001100100
+0000100011000101
+0000101101100010
+0000111000111000
+0001000101000100
+0001010010000000
+0001011111100111
+0001101101110011
+0001111100011100
+0010001011011001
+0010011010100001
+0010101001101011
+0010111000101100
+0011000111011001
+0011010101101000
+0011100011001110
+0011110000000000
+0011111011110100
+0100000110100001
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Hann.dat b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Hann.dat
new file mode 100644
index 0000000..593bd59
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Hann.dat
@@ -0,0 +1,128 @@
+0000000000000001
+0000000000001011
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Kaiser.dat b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Kaiser.dat
new file mode 100644
index 0000000..7d622f5
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Kaiser.dat
@@ -0,0 +1,128 @@
+0000000000000110
+0000000000001011
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+0000000000100111
+0000000000110110
+0000000001000111
+0000000001011101
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/MAX2871.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/MAX2871.vhd
new file mode 100644
index 0000000..b7b9f13
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/MAX2871.vhd
@@ -0,0 +1,117 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:59:45 05/05/2020
+-- Design Name:
+-- Module Name: MAX2871 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity MAX2871 is
+ Generic (CLK_DIV : integer);
+ Port ( CLK : in STD_LOGIC;
+ RESET : in STD_LOGIC;
+ REG4 : in STD_LOGIC_VECTOR (31 downto 0);
+ REG3 : in STD_LOGIC_VECTOR (31 downto 0);
+ REG1 : in STD_LOGIC_VECTOR (31 downto 0);
+ REG0 : in STD_LOGIC_VECTOR (31 downto 0);
+ RELOAD : in STD_LOGIC;
+ CLK_OUT : out STD_LOGIC;
+ MOSI : out STD_LOGIC;
+ LE : out STD_LOGIC;
+ DONE : out STD_LOGIC);
+end MAX2871;
+
+architecture Behavioral of MAX2871 is
+ signal clk_cnt : integer range 0 to (CLK_DIV/2)-1;
+ signal reg_cnt : integer range 0 to 3;
+ signal bit_cnt : integer range 0 to 32;
+ signal latched_regs : std_logic_vector(127 downto 0);
+
+ signal sclk : std_logic;
+ signal latch : std_logic;
+ signal done_int : std_logic;
+begin
+
+ CLK_OUT <= sclk;
+ MOSI <= latched_regs(127);
+ LE <= latch;
+ DONE <= done_int;
+
+ process(CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ sclk <= '0';
+ latch <= '0';
+ done_int <= '1';
+ else
+ if done_int = '1' then
+ -- can start a new reload process
+ if RELOAD = '1' then
+ done_int <= '0';
+ latched_regs <= REG4 & REG3 & REG1 & REG0;
+ reg_cnt <= 0;
+ bit_cnt <= 0;
+ clk_cnt <= 0;
+ end if;
+ else
+ if clk_cnt < (CLK_DIV/2) - 1 then
+ clk_cnt <= clk_cnt + 1;
+ else
+ clk_cnt <= 0;
+ -- advance SPI state machine
+ if bit_cnt < 32 then
+ if sclk = '0' then
+ sclk <= '1';
+ else
+ -- falling edge of clk, shift out new bit
+ sclk <= '0';
+ latched_regs <= latched_regs(126 downto 0) & "0";
+ bit_cnt <= bit_cnt + 1;
+ end if;
+ else
+ -- shifted out one register, strobe latch
+ if latch = '0' then
+ latch <= '1';
+ else
+ latch <= '0';
+ -- move on to next register
+ if reg_cnt < 3 then
+ reg_cnt <= reg_cnt + 1;
+ bit_cnt <= 0;
+ else
+ -- all done
+ done_int <= '1';
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+end Behavioral;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/MCP33131.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/MCP33131.vhd
new file mode 100644
index 0000000..d0db141
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/MCP33131.vhd
@@ -0,0 +1,161 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:01:43 05/05/2020
+-- Design Name:
+-- Module Name: MCP33131 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity MCP33131 is
+ Generic(CLK_DIV : integer;
+ CONVCYCLES : integer);
+ Port ( CLK : in STD_LOGIC;
+ RESET : in STD_LOGIC;
+ START : in STD_LOGIC;
+ READY : out STD_LOGIC;
+ DATA : out STD_LOGIC_VECTOR (15 downto 0);
+ MIN : out STD_LOGIC_VECTOR (15 downto 0);
+ MAX : out STD_LOGIC_VECTOR (15 downto 0);
+ RESET_MINMAX : in STD_LOGIC;
+ SDO : in STD_LOGIC;
+ CONVSTART : out STD_LOGIC;
+ SCLK : inout STD_LOGIC);
+end MCP33131;
+
+architecture Behavioral of MCP33131 is
+ signal conv_cnt : integer range 0 to CONVCYCLES-1;
+ signal div_cnt : integer range 0 to (CLK_DIV/2)-1;
+ signal bit_cnt : integer range 0 to 15;
+ signal sclk_phase : std_logic;
+ signal adc_data : std_logic_vector(15 downto 0);
+ type States is (Idle, Conversion, WAIT_tEN, Transmission, Done);
+ signal state : States;
+ signal ready_int : std_logic;
+ signal ready_delay : integer range 0 to 30;
+ signal min_int, max_int, data_int : signed(15 downto 0);
+begin
+
+ MIN <= std_logic_vector(min_int);
+ MAX <= std_logic_vector(max_int);
+ DATA <= std_logic_vector(data_int);
+ SCLK <= sclk_phase;
+
+ process(SCLK, START)
+ begin
+ if(falling_edge(SCLK)) then
+ adc_data <= adc_data(14 downto 0) & SDO;
+ end if;
+ end process;
+
+ process(CLK, RESET)
+ begin
+ if(rising_edge(CLK)) then
+ if(RESET = '1') then
+ state <= Idle;
+ READY <= '0';
+ ready_int <= '0';
+ CONVSTART <= '0';
+ sclk_phase <= '0';
+ CONVSTART <= '0';
+ conv_cnt <= 0;
+ div_cnt <= 0;
+ bit_cnt <= 0;
+ min_int <= to_signed(32767, 16);
+ max_int <= to_signed(-32768, 16);
+ else
+ if RESET_MINMAX = '1' then
+ min_int <= to_signed(32767, 16);
+ max_int <= to_signed(-32768, 16);
+ else
+ if data_int < min_int then
+ min_int <= data_int;
+ end if;
+ if data_int > max_int then
+ max_int <= data_int;
+ end if;
+ end if;
+
+ READY <= '0';
+ if ready_int = '1' then
+ ready_delay <= 3;
+ else
+ if ready_delay > 0 then
+ ready_delay <= ready_delay - 1;
+ end if;
+ if ready_delay = 1 then
+ READY <= '1';
+ data_int <= signed(adc_data);
+ end if;
+ end if;
+
+ case state is
+ when Idle =>
+ ready_int <= '0';
+ if START = '1' then
+ state <= Conversion;
+ conv_cnt <= 0;
+ CONVSTART <= '1';
+ end if;
+ when Conversion =>
+ ready_int <= '0';
+ if(conv_cnt < CONVCYCLES-1) then
+ conv_cnt <= conv_cnt + 1;
+ else
+ div_cnt <= 0;
+ CONVSTART <= '0';
+ state <= WAIT_tEN;
+ end if;
+ when WAIT_tEN =>
+ ready_int <= '0';
+ state <= Transmission;
+ when Transmission =>
+ ready_int <= '0';
+ if(div_cnt < (CLK_DIV/2)-1) then
+ div_cnt <= div_cnt + 1;
+ else
+ if(sclk_phase = '0') then
+ sclk_phase <= '1';
+ else
+ sclk_phase <= '0';
+ if bit_cnt = 15 then
+ state <= Done;
+ bit_cnt <= 0;
+ else
+ bit_cnt <= bit_cnt + 1;
+ end if;
+ end if;
+ div_cnt <= 0;
+ end if;
+ when Done =>
+ ready_int <= '1';
+ state <= Idle;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end Behavioral;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ResetDelay.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ResetDelay.vhd
new file mode 100644
index 0000000..bb8c1d0
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ResetDelay.vhd
@@ -0,0 +1,61 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:06:31 05/12/2020
+-- Design Name:
+-- Module Name: ResetDelay - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ResetDelay is
+ Generic(CLK_DELAY : integer);
+ Port ( CLK : in STD_LOGIC;
+ IN_RESET : in STD_LOGIC;
+ OUT_RESET : out STD_LOGIC);
+end ResetDelay;
+
+architecture Behavioral of ResetDelay is
+ signal clk_cnt : integer range 0 to CLK_DELAY-1;
+begin
+
+ process(CLK, IN_RESET)
+ begin
+ if rising_edge(CLK) then
+ if IN_RESET = '1' then
+ clk_cnt <= 0;
+ OUT_RESET <= '1';
+ else
+ if clk_cnt < CLK_DELAY-1 then
+ clk_cnt <= clk_cnt + 1;
+ else
+ OUT_RESET <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+end Behavioral;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/SPIConfig.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/SPIConfig.vhd
new file mode 100644
index 0000000..4703728
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/SPIConfig.vhd
@@ -0,0 +1,329 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 19:51:11 05/05/2020
+-- Design Name:
+-- Module Name: SPICommands - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity SPICommands is
+ Port ( CLK : in STD_LOGIC;
+ RESET : in STD_LOGIC;
+ SCLK : in STD_LOGIC;
+ MOSI : in STD_LOGIC;
+ MISO : out STD_LOGIC;
+ NSS : in STD_LOGIC;
+ NEW_SAMPLING_DATA : in STD_LOGIC;
+ SAMPLING_RESULT : in STD_LOGIC_VECTOR (303 downto 0);
+ ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
+ SOURCE_UNLOCKED : in STD_LOGIC;
+ LO_UNLOCKED : in STD_LOGIC;
+ MAX2871_DEF_4 : out STD_LOGIC_VECTOR (31 downto 0);
+ MAX2871_DEF_3 : out STD_LOGIC_VECTOR (31 downto 0);
+ MAX2871_DEF_1 : out STD_LOGIC_VECTOR (31 downto 0);
+ MAX2871_DEF_0 : out STD_LOGIC_VECTOR (31 downto 0);
+ SWEEP_DATA : out STD_LOGIC_VECTOR (95 downto 0);
+ SWEEP_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
+ SWEEP_WRITE : out STD_LOGIC_VECTOR (0 downto 0);
+ SWEEP_POINTS : out STD_LOGIC_VECTOR (12 downto 0);
+ NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
+ STAGES : out STD_LOGIC_VECTOR (2 downto 0);
+ SETTLING_TIME : out STD_LOGIC_VECTOR (19 downto 0);
+ SYNC_ENABLED : out STD_LOGIC;
+ SYNC_MASTER : out STD_LOGIC;
+ PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
+ PORT2_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
+ PORT1_EN : out STD_LOGIC;
+ PORT2_EN : out STD_LOGIC;
+ REF_EN : out STD_LOGIC;
+ AMP_SHDN : out STD_LOGIC;
+ SOURCE_RF_EN : out STD_LOGIC;
+ LO_RF_EN : out STD_LOGIC;
+ SOURCE_CE_EN : out STD_LOGIC;
+ LO_CE_EN : out STD_LOGIC;
+ PORTSWITCH_EN : out STD_LOGIC;
+ LEDS : out STD_LOGIC_VECTOR(2 downto 0);
+ WINDOW_SETTING : out STD_LOGIC_VECTOR(1 downto 0);
+ ADC_PRESCALER : out STD_LOGIC_VECTOR(7 downto 0);
+ ADC_PHASEINC : out STD_LOGIC_VECTOR(11 downto 0);
+ INTERRUPT_ASSERTED : out STD_LOGIC;
+ RESET_MINMAX : out STD_LOGIC;
+ SWEEP_HALTED : in STD_LOGIC;
+ SWEEP_RESUME : out STD_LOGIC;
+
+ -- hardware overwrite signals
+ SPI_OVERWRITE_ENABLED : out STD_LOGIC;
+ SPI_OVERWRITE_DATA : out STD_LOGIC_VECTOR(14 downto 0);
+
+ -- DFT signals
+ DFT_BIN1_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
+ DFT_DIFFBIN_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
+ DFT_RESULT_READY : in STD_LOGIC;
+ DFT_OUTPUT : in STD_LOGIC_VECTOR (191 downto 0);
+ DFT_NEXT_OUTPUT : out STD_LOGIC;
+ DFT_ENABLE : out STD_LOGIC;
+
+ DEBUG_STATUS : in STD_LOGIC_VECTOR(10 downto 0));
+end SPICommands;
+
+architecture Behavioral of SPICommands is
+ COMPONENT spi_slave
+ Generic(W : integer;
+ PREWIDTH : integer);
+ PORT(
+ SPI_CLK : in STD_LOGIC;
+ MISO : out STD_LOGIC;
+ MOSI : in STD_LOGIC;
+ CS : in STD_LOGIC;
+ BUF_OUT : out STD_LOGIC_VECTOR (W-1 downto 0) := (others => '0');
+ BUF_IN : in STD_LOGIC_VECTOR (W-1 downto 0);
+ CLK : in STD_LOGIC;
+ COMPLETE : out STD_LOGIC;
+ PRE_COMPLETE : out STD_LOGIC;
+ PRE_BUF_OUT : out STD_LOGIC_VECTOR (PREWIDTH-1 downto 0)
+ );
+ END COMPONENT;
+
+ -- SPI control signals
+ signal spi_buf_out : std_logic_vector(15 downto 0);
+ signal spi_buf_in : std_logic_vector(15 downto 0);
+ signal spi_complete : std_logic;
+ signal spi_pre_complete : std_logic;
+ signal spi_pre_buf_out : std_logic_vector(2 downto 0);
+ signal word_cnt : integer range 0 to 19;
+ type SPI_states is (FirstWord, WriteSweepConfig, ReadResult, WriteRegister);
+ signal state : SPI_states;
+ signal selected_register : integer range 0 to 31;
+
+ signal dft_next : std_logic;
+
+ signal last_NSS : std_logic;
+
+ signal sweep_config_write : std_logic;
+ signal unread_sampling_data : std_logic;
+ signal data_overrun : std_logic;
+ -- Configuration registers
+ signal interrupt_mask : std_logic_vector(15 downto 0);
+ signal interrupt_status : std_logic_vector(15 downto 0);
+
+ signal latched_result : std_logic_vector(287 downto 0);
+ signal sweepconfig_buffer : std_logic_vector(79 downto 0);
+begin
+ SPI: spi_slave
+ GENERIC MAP(W => 16,
+ PREWIDTH => 3)
+ PORT MAP(
+ SPI_CLK => SCLK,
+ MISO => MISO,
+ MOSI => MOSI,
+ CS => NSS,
+ BUF_OUT => spi_buf_out,
+ BUF_IN => spi_buf_in,
+ CLK => CLK,
+ COMPLETE => spi_complete,
+ PRE_COMPLETE => spi_pre_complete,
+ PRE_BUF_OUT => spi_pre_buf_out
+ );
+
+ SWEEP_WRITE(0) <= sweep_config_write;
+ DFT_NEXT_OUTPUT <= dft_next;
+ DFT_ENABLE <= interrupt_mask(5);
+
+ process(CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ sweep_config_write <= '0';
+ data_overrun <= '0';
+ SWEEP_POINTS <= (others => '0');
+ NSAMPLES <= (others => '0');
+ --SETTLING_TIME <= (others => '0');
+ PORT1_EN <= '0';
+ PORT2_EN <= '0';
+ REF_EN <= '0';
+ AMP_SHDN <= '1';
+ SOURCE_RF_EN <= '0';
+ LO_RF_EN <= '0';
+ SOURCE_CE_EN <= '0';
+ LO_CE_EN <= '0';
+ PORTSWITCH_EN <= '0';
+ LEDS <= (others => '1');
+ WINDOW_SETTING <= "00";
+ unread_sampling_data <= '0';
+ interrupt_mask <= (others => '0');
+ ADC_PRESCALER <= std_logic_vector(to_unsigned(112, 8));
+ ADC_PHASEINC <= std_logic_vector(to_unsigned(1120, 12));
+ RESET_MINMAX <= '0';
+ INTERRUPT_ASSERTED <= '0';
+ latched_result <= (others => '0');
+
+ SPI_OVERWRITE_ENABLED <= '0';
+ SPI_OVERWRITE_DATA <= (others => '0');
+
+ DFT_BIN1_PHASEINC <= (others => '0');
+ DFT_DIFFBIN_PHASEINC <= (others => '0');
+ dft_next <= '0';
+ last_NSS <= '1';
+ else
+ interrupt_status <= DEBUG_STATUS(10 downto 1) & DFT_RESULT_READY & SWEEP_HALTED & data_overrun & unread_sampling_data & SOURCE_UNLOCKED & LO_UNLOCKED;
+ if (interrupt_status and interrupt_mask) = "0000000000000000" then
+ INTERRUPT_ASSERTED <= '0';
+ else
+ INTERRUPT_ASSERTED <= '1';
+ end if;
+ if sweep_config_write = '1' then
+ sweep_config_write <= '0';
+ end if;
+ if dft_next = '1' then
+ dft_next <= '0';
+ end if;
+ RESET_MINMAX <= '0';
+ SWEEP_RESUME <= '0';
+ if NEW_SAMPLING_DATA = '1' then
+ unread_sampling_data <= '1';
+ if unread_sampling_data = '1' then
+ data_overrun <= '1';
+ end if;
+ end if;
+ last_NSS <= NSS;
+ if NSS = '0' and last_NSS = '1' then
+ word_cnt <= 0;
+ spi_buf_in <= interrupt_status;
+ state <= FirstWord;
+ else
+ -- handle read operations when the first PREWIDTH bits are complete
+ if spi_pre_complete = '1' then
+ case state is
+ when FirstWord =>
+ -- initial word determines the action
+ case spi_pre_buf_out is
+ when "010" => state <= FirstWord;
+ spi_buf_in <= "1111000010100101";
+ when "101" => state <= ReadResult;-- can use same state as read result, but the latched data will contain the DFT values
+ latched_result(175 downto 0) <= DFT_OUTPUT(191 downto 16);
+ spi_buf_in <= DFT_OUTPUT(15 downto 0);
+ dft_next <= '1';
+ when "110" => state <= ReadResult;
+ latched_result <= SAMPLING_RESULT(303 downto 16);
+ spi_buf_in <= SAMPLING_RESULT(15 downto 0);
+ unread_sampling_data <= '0';
+ when "111" => state <= ReadResult; -- can use same state as read result, but the latched data will contain the min/max ADC values
+ latched_result(79 downto 0) <= ADC_MINMAX(95 downto 16);
+ spi_buf_in <= ADC_MINMAX(15 downto 0);
+ --ignore other options
+ when others =>
+ end case;
+ when ReadResult =>
+ -- pass on next word of latched result
+ spi_buf_in <= latched_result(15 downto 0);
+ latched_result <= "0000000000000000" & latched_result(287 downto 16);
+ when others =>
+ end case;
+ end if;
+ -- handle write operations when the whole word is complete
+ if spi_complete = '1' then
+ word_cnt <= word_cnt + 1;
+ case state is
+ when FirstWord =>
+ -- initial word determines action
+ case spi_buf_out(15 downto 13) is
+ when "000" => state <= WriteSweepConfig;
+ -- also extract the point number
+ SWEEP_ADDRESS <= spi_buf_out(12 downto 0);
+ when "001" => state <= FirstWord;
+ SWEEP_RESUME <= '1';
+ when "011" => state <= FirstWord;
+ RESET_MINMAX <= '1';
+ when "100" => state <= WriteRegister;
+ selected_register <= to_integer(unsigned(spi_buf_out(4 downto 0)));
+ -- ignore read options (already handled in other state machine)
+ when "010" =>
+ when "101" =>
+ when "110" =>
+ when "111" =>
+ when others => state <= FirstWord;
+ end case;
+ when WriteRegister =>
+ -- write received data into previously selected register
+ case selected_register is
+ when 0 => interrupt_mask <= spi_buf_out;
+ when 1 => SWEEP_POINTS <= spi_buf_out(12 downto 0);
+ when 2 => NSAMPLES <= spi_buf_out(12 downto 0);
+ when 3 => PORTSWITCH_EN <= spi_buf_out(0);
+ PORT1_EN <= spi_buf_out(15);
+ PORT2_EN <= spi_buf_out(14);
+ REF_EN <= spi_buf_out(13);
+ AMP_SHDN <= not spi_buf_out(12);
+ SOURCE_RF_EN <= spi_buf_out(11);
+ LO_RF_EN <= spi_buf_out(10);
+ LEDS <= not spi_buf_out(9 downto 7);
+ WINDOW_SETTING <= spi_buf_out(6 downto 5);
+ SOURCE_CE_EN <= spi_buf_out(4);
+ LO_CE_EN <= spi_buf_out(3);
+ SYNC_MASTER <= spi_buf_out(1);
+ when 4 => ADC_PRESCALER <= spi_buf_out(7 downto 0);
+ when 5 => ADC_PHASEINC <= spi_buf_out(11 downto 0);
+ when 6 => STAGES <= spi_buf_out(15 downto 13);
+ SYNC_ENABLED <= spi_buf_out(12);
+ PORT1_STAGE <= spi_buf_out(5 downto 3);
+ PORT2_STAGE <= spi_buf_out(2 downto 0);
+ when 7 => SPI_OVERWRITE_ENABLED <= spi_buf_out(15);
+ SPI_OVERWRITE_DATA <= spi_buf_out(14 downto 0);
+ when 8 => MAX2871_DEF_0(15 downto 0) <= spi_buf_out;
+ when 9 => MAX2871_DEF_0(31 downto 16) <= spi_buf_out;
+ when 10 => MAX2871_DEF_1(15 downto 0) <= spi_buf_out;
+ when 11 => MAX2871_DEF_1(31 downto 16) <= spi_buf_out;
+ when 12 => MAX2871_DEF_3(15 downto 0) <= spi_buf_out;
+ when 13 => MAX2871_DEF_3(31 downto 16) <= spi_buf_out;
+ when 14 => MAX2871_DEF_4(15 downto 0) <= spi_buf_out;
+ when 15 => MAX2871_DEF_4(31 downto 16) <= spi_buf_out;
+ when 18 => DFT_BIN1_PHASEINC <= spi_buf_out;
+ when 19 => DFT_DIFFBIN_PHASEINC <= spi_buf_out;
+ when 20 => SETTLING_TIME(15 downto 0) <= spi_buf_out;
+ when 21 => SETTLING_TIME(19 downto 16) <= spi_buf_out(3 downto 0);
+ when others =>
+ end case;
+ selected_register <= selected_register + 1;
+ when WriteSweepConfig =>
+ if word_cnt = 6 then
+ -- Sweep config data is complete pass on
+ SWEEP_DATA <= sweepconfig_buffer & spi_buf_out;
+ sweep_config_write <= '1';
+ else
+ -- shift next word into buffer
+ sweepconfig_buffer <= sweepconfig_buffer(63 downto 0) & spi_buf_out;
+ end if;
+ -- read already handled in pre_complete, ignore
+ when ReadResult =>
+ end case;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end Behavioral;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Sampling.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Sampling.vhd
new file mode 100644
index 0000000..0c752e2
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Sampling.vhd
@@ -0,0 +1,301 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:27:54 05/05/2020
+-- Design Name:
+-- Module Name: Sampling - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Sampling is
+ Generic(CLK_CYCLES_PRE_DONE : integer);
+ Port ( CLK : in STD_LOGIC;
+ RESET : in STD_LOGIC;
+ ADC_PRESCALER : in STD_LOGIC_VECTOR(7 downto 0);
+ PHASEINC : in STD_LOGIC_VECTOR(11 downto 0);
+ PORT1 : in STD_LOGIC_VECTOR (17 downto 0);
+ PORT2 : in STD_LOGIC_VECTOR (17 downto 0);
+ REF : in STD_LOGIC_VECTOR (17 downto 0);
+ ADC_START : out STD_LOGIC;
+ NEW_SAMPLE : in STD_LOGIC;
+ DONE : out STD_LOGIC;
+ PRE_DONE : out STD_LOGIC;
+ START : in STD_LOGIC;
+ SAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
+ PORT1_I : out STD_LOGIC_VECTOR (47 downto 0);
+ PORT1_Q : out STD_LOGIC_VECTOR (47 downto 0);
+ PORT2_I : out STD_LOGIC_VECTOR (47 downto 0);
+ PORT2_Q : out STD_LOGIC_VECTOR (47 downto 0);
+ REF_I : out STD_LOGIC_VECTOR (47 downto 0);
+ REF_Q : out STD_LOGIC_VECTOR (47 downto 0);
+ ACTIVE : out STD_LOGIC);
+end Sampling;
+
+architecture Behavioral of Sampling is
+COMPONENT SinCos
+ PORT (
+ clk : IN STD_LOGIC;
+ phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+ cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+ );
+END COMPONENT;
+COMPONENT DSP_SLICE
+ PORT (
+ clk : IN STD_LOGIC;
+ ce : IN STD_LOGIC;
+ sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+ p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+ );
+END COMPONENT;
+COMPONENT window
+PORT(
+ CLK : IN std_logic;
+ INDEX : IN std_logic_vector(6 downto 0);
+ WINDOW_TYPE : IN std_logic_vector(1 downto 0);
+ VALUE : OUT std_logic_vector(15 downto 0)
+ );
+END COMPONENT;
+
+ signal p1_I : std_logic_vector(47 downto 0);
+ signal p1_Q : std_logic_vector(47 downto 0);
+ signal p2_I : std_logic_vector(47 downto 0);
+ signal p2_Q : std_logic_vector(47 downto 0);
+ signal r_I : std_logic_vector(47 downto 0);
+ signal r_Q : std_logic_vector(47 downto 0);
+ signal clk_cnt : integer range 0 to 255;
+ signal sample_cnt : integer range 0 to 131071;
+ signal samples_to_take : integer range 0 to 131071;
+
+ signal phase : std_logic_vector(11 downto 0);
+ signal sine : std_logic_vector(15 downto 0);
+ signal cosine : std_logic_vector(15 downto 0);
+
+ signal mult_a : std_logic_vector(17 downto 0);
+ signal mult_b : std_logic_vector(17 downto 0);
+ signal mult_c : std_logic_vector(47 downto 0);
+ signal mult_p : std_logic_vector(47 downto 0);
+
+ signal mult_enable : std_logic;
+ signal mult_accumulate : std_logic_vector(0 downto 0);
+
+ type States is (Idle, Sampling, P1Q, P2I, P2Q, RI, RQ, SaveP1Q, SaveP2I, SaveP2Q, SaveRI, SaveRQ, Ready);
+ signal state : States;
+begin
+-- Always fails for simulation, comment out
+-- assert (phase_inc * CLK_FREQ / (4096*CLK_DIV) = IF_FREQ)
+-- report "Phase increment not exact"
+-- severity FAILURE;
+
+ LookupTable : SinCos
+ PORT MAP (
+ clk => CLK,
+ phase_in => phase,
+ cosine => cosine,
+ sine => sine
+ );
+
+ Mult : DSP_SLICE
+ PORT MAP (
+ clk => CLK,
+ ce => mult_enable,
+ sel => mult_accumulate,
+ a => mult_a,
+ b => mult_b,
+ c => mult_c,
+ p => mult_p
+ );
+
+ -- sign extend b input of multiplier (sin/cos)
+ mult_b(17 downto 16) <= mult_b(15) & mult_b(15);
+
+ process(CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ state <= Idle;
+ ADC_START <= '0';
+ DONE <= '0';
+ PRE_DONE <= '0';
+ ACTIVE <= '0';
+ clk_cnt <= 0;
+ sample_cnt <= 0;
+ phase <= (others => '0');
+ mult_enable <= '0';
+ mult_accumulate <= "0";
+ else
+ -- when not idle, generate pulses for ADCs
+ if state /= Idle then
+ if clk_cnt = unsigned(ADC_PRESCALER) - 1 then
+ if sample_cnt < samples_to_take then
+ ADC_START <= '1';
+ end if;
+ clk_cnt <= 0;
+ else
+ clk_cnt <= clk_cnt + 1;
+ ADC_START <= '0';
+ end if;
+ else
+ ADC_START <= '0';
+ end if;
+ -- handle state transitions
+ case state is
+ when Idle =>
+ sample_cnt <= 0;
+ DONE <= '0';
+ PRE_DONE <= '0';
+ ACTIVE <= '0';
+ clk_cnt <= 0;
+ phase <= (others => '0');
+ mult_enable <= '0';
+ mult_accumulate <= "0";
+ if START = '1' then
+ state <= Sampling;
+ samples_to_take <= to_integer(unsigned(SAMPLES & "0000"));
+ end if;
+ when Sampling =>
+ DONE <= '0';
+ PRE_DONE <= '0';
+ ACTIVE <= '1';
+ mult_enable <= '0';
+ if NEW_SAMPLE = '1' then
+ sample_cnt <= sample_cnt + 1;
+ mult_enable <= '1';
+ mult_a <= PORT1;
+ mult_b(15 downto 0) <= cosine;
+ mult_c <= p1_I;
+ state <= P1Q;
+ end if;
+ when P1Q =>
+ ACTIVE <= '1';
+ DONE <= '0';
+ PRE_DONE <= '0';
+ mult_enable <= '1';
+ mult_a <= PORT1;
+ mult_b(15 downto 0) <= sine;
+ mult_c <= p1_Q;
+ state <= P2I;
+ when P2I =>
+ ACTIVE <= '1';
+ DONE <= '0';
+ PRE_DONE <= '0';
+ mult_enable <= '1';
+ mult_a <= PORT2;
+ mult_b(15 downto 0) <= cosine;
+ mult_c <= p2_I;
+ state <= P2Q;
+ when P2Q =>
+ ACTIVE <= '1';
+ DONE <= '0';
+ PRE_DONE <= '0';
+ mult_enable <= '1';
+ mult_a <= PORT2;
+ mult_b(15 downto 0) <= sine;
+ mult_c <= p2_Q;
+ state <= RI;
+ when RI =>
+ ACTIVE <= '1';
+ DONE <= '0';
+ PRE_DONE <= '0';
+ mult_enable <= '1';
+ mult_a <= REF;
+ mult_b(15 downto 0) <= cosine;
+ mult_c <= r_I;
+ state <= RQ;
+ when RQ =>
+ ACTIVE <= '1';
+ DONE <= '0';
+ PRE_DONE <= '0';
+ mult_enable <= '1';
+ mult_a <= REF;
+ mult_b(15 downto 0) <= sine;
+ mult_c <= r_Q;
+ -- first result is available
+ p1_I <= mult_p;
+ state <= SaveP1Q;
+ when SaveP1Q =>
+ ACTIVE <= '1';
+ DONE <= '0';
+ PRE_DONE <= '0';
+ mult_enable <= '1';
+ p1_Q <= mult_p;
+ state <= SaveP2I;
+ when SaveP2I =>
+ ACTIVE <= '1';
+ DONE <= '0';
+ PRE_DONE <= '0';
+ mult_enable <= '1';
+ p2_I <= mult_p;
+ state <= SaveP2Q;
+ when SaveP2Q =>
+ ACTIVE <= '1';
+ DONE <= '0';
+ PRE_DONE <= '0';
+ mult_enable <= '1';
+ p2_Q <= mult_p;
+ state <= SaveRI;
+ when SaveRI =>
+ ACTIVE <= '1';
+ DONE <= '0';
+ PRE_DONE <= '0';
+ mult_enable <= '1';
+ r_I <= mult_p;
+ state <= SaveRQ;
+ when SaveRQ =>
+ ACTIVE <= '1';
+ DONE <= '0';
+ PRE_DONE <= '0';
+ mult_enable <= '0';
+ r_Q <= mult_p;
+ -- from now on accumulate results
+ mult_accumulate <= "1";
+ phase <= std_logic_vector(unsigned(phase) + unsigned(PHASEINC));
+ if sample_cnt < samples_to_take then
+ state <= Sampling;
+ else
+ state <= Ready;
+ end if;
+ when Ready =>
+ ACTIVE <= '1';
+ DONE <= '1';
+ PRE_DONE <= '1';
+ mult_enable <= '0';
+ PORT1_I <= p1_I;
+ PORT1_Q <= p1_Q;
+ PORT2_I <= p2_I;
+ PORT2_Q <= p2_Q;
+ REF_I <= r_I;
+ REF_Q <= r_Q;
+ state <= Idle;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end Behavioral;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Sweep.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Sweep.vhd
new file mode 100644
index 0000000..c2408ef
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Sweep.vhd
@@ -0,0 +1,272 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:35:02 05/06/2020
+-- Design Name:
+-- Module Name: Sweep - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Sweep is
+ Port ( CLK : in STD_LOGIC;
+ RESET : in STD_LOGIC;
+ NPOINTS : in STD_LOGIC_VECTOR (12 downto 0);
+ CONFIG_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
+ CONFIG_DATA : in STD_LOGIC_VECTOR (95 downto 0);
+ USER_NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
+ NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
+ SETTLING_TIME : in STD_LOGIC_VECTOR (19 downto 0);
+ SAMPLING_BUSY : in STD_LOGIC;
+ SAMPLING_DONE : in STD_LOGIC;
+ START_SAMPLING : out STD_LOGIC;
+ BAND_SELECT : out STD_LOGIC;
+ -- fixed part of source/LO registers
+ MAX2871_DEF_4 : in STD_LOGIC_VECTOR (31 downto 0);
+ MAX2871_DEF_3 : in STD_LOGIC_VECTOR (31 downto 0);
+ MAX2871_DEF_1 : in STD_LOGIC_VECTOR (31 downto 0);
+ MAX2871_DEF_0 : in STD_LOGIC_VECTOR (31 downto 0);
+ -- assembled source/LO registers
+ SOURCE_REG_4 : out STD_LOGIC_VECTOR (31 downto 0);
+ SOURCE_REG_3 : out STD_LOGIC_VECTOR (31 downto 0);
+ SOURCE_REG_1 : out STD_LOGIC_VECTOR (31 downto 0);
+ SOURCE_REG_0 : out STD_LOGIC_VECTOR (31 downto 0);
+ LO_REG_4 : out STD_LOGIC_VECTOR (31 downto 0);
+ LO_REG_3 : out STD_LOGIC_VECTOR (31 downto 0);
+ LO_REG_1 : out STD_LOGIC_VECTOR (31 downto 0);
+ LO_REG_0 : out STD_LOGIC_VECTOR (31 downto 0);
+ RELOAD_PLL_REGS : out STD_LOGIC;
+ PLL_RELOAD_DONE : in STD_LOGIC;
+ PLL_LOCKED : in STD_LOGIC;
+ SWEEP_HALTED : out STD_LOGIC;
+ SWEEP_RESUME : in STD_LOGIC;
+
+ SYNC_ENABLED : in STD_LOGIC;
+ SYNC_MASTER : in STD_LOGIC;
+ TRIGGER_IN : in STD_LOGIC;
+ TRIGGER_OUT : out STD_LOGIC;
+
+ NEW_DATA : out STD_LOGIC;
+
+ ATTENUATOR : out STD_LOGIC_VECTOR(6 downto 0);
+ SOURCE_FILTER : out STD_LOGIC_VECTOR(1 downto 0);
+
+ --SETTLING_TIME : in STD_LOGIC_VECTOR (15 downto 0);
+
+ STAGES : in STD_LOGIC_VECTOR (2 downto 0);
+ PORT1_STAGE : in STD_LOGIC_VECTOR (2 downto 0);
+ PORT2_STAGE : in STD_LOGIC_VECTOR (2 downto 0);
+
+ PORT1_ACTIVE : out STD_LOGIC;
+ PORT2_ACTIVE : out STD_LOGIC;
+
+ SOURCE_CE : out STD_LOGIC;
+
+ -- Debug signals
+ DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0);
+ RESULT_INDEX : out STD_LOGIC_VECTOR (15 downto 0)
+ );
+end Sweep;
+
+architecture Behavioral of Sweep is
+ signal point_cnt : unsigned(12 downto 0);
+ type Point_states is (WaitInitialLow, TriggerSetup, SettingUp, Settling, WaitTriggerHigh, Exciting, WaitTriggerLow, SamplingDone, NextPoint, Done);
+ signal state : Point_states;
+ signal settling_cnt : unsigned(19 downto 0);
+ signal stage_cnt : unsigned (2 downto 0);
+ signal config_reg : std_logic_vector(95 downto 0);
+ signal source_active : std_logic;
+begin
+
+ CONFIG_ADDRESS <= std_logic_vector(point_cnt);
+
+ -- assemble registers
+ -- source register 0: N divider and fractional division value
+ SOURCE_REG_0 <= MAX2871_DEF_0(31) & "000000000" & config_reg(93) & config_reg(5 downto 0) & config_reg(26 downto 15) & "000";
+ -- source register 1: Modulus value
+ SOURCE_REG_1 <= MAX2871_DEF_1(31 downto 15) & config_reg(38 downto 27) & "001";
+ -- source register 3: VCO selection
+ SOURCE_REG_3 <= config_reg(11 downto 6) & MAX2871_DEF_3(25 downto 3) & "011";
+ -- output power A from config, output B disabled
+ SOURCE_REG_4 <= MAX2871_DEF_4(31 downto 23) & config_reg(14 downto 12) & MAX2871_DEF_4(19 downto 9) & "000" & MAX2871_DEF_4(5) & config_reg(47 downto 46) & "100";
+
+ -- LO register 0: N divider and fractional division value
+ LO_REG_0 <= MAX2871_DEF_0(31) & "000000000" & config_reg(94) & config_reg(54 downto 49) & config_reg(75 downto 64) & "000";
+ -- LO register 1: Modulus value
+ LO_REG_1 <= MAX2871_DEF_1(31 downto 15) & config_reg(87 downto 76) & "001";
+ -- LO register 3: VCO selection
+ LO_REG_3 <= config_reg(60 downto 55) & MAX2871_DEF_3(25 downto 3) & "011";
+ -- both outputs enabled at +5dbm
+ LO_REG_4 <= MAX2871_DEF_4(31 downto 23) & config_reg(63 downto 61) & MAX2871_DEF_4(19 downto 9) & "111111100";
+
+ ATTENUATOR <= config_reg(45 downto 39);
+ SOURCE_FILTER <= config_reg(89 downto 88);
+ BAND_SELECT <= config_reg(48);
+ SOURCE_CE <= source_active;
+
+ NSAMPLES <= USER_NSAMPLES when config_reg(92 downto 90) = "000" else
+ std_logic_vector(to_unsigned(6, 13)) when config_reg(92 downto 90) = "001" else
+ std_logic_vector(to_unsigned(19, 13)) when config_reg(92 downto 90) = "010" else
+ std_logic_vector(to_unsigned(57, 13)) when config_reg(92 downto 90) = "011" else
+ std_logic_vector(to_unsigned(190, 13)) when config_reg(92 downto 90) = "100" else
+ std_logic_vector(to_unsigned(571, 13)) when config_reg(92 downto 90) = "101" else
+ std_logic_vector(to_unsigned(1904, 13)) when config_reg(92 downto 90) = "110" else
+ std_logic_vector(to_unsigned(5712, 13));
+
+ DEBUG_STATUS(10 downto 7) <= "0000" when state = TriggerSetup else
+ "0001" when state = SettingUp else
+ "0010" when state = Settling else
+ "0011" when state = WaitTriggerHigh else
+ "0100" when state = Exciting else
+ "0101" when state = WaitTriggerLow else
+ "0110" when state = SamplingDone else
+ "0111" when state = NextPoint else
+ "1000" when state = Done else
+ "1001";
+ DEBUG_STATUS(6) <= PLL_RELOAD_DONE;
+ DEBUG_STATUS(5) <= PLL_RELOAD_DONE and PLL_LOCKED;
+ DEBUG_STATUS(4) <= SAMPLING_BUSY;
+ DEBUG_STATUS(3) <= TRIGGER_IN;
+ DEBUG_STATUS(2) <= source_active;
+ DEBUG_STATUS(1 downto 0) <= (others => '1');
+
+ config_reg <= CONFIG_DATA;
+
+ process(CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ point_cnt <= (others => '0');
+ stage_cnt <= (others => '0');
+ state <= WaitInitialLow;
+ START_SAMPLING <= '0';
+ RELOAD_PLL_REGS <= '0';
+ SWEEP_HALTED <= '0';
+ RESULT_INDEX <= (others => '1');
+ PORT1_ACTIVE <= '0';
+ PORT2_ACTIVE <= '0';
+ TRIGGER_OUT <= '0';
+ source_active <= '0';
+ else
+ case state is
+ when WaitInitialLow =>
+ TRIGGER_OUT <= '0';
+ if TRIGGER_IN = '0' or SYNC_ENABLED = '0' then
+ state <= TriggerSetup;
+ end if;
+ when TriggerSetup =>
+ RELOAD_PLL_REGS <= '1';
+ if PLL_RELOAD_DONE = '0' then
+ state <= SettingUp;
+ end if;
+ when SettingUp =>
+ -- highest bit in config_reg determines whether the sweep should be halted prior to sampling
+ SWEEP_HALTED <= config_reg(95);
+ RELOAD_PLL_REGS <= '0';
+ settling_cnt <= unsigned(SETTLING_TIME);
+ if PLL_RELOAD_DONE = '1' and PLL_LOCKED = '1' then
+ -- check if halted sweep is resumed
+ if config_reg(95) = '0' or SWEEP_RESUME = '1' then
+ SWEEP_HALTED <= '0';
+ state <= Settling;
+ end if;
+ end if;
+ when Settling =>
+ NEW_DATA <= '0';
+ source_active <= '0';
+ if std_logic_vector(stage_cnt) = PORT1_STAGE then
+ PORT1_ACTIVE <= '1';
+ source_active <= '1';
+ else
+ PORT1_ACTIVE <= '0';
+ end if;
+ if std_logic_vector(stage_cnt) = PORT2_STAGE then
+ PORT2_ACTIVE <= '1';
+ source_active <= '1';
+ else
+ PORT2_ACTIVE <= '0';
+ end if;
+ -- wait for settling time to elapse
+ if settling_cnt > 0 then
+ settling_cnt <= settling_cnt - 1;
+ else
+ -- need to wait for the trigger
+ state <= WaitTriggerHigh;
+ if SYNC_MASTER = '1' then
+ -- this device generates the stimulus signal, it needs start the trigger itself
+ TRIGGER_OUT <= '1';
+ end if;
+ end if;
+ when WaitTriggerHigh =>
+ if TRIGGER_IN = '1' or SYNC_ENABLED = '0' then
+ TRIGGER_OUT <= SYNC_ENABLED; -- pass on trigger signal if enabled
+ START_SAMPLING <= '1';
+ if SAMPLING_BUSY = '1' then
+ state <= Exciting;
+ end if;
+ end if;
+ when Exciting =>
+ -- wait for sampling to finish
+ START_SAMPLING <= '0';
+ if SAMPLING_BUSY = '0' then
+ RESULT_INDEX <= std_logic_vector(stage_cnt) & std_logic_vector(point_cnt);
+ state <= WaitTriggerLow;
+ end if;
+ when WaitTriggerLow =>
+ NEW_DATA <= '0';
+ if SYNC_MASTER = '1' then
+ TRIGGER_OUT <= '0';
+ end if;
+ if TRIGGER_IN = '0' or SYNC_ENABLED = '0' then
+ TRIGGER_OUT <= '0';
+ state <= SamplingDone;
+ end if;
+ when SamplingDone =>
+ NEW_DATA <= '1';
+ if stage_cnt < unsigned(STAGES) then
+ stage_cnt <= stage_cnt + 1;
+ -- can go directly to preperation for next stage
+ state <= Settling;
+ else
+ state <= NextPoint;
+ end if;
+ settling_cnt <= unsigned(SETTLING_TIME);
+ when NextPoint =>
+ NEW_DATA <= '0';
+ if point_cnt < unsigned(NPOINTS) then
+ point_cnt <= point_cnt + 1;
+ stage_cnt <= (others => '0');
+ state <= TriggerSetup;
+ else
+ point_cnt <= (others => '0');
+ state <= Done;
+ TRIGGER_OUT <= '0';
+ end if;
+ when others =>
+ end case;
+ end if;
+ end if;
+ end process;
+end Behavioral;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Synchronizer.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Synchronizer.vhd
new file mode 100644
index 0000000..bc1a010
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Synchronizer.vhd
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 23:31:10 05/15/2020
+-- Design Name:
+-- Module Name: Synchronizer - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Synchronizer is
+ Generic(stages : integer);
+ Port ( CLK : in STD_LOGIC;
+ SYNC_IN : in STD_LOGIC;
+ SYNC_OUT : out STD_LOGIC);
+end Synchronizer;
+
+architecture Behavioral of Synchronizer is
+ signal sync_line : std_logic_vector(stages downto 0);
+begin
+
+ SYNC_OUT <= sync_line(stages);
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ sync_line <= sync_line(stages-1 downto 0) & SYNC_IN;
+ end if;
+ end process;
+
+end Behavioral;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_DFT.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_DFT.vhd
new file mode 100644
index 0000000..85ecc36
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_DFT.vhd
@@ -0,0 +1,133 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:25:23 09/18/2020
+-- Design Name:
+-- Module Name: /home/jan/Projekte/VNA2/FPGA/VNA/Test_DFT.vhd
+-- Project Name: VNA
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: DFT
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY Test_DFT IS
+END Test_DFT;
+
+ARCHITECTURE behavior OF Test_DFT IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT DFT
+ GENERIC(BINS : integer);
+ PORT(
+ CLK : IN std_logic;
+ RESET : IN std_logic;
+ PORT1 : IN std_logic_vector(17 downto 0);
+ PORT2 : IN std_logic_vector(17 downto 0);
+ NEW_SAMPLE : IN std_logic;
+ NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
+ BIN1_PHASEINC : IN std_logic_vector(15 downto 0);
+ DIFFBIN_PHASEINC : IN std_logic_vector(15 downto 0);
+ RESULT_READY : OUT std_logic;
+ OUTPUT : out STD_LOGIC_VECTOR (191 downto 0);
+ NEXT_OUTPUT : IN std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal CLK : std_logic := '0';
+ signal RESET : std_logic := '0';
+ signal PORT1 : std_logic_vector(17 downto 0) := (others => '0');
+ signal PORT2 : std_logic_vector(17 downto 0) := (others => '0');
+ signal NEW_SAMPLE : std_logic := '0';
+ signal BIN1_PHASEINC : std_logic_vector(15 downto 0) := (others => '0');
+ signal DIFFBIN_PHASEINC : std_logic_vector(15 downto 0) := (others => '0');
+ signal NEXT_OUTPUT : std_logic := '0';
+ signal NSAMPLES : STD_LOGIC_VECTOR (12 downto 0);
+
+ --Outputs
+ signal RESULT_READY : std_logic;
+ signal OUTPUT : STD_LOGIC_VECTOR (191 downto 0);
+
+ -- Clock period definitions
+ constant CLK_period : time := 10 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: DFT
+ GENERIC MAP(BINS => 64)
+ PORT MAP (
+ CLK => CLK,
+ RESET => RESET,
+ PORT1 => PORT1,
+ PORT2 => PORT2,
+ NEW_SAMPLE => NEW_SAMPLE,
+ NSAMPLES => NSAMPLES,
+ BIN1_PHASEINC => BIN1_PHASEINC,
+ DIFFBIN_PHASEINC => DIFFBIN_PHASEINC,
+ RESULT_READY => RESULT_READY,
+ OUTPUT => OUTPUT,
+ NEXT_OUTPUT => NEXT_OUTPUT
+ );
+
+ -- Clock process definitions
+ CLK_process :process
+ begin
+ CLK <= '0';
+ wait for CLK_period/2;
+ CLK <= '1';
+ wait for CLK_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ RESET <= '1';
+ PORT1 <= "100000000000000000";
+ PORT2 <= "010000000000000000";
+ BIN1_PHASEINC <= "0100000000000000";
+ DIFFBIN_PHASEINC <= "0010000000000000";
+ NSAMPLES <= "0000000000011";
+ wait for 100 ns;
+ RESET <= '0';
+ wait for CLK_period*10;
+ NEW_SAMPLE <= '1';
+ wait for CLK_period;
+ NEW_SAMPLE <= '0';
+ while True loop
+ wait for CLK_period * 79;
+ NEW_SAMPLE <= '1';
+ wait for CLK_period;
+ NEW_SAMPLE <= '0';
+ end loop;
+
+ wait;
+ end process;
+
+END;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_MAX2871.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_MAX2871.vhd
new file mode 100644
index 0000000..4180408
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_MAX2871.vhd
@@ -0,0 +1,127 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:46:34 05/07/2020
+-- Design Name:
+-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_MAX2871.vhd
+-- Project Name: VNA
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: MAX2871
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY Test_MAX2871 IS
+END Test_MAX2871;
+
+ARCHITECTURE behavior OF Test_MAX2871 IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT MAX2871
+ Generic (CLK_DIV : integer);
+ PORT(
+ CLK : IN std_logic;
+ RESET : IN std_logic;
+ REG4 : IN std_logic_vector(31 downto 0);
+ REG3 : IN std_logic_vector(31 downto 0);
+ REG1 : IN std_logic_vector(31 downto 0);
+ REG0 : IN std_logic_vector(31 downto 0);
+ RELOAD : IN std_logic;
+ CLK_OUT : OUT std_logic;
+ MOSI : OUT std_logic;
+ LE : OUT std_logic;
+ DONE : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal CLK : std_logic := '0';
+ signal RESET : std_logic := '0';
+ signal REG4 : std_logic_vector(31 downto 0) := (others => '0');
+ signal REG3 : std_logic_vector(31 downto 0) := (others => '0');
+ signal REG1 : std_logic_vector(31 downto 0) := (others => '0');
+ signal REG0 : std_logic_vector(31 downto 0) := (others => '0');
+ signal RELOAD : std_logic := '0';
+
+ --Outputs
+ signal CLK_OUT : std_logic;
+ signal MOSI : std_logic;
+ signal LE : std_logic;
+ signal DONE : std_logic;
+
+ -- Clock period definitions
+ constant CLK_period : time := 6.25 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: MAX2871
+ GENERIC MAP(CLK_DIV => 10)
+ PORT MAP (
+ CLK => CLK,
+ RESET => RESET,
+ REG4 => REG4,
+ REG3 => REG3,
+ REG1 => REG1,
+ REG0 => REG0,
+ RELOAD => RELOAD,
+ CLK_OUT => CLK_OUT,
+ MOSI => MOSI,
+ LE => LE,
+ DONE => DONE
+ );
+
+ -- Clock process definitions
+ CLK_process :process
+ begin
+ CLK <= '0';
+ wait for CLK_period/2;
+ CLK <= '1';
+ wait for CLK_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ RESET <= '1';
+ wait for 100 ns;
+ RESET <= '0';
+ wait for CLK_period*10;
+
+ -- insert stimulus here
+ REG4 <= "11111111000000001111111100000000";
+ REG3 <= "11110000111100001111000011110000";
+ REG1 <= "11001100110011001100110011001100";
+ REG0 <= "10101010101010101010101010101010";
+ RELOAD <= '1';
+ wait for CLK_period;
+ RELOAD <= '0';
+ wait;
+ end process;
+
+END;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_MCP33131.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_MCP33131.vhd
new file mode 100644
index 0000000..c3f8214
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_MCP33131.vhd
@@ -0,0 +1,123 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:27:40 05/05/2020
+-- Design Name:
+-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_MCP33131.vhd
+-- Project Name: VNA
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: MCP33131
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY Test_MCP33131 IS
+END Test_MCP33131;
+
+ARCHITECTURE behavior OF Test_MCP33131 IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT MCP33131
+ Generic(CLK_DIV : integer;
+ CONVCYCLES : integer);
+ PORT(
+ CLK : IN std_logic;
+ RESET : IN std_logic;
+ START : IN std_logic;
+ READY : OUT std_logic;
+ DATA : OUT std_logic_vector(15 downto 0);
+ MIN : out STD_LOGIC_VECTOR (15 downto 0);
+ MAX : out STD_LOGIC_VECTOR (15 downto 0);
+ RESET_MINMAX : in STD_LOGIC;
+ SDO : IN std_logic;
+ CONVSTART : OUT std_logic;
+ SCLK : INOUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal CLK : std_logic := '0';
+ signal RESET : std_logic := '0';
+ signal START : std_logic := '0';
+ signal SDO : std_logic := '0';
+ signal RESET_MINMAX : STD_LOGIC := '0';
+
+ --Outputs
+ signal READY : std_logic;
+ signal DATA : std_logic_vector(15 downto 0);
+ signal CONVSTART : std_logic;
+ signal SCLK : std_logic;
+
+ -- Clock period definitions
+ constant CLK_period : time := 9.765 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: MCP33131
+ GENERIC MAP(CLK_DIV => 2,
+ CONVCYCLES => 77)
+ PORT MAP (
+ CLK => CLK,
+ RESET => RESET,
+ START => START,
+ READY => READY,
+ DATA => DATA,
+ RESET_MINMAX => RESET_MINMAX,
+ SDO => SDO,
+ CONVSTART => CONVSTART,
+ SCLK => SCLK
+ );
+
+ -- Clock process definitions
+ CLK_process :process
+ begin
+ CLK <= '0';
+ wait for CLK_period/2;
+ CLK <= '1';
+ wait for CLK_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ RESET <= '1';
+ wait for CLK_period*10.5;
+ RESET <= '0';
+ wait for CLK_period*10;
+
+ -- insert stimulus here
+ while True loop
+ wait for CLK_period*111;
+ START <= '1';
+ wait for CLK_period;
+ START <= '0';
+ end loop;
+ wait;
+ end process;
+
+END;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_PLL.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_PLL.vhd
new file mode 100644
index 0000000..642f15a
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_PLL.vhd
@@ -0,0 +1,99 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:58:50 05/08/2020
+-- Design Name:
+-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_PLL.vhd
+-- Project Name: VNA
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: PLL
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY Test_PLL IS
+END Test_PLL;
+
+ARCHITECTURE behavior OF Test_PLL IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT PLL
+ PORT(
+ CLK_IN1 : IN std_logic;
+ CLK_OUT1 : OUT std_logic;
+ RESET : IN std_logic;
+ LOCKED : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal CLK_IN1 : std_logic := '0';
+ signal RESET : std_logic := '0';
+
+ --Outputs
+ signal CLK_OUT1 : std_logic;
+ signal LOCKED : std_logic;
+
+ -- Clock period definitions
+ constant CLK_IN1_period : time := 20 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: PLL PORT MAP (
+ CLK_IN1 => CLK_IN1,
+ CLK_OUT1 => CLK_OUT1,
+ RESET => RESET,
+ LOCKED => LOCKED
+ );
+
+ -- Clock process definitions
+ CLK_IN1_process :process
+ begin
+ CLK_IN1 <= '0';
+ wait for CLK_IN1_period/2;
+ CLK_IN1 <= '1';
+ wait for CLK_IN1_period/2;
+ end process;
+
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ RESET <= '1';
+ wait for 100 ns;
+ RESET <= '0';
+
+ wait for CLK_IN1_period*10;
+
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_SPI.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_SPI.vhd
new file mode 100644
index 0000000..953a47f
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_SPI.vhd
@@ -0,0 +1,237 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:32:41 05/15/2020
+-- Design Name:
+-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SPI.vhd
+-- Project Name: VNA
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: spi_slave
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY Test_SPI IS
+END Test_SPI;
+
+ARCHITECTURE behavior OF Test_SPI IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT spi_slave
+ GENERIC(W : integer;
+ PREWIDTH : integer);
+ PORT(
+ SPI_CLK : IN std_logic;
+ MISO : OUT std_logic;
+ MOSI : IN std_logic;
+ CS : IN std_logic;
+ BUF_OUT : OUT std_logic_vector(W-1 downto 0);
+ BUF_IN : IN std_logic_vector(W-1 downto 0);
+ CLK : IN std_logic;
+ COMPLETE : OUT std_logic;
+ PRE_COMPLETE : out STD_LOGIC;
+ PRE_BUF_OUT : out STD_LOGIC_VECTOR (PREWIDTH-1 downto 0)
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal SPI_CLK : std_logic := '0';
+ signal MOSI : std_logic := '0';
+ signal CS : std_logic := '0';
+ signal BUF_IN : std_logic_vector(15 downto 0) := (others => '0');
+ signal CLK : std_logic := '0';
+
+ --Outputs
+ signal MISO : std_logic;
+ signal BUF_OUT : std_logic_vector(15 downto 0);
+ signal COMPLETE : std_logic;
+ signal PRE_COMPLETE : std_logic;
+ signal PRE_BUF_OUT : std_logic_vector(2 downto 0);
+
+ -- Clock period definitions
+ constant CLK_period : time := 9.765625 ns;
+ constant SPI_CLK_period : time := 25 ns;
+
+ signal data_signal : std_logic_vector(15 downto 0);
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: spi_slave
+ GENERIC MAP(W => 16, PREWIDTH => 3)
+ PORT MAP (
+ SPI_CLK => SPI_CLK,
+ MISO => MISO,
+ MOSI => MOSI,
+ CS => CS,
+ BUF_OUT => BUF_OUT,
+ BUF_IN => BUF_IN,
+ CLK => CLK,
+ COMPLETE => COMPLETE,
+ PRE_COMPLETE => PRE_COMPLETE,
+ PRE_BUF_OUT => PRE_BUF_OUT
+ );
+
+ -- Clock process definitions
+
+ CLK_process :process
+ begin
+ CLK <= '0';
+ wait for CLK_period/2;
+ CLK <= '1';
+ wait for CLK_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ procedure SPI(data : std_logic_vector(15 downto 0)) is
+ begin
+ MOSI <= data(15);
+ data_signal <= data(14 downto 0) & "0";
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '1';
+ wait for SPI_CLK_period/2;
+ SPI_CLK <= '0';
+ end procedure SPI;
+
+ begin
+ -- hold reset state for 100 ns.
+ CS <= '1';
+ wait for 100 ns;
+
+ wait for CLK_period*10;
+ BUF_IN <= "1111000010100101";
+ -- insert stimulus here
+ wait for CLK_period*10;
+ CS <= '0';
+ SPI("0101010101010101");
+ CS <= '1';
+
+ wait for CLK_period*10;
+ BUF_IN <= "0000111100001111";
+ wait for CLK_period*10;
+ CS <= '0';
+ SPI("0101010101010101");
+ BUF_IN <= "1010101010101010";
+ wait for SPI_CLK_period/2;
+ SPI("1100110011001100");
+ CS <= '1';
+
+ wait;
+ end process;
+
+END;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_SPICommands.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_SPICommands.vhd
new file mode 100644
index 0000000..eef0cf4
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_SPICommands.vhd
@@ -0,0 +1,363 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:42:26 05/07/2020
+-- Design Name:
+-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SPICommands.vhd
+-- Project Name: VNA
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: SPICommands
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY Test_SPICommands IS
+END Test_SPICommands;
+
+ARCHITECTURE behavior OF Test_SPICommands IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT SPICommands
+ PORT(
+ CLK : in STD_LOGIC;
+ RESET : in STD_LOGIC;
+ SCLK : in STD_LOGIC;
+ MOSI : in STD_LOGIC;
+ MISO : out STD_LOGIC;
+ NSS : in STD_LOGIC;
+ NEW_SAMPLING_DATA : in STD_LOGIC;
+ SAMPLING_RESULT : in STD_LOGIC_VECTOR (303 downto 0);
+ ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
+ SOURCE_UNLOCKED : in STD_LOGIC;
+ LO_UNLOCKED : in STD_LOGIC;
+ MAX2871_DEF_4 : out STD_LOGIC_VECTOR (31 downto 0);
+ MAX2871_DEF_3 : out STD_LOGIC_VECTOR (31 downto 0);
+ MAX2871_DEF_1 : out STD_LOGIC_VECTOR (31 downto 0);
+ MAX2871_DEF_0 : out STD_LOGIC_VECTOR (31 downto 0);
+ SWEEP_DATA : out STD_LOGIC_VECTOR (95 downto 0);
+ SWEEP_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
+ SWEEP_WRITE : out STD_LOGIC_VECTOR (0 downto 0);
+ SWEEP_POINTS : out STD_LOGIC_VECTOR (12 downto 0);
+ NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
+ STAGES : out STD_LOGIC_VECTOR (2 downto 0);
+ SETTLING_TIME : out STD_LOGIC_VECTOR (19 downto 0);
+ SYNC_ENABLED : out STD_LOGIC;
+ SYNC_MASTER : out STD_LOGIC;
+ PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
+ PORT2_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
+ PORT1_EN : out STD_LOGIC;
+ PORT2_EN : out STD_LOGIC;
+ REF_EN : out STD_LOGIC;
+ AMP_SHDN : out STD_LOGIC;
+ SOURCE_RF_EN : out STD_LOGIC;
+ LO_RF_EN : out STD_LOGIC;
+ SOURCE_CE_EN : out STD_LOGIC;
+ LO_CE_EN : out STD_LOGIC;
+ PORTSWITCH_EN : out STD_LOGIC;
+ LEDS : out STD_LOGIC_VECTOR(2 downto 0);
+ WINDOW_SETTING : out STD_LOGIC_VECTOR(1 downto 0);
+ ADC_PRESCALER : out STD_LOGIC_VECTOR(7 downto 0);
+ ADC_PHASEINC : out STD_LOGIC_VECTOR(11 downto 0);
+ INTERRUPT_ASSERTED : out STD_LOGIC;
+ RESET_MINMAX : out STD_LOGIC;
+ SWEEP_HALTED : in STD_LOGIC;
+ SWEEP_RESUME : out STD_LOGIC;
+
+ -- hardware overwrite signals
+ SPI_OVERWRITE_ENABLED : out STD_LOGIC;
+ SPI_OVERWRITE_DATA : out STD_LOGIC_VECTOR(14 downto 0);
+
+ -- DFT signals
+ DFT_BIN1_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
+ DFT_DIFFBIN_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
+ DFT_RESULT_READY : in STD_LOGIC;
+ DFT_OUTPUT : in STD_LOGIC_VECTOR (191 downto 0);
+ DFT_NEXT_OUTPUT : out STD_LOGIC;
+ DFT_ENABLE : out STD_LOGIC;
+
+ DEBUG_STATUS : in STD_LOGIC_VECTOR(10 downto 0)
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal CLK : std_logic := '0';
+ signal RESET : std_logic := '0';
+ signal SCLK : std_logic := '0';
+ signal MOSI : std_logic := '0';
+ signal NSS : std_logic := '0';
+ signal NEW_SAMPLING_DATA : std_logic := '0';
+ signal SAMPLING_RESULT : std_logic_vector(303 downto 0) := (others => '0');
+ signal SOURCE_UNLOCKED : std_logic := '1';
+ signal LO_UNLOCKED : std_logic := '1';
+
+ --Outputs
+ signal MISO : std_logic;
+ signal MAX2871_DEF_4 : std_logic_vector(31 downto 0);
+ signal MAX2871_DEF_3 : std_logic_vector(31 downto 0);
+ signal MAX2871_DEF_1 : std_logic_vector(31 downto 0);
+ signal MAX2871_DEF_0 : std_logic_vector(31 downto 0);
+ signal SWEEP_DATA : std_logic_vector(95 downto 0);
+ signal SWEEP_ADDRESS : std_logic_vector(12 downto 0);
+ signal SWEEP_WRITE : std_logic_vector(0 downto 0);
+ signal SWEEP_POINTS : std_logic_vector(12 downto 0);
+ signal NSAMPLES : std_logic_vector(12 downto 0);
+ signal PORT1_EN : std_logic;
+ signal PORT2_EN : std_logic;
+ signal REF_EN : std_logic;
+ signal AMP_SHDN : std_logic;
+ signal SOURCE_RF_EN : std_logic;
+ signal LO_RF_EN : std_logic;
+ signal LEDS : std_logic_vector(2 downto 0);
+ signal INTERRUPT_ASSERTED : std_logic;
+
+ -- Clock period definitions
+ constant CLK_period : time := 9.765625 ns;
+ constant SPI_CLK_period : time := 23.52941176 ns;
+
+ signal data_signal : std_logic_vector(15 downto 0);
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: SPICommands PORT MAP (
+ CLK => CLK,
+ RESET => RESET,
+ SCLK => SCLK,
+ MOSI => MOSI,
+ MISO => MISO,
+ NSS => NSS,
+ NEW_SAMPLING_DATA => NEW_SAMPLING_DATA,
+ SAMPLING_RESULT => SAMPLING_RESULT,
+ ADC_MINMAX => (others => '0'),
+ SOURCE_UNLOCKED => SOURCE_UNLOCKED,
+ LO_UNLOCKED => LO_UNLOCKED,
+ MAX2871_DEF_4 => MAX2871_DEF_4,
+ MAX2871_DEF_3 => MAX2871_DEF_3,
+ MAX2871_DEF_1 => MAX2871_DEF_1,
+ MAX2871_DEF_0 => MAX2871_DEF_0,
+ SWEEP_DATA => SWEEP_DATA,
+ SWEEP_ADDRESS => SWEEP_ADDRESS,
+ SWEEP_WRITE => SWEEP_WRITE,
+ SWEEP_POINTS => SWEEP_POINTS,
+ NSAMPLES => NSAMPLES,
+ PORT1_EN => PORT1_EN,
+ PORT2_EN => PORT2_EN,
+ REF_EN => REF_EN,
+ AMP_SHDN => AMP_SHDN,
+ SOURCE_RF_EN => SOURCE_RF_EN,
+ LO_RF_EN => LO_RF_EN,
+ LEDS => LEDS,
+ INTERRUPT_ASSERTED => INTERRUPT_ASSERTED,
+ SWEEP_HALTED => '0',
+ DFT_RESULT_READY => '0',
+ DFT_OUTPUT => (others => '0'),
+ DEBUG_STATUS => (others => '0')
+ );
+
+ -- Clock process definitions
+ CLK_process :process
+ begin
+ CLK <= '0';
+ wait for CLK_period/2;
+ CLK <= '1';
+ wait for CLK_period/2;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ procedure SPI(data : std_logic_vector(15 downto 0)) is
+ begin
+ MOSI <= data(15);
+ data_signal <= data(14 downto 0) & "0";
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ MOSI <= data_signal(15);
+ data_signal <= data_signal(14 downto 0) & '0';
+ wait for SPI_CLK_period/2;
+ SCLK <= '1';
+ wait for SPI_CLK_period/2;
+ SCLK <= '0';
+ end procedure SPI;
+ begin
+ -- hold reset state for 100 ns.
+ RESET <= '1';
+ NSS <= '1';
+ wait for 100 ns;
+ RESET <= '0';
+ wait for CLK_period*10;
+ -- read static test register
+ NSS <= '0';
+ SPI("0100000000000000");
+ SPI("0000000000000000");
+ NSS <= '1';
+
+ wait for CLK_period*50;
+ -- write register 3 = 0xFFFF (enable all periphery)
+ NSS <= '0';
+ SPI("1000000000000011");
+ SPI("1111111111111111");
+ NSS <= '1';
+
+ wait for CLK_period*50;
+ -- set sampling result and read first 4 words
+ SAMPLING_RESULT(63 downto 0) <= "1111000011110000101010101010101001010101010101010000111100001111";
+ NSS <= '0';
+ SPI("1100000000000000");
+ SPI("0000000000000000");
+ SPI("0000000000000000");
+ SPI("0000000000000000");
+ SPI("0000000000000000");
+ NSS <= '1';
+
+ wait for CLK_period*50;
+ -- insert stimulus here
+ -- write number of points
+ NSS <= '0';
+ SPI("1000000000000001");
+ SPI("1111000011110000");
+ NSS <= '1';
+
+ wait for CLK_period*100;
+ -- Write sweep config
+ NSS <= '0';
+ SPI("0000000000001011");
+ SPI("1111111100000000");
+ SPI("1111000011110000");
+ SPI("1100110011001100");
+ SPI("1010101010101010");
+ SPI("1101101101101101");
+ SPI("1110111011101110");
+ SPI("1111101111101111");
+ NSS <= '1';
+
+ wait for CLK_period*50;
+ NEW_SAMPLING_DATA <= '1';
+ wait for CLK_period;
+ NEW_SAMPLING_DATA <= '0';
+ wait for CLK_period*20;
+ NSS <= '0';
+ SPI("1100000000000000");
+ NSS <= '1';
+
+ wait for CLK_period*50;
+ NEW_SAMPLING_DATA <= '1';
+ wait for CLK_period;
+ NEW_SAMPLING_DATA <= '0';
+ wait for CLK_period*20;
+ NSS <= '0';
+ SPI("1100000000000000");
+ NSS <= '1';
+
+
+ wait;
+ end process;
+
+END;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_Sampling.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_Sampling.vhd
new file mode 100644
index 0000000..b56f330
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_Sampling.vhd
@@ -0,0 +1,161 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:40:38 05/05/2020
+-- Design Name:
+-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_Sampling.vhd
+-- Project Name: VNA
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: Sampling
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY Test_Sampling IS
+END Test_Sampling;
+
+ARCHITECTURE behavior OF Test_Sampling IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT Sampling
+ Generic(CLK_CYCLES_PRE_DONE : integer);
+ PORT(
+ CLK : IN std_logic;
+ RESET : IN std_logic;
+ ADC_PRESCALER : IN std_logic_vector(7 downto 0);
+ PHASEINC : IN std_logic_vector(11 downto 0);
+ PORT1 : IN std_logic_vector(17 downto 0);
+ PORT2 : IN std_logic_vector(17 downto 0);
+ REF : IN std_logic_vector(17 downto 0);
+ NEW_SAMPLE : IN std_logic;
+ START : IN std_logic;
+ SAMPLES : IN std_logic_vector(12 downto 0);
+ ADC_START : OUT std_logic;
+ DONE : OUT std_logic;
+ PRE_DONE : OUT std_logic;
+ PORT1_I : OUT std_logic_vector(47 downto 0);
+ PORT1_Q : OUT std_logic_vector(47 downto 0);
+ PORT2_I : OUT std_logic_vector(47 downto 0);
+ PORT2_Q : OUT std_logic_vector(47 downto 0);
+ REF_I : OUT std_logic_vector(47 downto 0);
+ REF_Q : OUT std_logic_vector(47 downto 0);
+ ACTIVE : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal CLK : std_logic := '0';
+ signal RESET : std_logic := '0';
+ signal PORT1 : std_logic_vector(17 downto 0) := (others => '0');
+ signal PORT2 : std_logic_vector(17 downto 0) := (others => '0');
+ signal REF : std_logic_vector(17 downto 0) := (others => '0');
+ signal NEW_SAMPLE : std_logic := '0';
+ signal START : std_logic := '0';
+ signal SAMPLES : std_logic_vector(12 downto 0) := (others => '0');
+ signal ADC_PRESCALER : std_logic_vector(7 downto 0);
+ signal PHASEINC : std_logic_vector(11 downto 0);
+ --Outputs
+ signal ADC_START : std_logic;
+ signal DONE : std_logic;
+ signal PRE_DONE : std_logic;
+ signal PORT1_I : std_logic_vector(47 downto 0);
+ signal PORT1_Q : std_logic_vector(47 downto 0);
+ signal PORT2_I : std_logic_vector(47 downto 0);
+ signal PORT2_Q : std_logic_vector(47 downto 0);
+ signal REF_I : std_logic_vector(47 downto 0);
+ signal REF_Q : std_logic_vector(47 downto 0);
+
+ -- Clock period definitions
+ constant CLK_period : time := 6.25 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: Sampling
+ Generic MAP(CLK_CYCLES_PRE_DONE => 0)
+ PORT MAP (
+ CLK => CLK,
+ RESET => RESET,
+ ADC_PRESCALER => ADC_PRESCALER,
+ PHASEINC => PHASEINC,
+ PORT1 => PORT1,
+ PORT2 => PORT2,
+ REF => REF,
+ NEW_SAMPLE => NEW_SAMPLE,
+ START => START,
+ SAMPLES => SAMPLES,
+ ADC_START => ADC_START,
+ DONE => DONE,
+ PRE_DONE => PRE_DONE,
+ PORT1_I => PORT1_I,
+ PORT1_Q => PORT1_Q,
+ PORT2_I => PORT2_I,
+ PORT2_Q => PORT2_Q,
+ REF_I => REF_I,
+ REF_Q => REF_Q,
+ ACTIVE => open
+ );
+
+ -- Clock process definitions
+ CLK_process :process
+ begin
+ CLK <= '0';
+ wait for CLK_period/2;
+ CLK <= '1';
+ wait for CLK_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ RESET <= '1';
+ wait for 100 ns;
+ RESET <= '0';
+ wait for CLK_period*10;
+
+ -- insert stimulus here
+ ADC_PRESCALER <= "011110000";
+ PHASEINC <= "010001100000";
+ PORT1 <= "000001111111111111";
+ PORT2 <= "000011111111111111";
+ REF <= "000111111111111111";
+ SAMPLES <= "0000000000001";
+ START <= '1';
+ while True loop
+ wait until ADC_START = '1';
+ START <= '0';
+ wait for CLK_period * 110;
+ NEW_SAMPLE <= '1';
+ wait for CLK_period;
+ NEW_SAMPLE <= '0';
+ end loop;
+ wait;
+
+ end process;
+
+END;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_SinCos.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_SinCos.vhd
new file mode 100644
index 0000000..6457c8d
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_SinCos.vhd
@@ -0,0 +1,104 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 09:16:15 05/14/2020
+-- Design Name:
+-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SinCos.vhd
+-- Project Name: VNA
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: SinCos
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY Test_SinCos IS
+END Test_SinCos;
+
+ARCHITECTURE behavior OF Test_SinCos IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT SinCos
+ PORT(
+ clk : IN std_logic;
+ phase_in : IN std_logic_vector(11 downto 0);
+ cosine : OUT std_logic_vector(15 downto 0);
+ sine : OUT std_logic_vector(15 downto 0)
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk : std_logic := '0';
+ signal phase_in : std_logic_vector(11 downto 0) := (others => '0');
+
+ --Outputs
+ signal cosine : std_logic_vector(15 downto 0);
+ signal sine : std_logic_vector(15 downto 0);
+
+ -- Clock period definitions
+ constant clk_period : time := 10 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: SinCos PORT MAP (
+ clk => clk,
+ phase_in => phase_in,
+ cosine => cosine,
+ sine => sine
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+
+ wait for clk_period*10;
+
+ -- insert stimulus here
+ phase_in <= "000000000000";
+ wait for clk_period*10;
+ phase_in <= "000000000001";
+ wait for clk_period*10;
+ phase_in <= "000000000010";
+ wait for clk_period*10;
+ phase_in <= "000000000011";
+ wait for clk_period*10;
+ phase_in <= "000000000100";
+ wait;
+ end process;
+
+END;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_Window.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_Window.vhd
new file mode 100644
index 0000000..fc53c7f
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_Window.vhd
@@ -0,0 +1,106 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:39:25 09/16/2020
+-- Design Name:
+-- Module Name: /home/jan/Projekte/VNA2/FPGA/VNA/Test_Window.vhd
+-- Project Name: VNA
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: window
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY Test_Window IS
+END Test_Window;
+
+ARCHITECTURE behavior OF Test_Window IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT window
+ PORT(
+ CLK : IN std_logic;
+ INDEX : IN std_logic_vector(6 downto 0);
+ WINDOW_TYPE : IN std_logic_vector(1 downto 0);
+ VALUE : OUT std_logic_vector(15 downto 0)
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal CLK : std_logic := '0';
+ signal INDEX : std_logic_vector(6 downto 0) := (others => '0');
+ signal WINDOW_TYPE : std_logic_vector(1 downto 0) := (others => '0');
+
+ --Outputs
+ signal VALUE : std_logic_vector(15 downto 0);
+
+ -- Clock period definitions
+ constant CLK_period : time := 10 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: window PORT MAP (
+ CLK => CLK,
+ INDEX => INDEX,
+ WINDOW_TYPE => WINDOW_TYPE,
+ VALUE => VALUE
+ );
+
+ -- Clock process definitions
+ CLK_process :process
+ begin
+ CLK <= '0';
+ wait for CLK_period/2;
+ CLK <= '1';
+ wait for CLK_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+ WINDOW_TYPE <= "00";
+ INDEX <= "0000000";
+ wait for CLK_period*10;
+
+ WINDOW_TYPE <= "10";
+ -- insert stimulus here
+ wait for CLK_period*10;
+ INDEX <= "0000001";
+ wait for CLK_period*10;
+ INDEX <= "0000010";
+ wait for CLK_period*10;
+ INDEX <= "0000011";
+ wait for CLK_period*10;
+ INDEX <= "0000100";
+
+ wait;
+ end process;
+
+END;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_Windowing.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_Windowing.vhd
new file mode 100644
index 0000000..398db59
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Test_Windowing.vhd
@@ -0,0 +1,135 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:37:51 11/06/2020
+-- Design Name:
+-- Module Name: /home/jan/Projekte/VNA2/FPGA/VNA/Test_Windowing.vhd
+-- Project Name: VNA
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: Windowing
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY Test_Windowing IS
+END Test_Windowing;
+
+ARCHITECTURE behavior OF Test_Windowing IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT Windowing
+ PORT(
+ CLK : IN std_logic;
+ RESET : IN std_logic;
+ WINDOW_TYPE : IN std_logic_vector(1 downto 0);
+ PORT1_RAW : IN std_logic_vector(15 downto 0);
+ PORT2_RAW : IN std_logic_vector(15 downto 0);
+ REF_RAW : IN std_logic_vector(15 downto 0);
+ ADC_READY : IN std_logic;
+ PORT1_WINDOWED : OUT std_logic_vector(17 downto 0);
+ PORT2_WINDOWED : OUT std_logic_vector(17 downto 0);
+ REF_WINDOWED : OUT std_logic_vector(17 downto 0);
+ WINDOWING_DONE : OUT std_logic;
+ NSAMPLES : IN std_logic_vector(12 downto 0)
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal CLK : std_logic := '0';
+ signal RESET : std_logic := '0';
+ signal WINDOW_TYPE : std_logic_vector(1 downto 0) := (others => '0');
+ signal PORT1_RAW : std_logic_vector(15 downto 0) := (others => '0');
+ signal PORT2_RAW : std_logic_vector(15 downto 0) := (others => '0');
+ signal REF_RAW : std_logic_vector(15 downto 0) := (others => '0');
+ signal ADC_READY : std_logic := '0';
+ signal NSAMPLES : std_logic_vector(12 downto 0) := (others => '0');
+
+ --Outputs
+ signal PORT1_WINDOWED : std_logic_vector(17 downto 0);
+ signal PORT2_WINDOWED : std_logic_vector(17 downto 0);
+ signal REF_WINDOWED : std_logic_vector(17 downto 0);
+ signal WINDOWING_DONE : std_logic;
+
+ -- Clock period definitions
+ constant CLK_period : time := 10 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: Windowing PORT MAP (
+ CLK => CLK,
+ RESET => RESET,
+ WINDOW_TYPE => WINDOW_TYPE,
+ PORT1_RAW => PORT1_RAW,
+ PORT2_RAW => PORT2_RAW,
+ REF_RAW => REF_RAW,
+ ADC_READY => ADC_READY,
+ PORT1_WINDOWED => PORT1_WINDOWED,
+ PORT2_WINDOWED => PORT2_WINDOWED,
+ REF_WINDOWED => REF_WINDOWED,
+ WINDOWING_DONE => WINDOWING_DONE,
+ NSAMPLES => NSAMPLES
+ );
+
+ -- Clock process definitions
+ CLK_process :process
+ begin
+ CLK <= '0';
+ wait for CLK_period/2;
+ CLK <= '1';
+ wait for CLK_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+
+ wait for CLK_period*10;
+
+ -- insert stimulus here
+ WINDOW_TYPE <= "10";
+ NSAMPLES <= "0000000010001";
+ PORT1_RAW <= "0000000010000000";
+ PORT2_RAW <= "0000000100000000";
+ REF_RAW <= "0000001000000000";
+ ADC_READY <= '0';
+ RESET <= '1';
+ wait for CLK_period;
+ RESET <= '0';
+ for i in 0 to 271 loop
+ wait for CLK_period*111;
+ ADC_READY <= '1';
+ wait for CLK_period;
+ ADC_READY <= '0';
+ end loop;
+
+ wait;
+ end process;
+
+END;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/VNA.gise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/VNA.gise
new file mode 100644
index 0000000..8529fb8
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/VNA.gise
@@ -0,0 +1,413 @@
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/VNA.xise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/VNA.xise
new file mode 100644
index 0000000..31ee3f6
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/VNA.xise
@@ -0,0 +1,513 @@
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/VNA_external_lo_slave.xise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/VNA_external_lo_slave.xise
new file mode 100644
index 0000000..e26b1fa
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/VNA_external_lo_slave.xise
@@ -0,0 +1,513 @@
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Windowing.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Windowing.vhd
new file mode 100644
index 0000000..3750645
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/Windowing.vhd
@@ -0,0 +1,201 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:18:17 11/06/2020
+-- Design Name:
+-- Module Name: Windowing - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Windowing is
+ Port ( CLK : in STD_LOGIC;
+ RESET : in STD_LOGIC;
+ WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
+ PORT1_RAW : in STD_LOGIC_VECTOR (15 downto 0);
+ PORT2_RAW : in STD_LOGIC_VECTOR (15 downto 0);
+ REF_RAW : in STD_LOGIC_VECTOR (15 downto 0);
+ ADC_READY : in STD_LOGIC;
+ PORT1_WINDOWED : out STD_LOGIC_VECTOR (17 downto 0);
+ PORT2_WINDOWED : out STD_LOGIC_VECTOR (17 downto 0);
+ REF_WINDOWED : out STD_LOGIC_VECTOR (17 downto 0);
+ WINDOWING_DONE : out STD_LOGIC;
+ NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0));
+end Windowing;
+
+architecture Behavioral of Windowing is
+COMPONENT window
+PORT(
+ CLK : IN std_logic;
+ INDEX : IN std_logic_vector(6 downto 0);
+ WINDOW_TYPE : IN std_logic_vector(1 downto 0);
+ VALUE : OUT std_logic_vector(15 downto 0)
+ );
+END COMPONENT;
+COMPONENT DSP_SLICE
+ PORT (
+ clk : IN STD_LOGIC;
+ ce : IN STD_LOGIC;
+ sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+ p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+ );
+END COMPONENT;
+ signal window_index : std_logic_vector(6 downto 0);
+ signal window_value : std_logic_vector(15 downto 0);
+ signal window_sample_cnt : integer range -8 to 8191;
+ signal window_index_inc : integer range 0 to 8;
+ signal window_sample_compare : integer range 0 to 8191;
+ signal window_sample_cnt_inc : integer range 0 to 8;
+
+ signal mult_a : std_logic_vector(17 downto 0);
+ signal mult_b : std_logic_vector(17 downto 0);
+ signal mult_p : std_logic_vector(47 downto 0);
+ signal mult_enable : std_logic;
+
+ type states is (CalcWindowInc, WaitingForADC, CalcPort1, CalcPort2, CalcRef, MultDelay1, MultDelay2, StorePort1, StorePort2, StoreRef);
+ signal state : states;
+begin
+
+ Mult : DSP_SLICE
+ PORT MAP (
+ clk => CLK,
+ ce => mult_enable,
+ sel => "0",
+ a => mult_a,
+ b => mult_b,
+ c => (others => '0'),
+ p => mult_p
+ );
+ WindowROM: window PORT MAP(
+ CLK => CLK,
+ INDEX => window_index,
+ WINDOW_TYPE => WINDOW_TYPE,
+ VALUE => window_value
+ );
+ -- sign extend multiplier inputs
+ mult_a(17 downto 16) <= mult_a(15) & mult_a(15);
+ mult_b(17 downto 16) <= mult_b(15) & mult_b(15);
+
+ mult_a(15 downto 0) <= window_value;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ WINDOWING_DONE <= '0';
+ state <= CalcWindowInc;
+ mult_enable <= '0';
+ mult_b(15 downto 0) <= (others => '0');
+ window_index <= (others => '0');
+ window_sample_cnt <= 0;
+ window_sample_compare <= to_integer(unsigned(NSAMPLES));
+ else
+ case state is
+ when CalcWindowInc =>
+ case window_sample_compare is
+ when 1 =>
+ -- 16 samples, increment on every sample by 8
+ window_sample_cnt_inc <= 1;
+ window_index_inc <= 8;
+ when 2 to 3 =>
+ -- 32-48 samples, increment by 4
+ window_sample_cnt_inc <= 2;
+ window_index_inc <= 4;
+ when 4 to 7 =>
+ -- 64-112 samples, increment by 2
+ window_sample_cnt_inc <= 4;
+ window_index_inc <= 2;
+ when others =>
+ -- 128 or more samples, increment by 1
+ window_sample_cnt_inc <= 8;
+ window_index_inc <= 1;
+ end case;
+ state <= WaitingForADC;
+ when WaitingForADC =>
+ WINDOWING_DONE <= '0';
+ mult_enable <= '0';
+ mult_b(15 downto 0) <= (others => '0');
+ if ADC_READY = '1' then
+ state <= CalcPort1;
+ end if;
+ when CalcPort1 =>
+ WINDOWING_DONE <= '0';
+ mult_enable <= '1';
+ mult_b(15 downto 0) <= PORT1_RAW;
+ state <= CalcPort2;
+ when CalcPort2 =>
+ WINDOWING_DONE <= '0';
+ mult_enable <= '1';
+ mult_b(15 downto 0) <= PORT2_RAW;
+ state <= CalcRef;
+ when CalcRef =>
+ WINDOWING_DONE <= '0';
+ mult_enable <= '1';
+ mult_b(15 downto 0) <= REF_RAW;
+ state <= MultDelay1;
+ when MultDelay1 =>
+ WINDOWING_DONE <= '0';
+ mult_enable <= '1';
+ mult_b(15 downto 0) <= (others => '0');
+ state <= MultDelay2;
+ when MultDelay2 =>
+ WINDOWING_DONE <= '0';
+ mult_enable <= '1';
+ mult_b(15 downto 0) <= (others => '0');
+ state <= StorePort1;
+ when StorePort1 =>
+ WINDOWING_DONE <= '0';
+ mult_enable <= '1';
+ mult_b(15 downto 0) <= (others => '0');
+ PORT1_WINDOWED <= mult_p(30 downto 13);
+ state <= StorePort2;
+ when StorePort2 =>
+ WINDOWING_DONE <= '0';
+ mult_enable <= '1';
+ mult_b(15 downto 0) <= (others => '0');
+ PORT2_WINDOWED <= mult_p(30 downto 13);
+ state <= StoreRef;
+ when StoreRef =>
+ WINDOWING_DONE <= '1';
+ mult_enable <= '0';
+ mult_b(15 downto 0) <= (others => '0');
+ REF_WINDOWED <= mult_p(30 downto 13);
+ -- update window increment
+ if window_sample_cnt + window_sample_cnt_inc < window_sample_compare then
+ window_sample_cnt <= window_sample_cnt + window_sample_cnt_inc;
+ else
+ window_sample_cnt <= window_sample_cnt + window_sample_cnt_inc - window_sample_compare;
+ window_index <= std_logic_vector( unsigned(window_index) + window_index_inc );
+ end if;
+ state <= WaitingForADC;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end Behavioral;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/.gitignore b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/.gitignore
new file mode 100644
index 0000000..68f8144
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/.gitignore
@@ -0,0 +1,6 @@
+*
+*/*
+!.gitignore
+!*.xco
+!*.xise
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/DSP48.xco b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/DSP48.xco
new file mode 100644
index 0000000..face7fc
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/DSP48.xco
@@ -0,0 +1,136 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Fri Nov 6 13:56:17 2020
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:xbip_dsp48_macro:2.1
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT DSP48_Macro xilinx.com:ip:xbip_dsp48_macro:2.1
+# END Select
+# BEGIN Parameters
+CSET a_binarywidth=0
+CSET a_width=18
+CSET areg_1=false
+CSET areg_2=false
+CSET areg_3=true
+CSET areg_4=true
+CSET b_binarywidth=0
+CSET b_width=18
+CSET breg_1=false
+CSET breg_2=false
+CSET breg_3=true
+CSET breg_4=true
+CSET c_binarywidth=0
+CSET c_width=48
+CSET cinreg_1=false
+CSET cinreg_2=false
+CSET cinreg_3=false
+CSET cinreg_4=false
+CSET cinreg_5=false
+CSET component_name=DSP48
+CSET concat_binarywidth=0
+CSET concat_width=48
+CSET concatreg_3=false
+CSET concatreg_4=false
+CSET concatreg_5=false
+CSET creg_1=false
+CSET creg_2=false
+CSET creg_3=true
+CSET creg_4=true
+CSET creg_5=true
+CSET d_binarywidth=0
+CSET d_width=18
+CSET dreg_1=false
+CSET dreg_2=false
+CSET dreg_3=false
+CSET gui_behaviour=Coregen
+CSET has_a_ce=false
+CSET has_a_sclr=false
+CSET has_acout=false
+CSET has_b_ce=false
+CSET has_b_sclr=false
+CSET has_bcout=false
+CSET has_c_ce=false
+CSET has_c_sclr=false
+CSET has_carrycascout=false
+CSET has_carryout=false
+CSET has_ce=true
+CSET has_concat_ce=false
+CSET has_concat_sclr=false
+CSET has_d_ce=false
+CSET has_d_sclr=false
+CSET has_m_ce=false
+CSET has_m_sclr=false
+CSET has_p_ce=false
+CSET has_p_sclr=false
+CSET has_pcout=false
+CSET has_sclr=false
+CSET has_sel_ce=false
+CSET has_sel_sclr=false
+CSET instruction1=A*B
+CSET instruction2=A*B+C
+CSET instruction3=#
+CSET instruction4=#
+CSET instruction5=#
+CSET instruction6=#
+CSET instruction7=#
+CSET instruction8=#
+CSET instruction_list=#
+CSET mreg_5=true
+CSET opreg_1=false
+CSET opreg_2=false
+CSET opreg_3=true
+CSET opreg_4=true
+CSET opreg_5=true
+CSET output_properties=Full_Precision
+CSET p_binarywidth=0
+CSET p_full_width=48
+CSET p_width=48
+CSET pcin_binarywidth=0
+CSET pipeline_options=Automatic
+CSET preg_6=true
+CSET show_filtered=false
+CSET tier_1=false
+CSET tier_2=false
+CSET tier_3=false
+CSET tier_4=false
+CSET tier_5=false
+CSET tier_6=false
+CSET use_dsp48=true
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-05T14:23:53Z
+# END Extra information
+GENERATE
+# CRC: 2ca4f824
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/DSP48.xise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/DSP48.xise
new file mode 100644
index 0000000..4da40c6
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/DSP48.xise
@@ -0,0 +1,73 @@
+
+
+
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/DSP_SLICE.xco b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/DSP_SLICE.xco
new file mode 100644
index 0000000..b39e78b
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/DSP_SLICE.xco
@@ -0,0 +1,136 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Fri Nov 6 13:57:46 2020
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:xbip_dsp48_macro:2.1
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT DSP48_Macro xilinx.com:ip:xbip_dsp48_macro:2.1
+# END Select
+# BEGIN Parameters
+CSET a_binarywidth=0
+CSET a_width=18
+CSET areg_1=false
+CSET areg_2=false
+CSET areg_3=true
+CSET areg_4=true
+CSET b_binarywidth=0
+CSET b_width=18
+CSET breg_1=false
+CSET breg_2=false
+CSET breg_3=true
+CSET breg_4=true
+CSET c_binarywidth=0
+CSET c_width=48
+CSET cinreg_1=false
+CSET cinreg_2=false
+CSET cinreg_3=false
+CSET cinreg_4=false
+CSET cinreg_5=false
+CSET component_name=DSP_SLICE
+CSET concat_binarywidth=0
+CSET concat_width=48
+CSET concatreg_3=false
+CSET concatreg_4=false
+CSET concatreg_5=false
+CSET creg_1=false
+CSET creg_2=false
+CSET creg_3=true
+CSET creg_4=true
+CSET creg_5=true
+CSET d_binarywidth=0
+CSET d_width=18
+CSET dreg_1=false
+CSET dreg_2=false
+CSET dreg_3=false
+CSET gui_behaviour=Coregen
+CSET has_a_ce=false
+CSET has_a_sclr=false
+CSET has_acout=false
+CSET has_b_ce=false
+CSET has_b_sclr=false
+CSET has_bcout=false
+CSET has_c_ce=false
+CSET has_c_sclr=false
+CSET has_carrycascout=false
+CSET has_carryout=false
+CSET has_ce=true
+CSET has_concat_ce=false
+CSET has_concat_sclr=false
+CSET has_d_ce=false
+CSET has_d_sclr=false
+CSET has_m_ce=false
+CSET has_m_sclr=false
+CSET has_p_ce=false
+CSET has_p_sclr=false
+CSET has_pcout=false
+CSET has_sclr=false
+CSET has_sel_ce=false
+CSET has_sel_sclr=false
+CSET instruction1=A*B
+CSET instruction2=A*B+C
+CSET instruction3=#
+CSET instruction4=#
+CSET instruction5=#
+CSET instruction6=#
+CSET instruction7=#
+CSET instruction8=#
+CSET instruction_list=#
+CSET mreg_5=true
+CSET opreg_1=false
+CSET opreg_2=false
+CSET opreg_3=true
+CSET opreg_4=true
+CSET opreg_5=true
+CSET output_properties=Full_Precision
+CSET p_binarywidth=0
+CSET p_full_width=48
+CSET p_width=48
+CSET pcin_binarywidth=0
+CSET pipeline_options=Automatic
+CSET preg_6=true
+CSET show_filtered=false
+CSET tier_1=false
+CSET tier_2=false
+CSET tier_3=false
+CSET tier_4=false
+CSET tier_5=false
+CSET tier_6=false
+CSET use_dsp48=true
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-05T14:23:53Z
+# END Extra information
+GENERATE
+# CRC: 57648294
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/DSP_SLICE.xise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/DSP_SLICE.xise
new file mode 100644
index 0000000..92644f3
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/DSP_SLICE.xise
@@ -0,0 +1,73 @@
+
+
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/PLL.xco b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/PLL.xco
new file mode 100644
index 0000000..709503d
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/PLL.xco
@@ -0,0 +1,269 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Thu May 14 06:56:00 2020
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:clk_wiz:3.6
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=CLK_OUT1
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=CLK_OUT2
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkfb_stopped_port=CLKFB_STOPPED
+CSET clkin1_jitter_ps=625.0
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.000
+CSET clkout1_requested_out_freq=102.4
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.000
+CSET clkout2_requested_out_freq=100.000
+CSET clkout2_requested_phase=0.000
+CSET clkout2_used=false
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.000
+CSET clkout3_requested_out_freq=100.000
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=false
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.000
+CSET clkout4_requested_out_freq=100.000
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.000
+CSET clkout5_requested_out_freq=100.000
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.000
+CSET clkout6_requested_out_freq=100.000
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.000
+CSET clkout7_requested_out_freq=100.000
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=AUTO
+CSET component_name=PLL
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=1X
+CSET dcm_clk_out1_port=CLKFX
+CSET dcm_clk_out2_port=CLK0
+CSET dcm_clk_out3_port=CLK0
+CSET dcm_clk_out4_port=CLK0
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=5
+CSET dcm_clkfx_multiply=32
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=1
+CSET dcm_clkgen_clkfx_md_max=0.000
+CSET dcm_clkgen_clkfx_multiply=4
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=10.000
+CSET dcm_clkgen_notes=None
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=62.500
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=4.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=10.000
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=4.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=1
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=0.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=1
+CSET override_dcm=false
+CSET override_dcm_clkgen=false
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=lin64
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=16
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=31.250
+CSET pll_clkout0_divide=5
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=1
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=1
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=1
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=SYSTEM_SYNCHRONOUS
+CSET pll_divclk_divide=1
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=16
+CSET prim_in_jitter=0.010
+CSET prim_source=Single_ended_clock_capable_pin
+CSET primary_port=CLK_IN1
+CSET primitive=MMCM
+CSET primtype_sel=PLL_BASE
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET ss_mod_freq=250
+CSET ss_mode=CENTER_HIGH
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=false
+CSET use_clkfb_stopped=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=true
+CSET use_inclk_stopped=false
+CSET use_inclk_switchover=false
+CSET use_locked=true
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=true
+CSET use_power_down=false
+CSET use_reset=true
+CSET use_spread_spectrum=false
+CSET use_spread_spectrum_1=false
+CSET use_status=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-05-10T12:44:55Z
+# END Extra information
+GENERATE
+# CRC: 2c6bfa8c
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/PLL.xise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/PLL.xise
new file mode 100644
index 0000000..b0b1f74
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/PLL.xise
@@ -0,0 +1,74 @@
+
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/SinCos.xco b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/SinCos.xco
new file mode 100644
index 0000000..2d9e926
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/SinCos.xco
@@ -0,0 +1,142 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Tue May 5 15:36:58 2020
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:dds_compiler:4.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT DDS_Compiler xilinx.com:ip:dds_compiler:4.0
+# END Select
+# BEGIN Parameters
+CSET amplitude_mode=Full_Range
+CSET channel_pin=false
+CSET channels=1
+CSET clock_enable=false
+CSET component_name=SinCos
+CSET dds_clock_rate=100
+CSET dsp48_use=Minimal
+CSET explicit_period=false
+CSET frequency_resolution=0.4
+CSET gui_behaviour=Coregen
+CSET has_phase_out=false
+CSET latency=6
+CSET latency_configuration=Auto
+CSET memory_type=Auto
+CSET negative_cosine=false
+CSET negative_sine=false
+CSET noise_shaping=None
+CSET optimization_goal=Auto
+CSET output_frequency1=0
+CSET output_frequency10=0
+CSET output_frequency11=0
+CSET output_frequency12=0
+CSET output_frequency13=0
+CSET output_frequency14=0
+CSET output_frequency15=0
+CSET output_frequency16=0
+CSET output_frequency2=0
+CSET output_frequency3=0
+CSET output_frequency4=0
+CSET output_frequency5=0
+CSET output_frequency6=0
+CSET output_frequency7=0
+CSET output_frequency8=0
+CSET output_frequency9=0
+CSET output_selection=Sine_and_Cosine
+CSET output_width=16
+CSET parameter_entry=Hardware_Parameters
+CSET partspresent=SIN_COS_LUT_only
+CSET period=1
+CSET phase_increment=Fixed
+CSET phase_offset=None
+CSET phase_offset_angles1=0
+CSET phase_offset_angles10=0
+CSET phase_offset_angles11=0
+CSET phase_offset_angles12=0
+CSET phase_offset_angles13=0
+CSET phase_offset_angles14=0
+CSET phase_offset_angles15=0
+CSET phase_offset_angles16=0
+CSET phase_offset_angles2=0
+CSET phase_offset_angles3=0
+CSET phase_offset_angles4=0
+CSET phase_offset_angles5=0
+CSET phase_offset_angles6=0
+CSET phase_offset_angles7=0
+CSET phase_offset_angles8=0
+CSET phase_offset_angles9=0
+CSET phase_width=12
+CSET pinc1=0
+CSET pinc10=0
+CSET pinc11=0
+CSET pinc12=0
+CSET pinc13=0
+CSET pinc14=0
+CSET pinc15=0
+CSET pinc16=0
+CSET pinc2=0
+CSET pinc3=0
+CSET pinc4=0
+CSET pinc5=0
+CSET pinc6=0
+CSET pinc7=0
+CSET pinc8=0
+CSET pinc9=0
+CSET poff1=0
+CSET poff10=0
+CSET poff11=0
+CSET poff12=0
+CSET poff13=0
+CSET poff14=0
+CSET poff15=0
+CSET poff16=0
+CSET poff2=0
+CSET poff3=0
+CSET poff4=0
+CSET poff5=0
+CSET poff6=0
+CSET poff7=0
+CSET poff8=0
+CSET poff9=0
+CSET por_mode=false
+CSET rdy=false
+CSET rfd=false
+CSET sclr_pin=false
+CSET spurious_free_dynamic_range=36
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-08-28T14:48:35Z
+# END Extra information
+GENERATE
+# CRC: dc69a097
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/SinCos.xise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/SinCos.xise
new file mode 100644
index 0000000..48631e5
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/SinCos.xise
@@ -0,0 +1,73 @@
+
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/SweepConfigMem.xco b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/SweepConfigMem.xco
new file mode 100644
index 0000000..2ee1c5a
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/SweepConfigMem.xco
@@ -0,0 +1,108 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Mon Sep 14 08:50:12 2020
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=9
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=SweepConfigMem
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_32bit_address=false
+CSET enable_a=Use_ENA_Pin
+CSET enable_b=Always_Enabled
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=false
+CSET mem_file=no_Mem_file_loaded
+CSET memory_type=Simple_Dual_Port_RAM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=0
+CSET primitive=8kx2
+CSET read_width_a=96
+CSET read_width_b=96
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_bram_block=Stand_Alone
+CSET use_byte_write_enable=false
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=4501
+CSET write_width_a=96
+CSET write_width_b=96
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T16:22:25Z
+# END Extra information
+GENERATE
+# CRC: e7b4a756
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/SweepConfigMem.xise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/SweepConfigMem.xise
new file mode 100644
index 0000000..eb7b0f0
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/SweepConfigMem.xise
@@ -0,0 +1,73 @@
+
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/result_bram.xco b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/result_bram.xco
new file mode 100644
index 0000000..5a73570
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/result_bram.xco
@@ -0,0 +1,108 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Sat Nov 7 15:56:38 2020
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=9
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=result_bram
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_32bit_address=false
+CSET enable_a=Always_Enabled
+CSET enable_b=Always_Enabled
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=false
+CSET mem_file=no_Mem_file_loaded
+CSET memory_type=Simple_Dual_Port_RAM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=0
+CSET primitive=8kx2
+CSET read_width_a=192
+CSET read_width_b=192
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_bram_block=Stand_Alone
+CSET use_byte_write_enable=false
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=256
+CSET write_width_a=192
+CSET write_width_b=192
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T16:22:25Z
+# END Extra information
+GENERATE
+# CRC: 14273b86
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/result_bram.xise b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/result_bram.xise
new file mode 100644
index 0000000..caffa95
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/ipcore_dir/result_bram.xise
@@ -0,0 +1,73 @@
+
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/spi_slave.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/spi_slave.vhd
new file mode 100644
index 0000000..c4654e4
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/spi_slave.vhd
@@ -0,0 +1,151 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:14:17 03/05/2019
+-- Design Name:
+-- Module Name: spi_slave - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity spi_slave is
+ generic ( W : integer;
+ PREWIDTH : integer);
+ Port ( SPI_CLK : in STD_LOGIC;
+ MISO : out STD_LOGIC;
+ MOSI : in STD_LOGIC;
+ CS : in STD_LOGIC;
+ BUF_OUT : out STD_LOGIC_VECTOR (W-1 downto 0) := (others => '0');
+ BUF_IN : in STD_LOGIC_VECTOR (W-1 downto 0);
+ CLK : in STD_LOGIC;
+ COMPLETE : out STD_LOGIC;
+ -- processing the complete word after it is complete leaves very little time
+ -- for read operations. Indicate when the first PREWIDTH bits are ready which
+ -- allows more time to prepare the response to the next word
+ PRE_COMPLETE : out STD_LOGIC;
+ PRE_BUF_OUT : out STD_LOGIC_VECTOR (PREWIDTH-1 downto 0) := (others => '0')
+ );
+end spi_slave;
+
+architecture Behavioral of spi_slave is
+ signal miso_buffer : STD_LOGIC_VECTOR (W-1 downto 0);
+ signal mosi_buffer : STD_LOGIC_VECTOR (W-2 downto 0);
+
+ signal data_valid : STD_LOGIC_VECTOR(2 downto 0);
+ signal data_synced : STD_LOGIC_VECTOR(2 downto 0);
+ signal data : STD_LOGIC_VECTOR(W-1 downto 0);
+ signal pre_data : STD_LOGIC_VECTOR(PREWIDTH-1 downto 0);
+ signal pre_data_valid : STD_LOGIC_VECTOR(3 downto 0);
+
+ signal bit_cnt : integer range 0 to W-1;
+begin
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ COMPLETE <= '0';
+ PRE_COMPLETE <= '0';
+ data_valid(2 downto 1) <= data_valid(1 downto 0);
+ pre_data_valid(3 downto 1) <= pre_data_valid(2 downto 0);
+ if data_valid(2) = '1' then
+ if data_synced(0) = '0' then
+ BUF_OUT <= data;
+ COMPLETE <= '1';
+ data_synced(0) <= '1';
+ end if;
+ else
+ data_synced(0) <= '0';
+ end if;
+ if pre_data_valid(3 downto 2) = "01" then
+ -- pre_data has just become valid
+ PRE_BUF_OUT <= pre_data;
+ PRE_COMPLETE <= '1';
+ end if;
+ end if;
+ end process;
+
+ MISO <= BUF_IN(15) when bit_cnt = 0 else miso_buffer(W-2);
+
+ slave_in: process(SPI_CLK, CS)
+ begin
+ if CS = '1' then
+ bit_cnt <= 0;
+ data_valid(0) <= '0';
+ pre_data_valid(0) <= '0';
+ elsif rising_edge(SPI_CLK) then
+ -- data input process: sample on the rising edge
+ data_synced(2 downto 1) <= data_synced(1 downto 0);
+ if bit_cnt = PREWIDTH-1 then
+ -- first couple of bits are ready
+ pre_data <= mosi_buffer(PREWIDTH-2 downto 0) & MOSI;
+ pre_data_valid(0) <= '1';
+ end if;
+ if bit_cnt = W-1 then
+ -- this was the last bit
+ pre_data_valid(0) <= '0';
+ data_valid(0) <= '1';
+ data <= mosi_buffer(W-2 downto 0) & MOSI;
+ else
+ if data_valid(0) = '1' and data_synced(2) = '1' then
+ data_valid(0) <= '0';
+ end if;
+ mosi_buffer <= mosi_buffer(W-3 downto 0) & MOSI;
+ end if;
+
+ -- data output process: data should be launched on the falling edge
+ -- but the delay is too large. Launch on the rising edge instead
+ if bit_cnt < W-1 then
+ bit_cnt <= bit_cnt + 1;
+ if bit_cnt = 0 then
+ miso_buffer <= BUF_IN;
+ else
+ miso_buffer <= miso_buffer(W-2 downto 0) & '0';
+ end if;
+ else
+ bit_cnt <= 0;
+ end if;
+ end if;
+ end process;
+
+-- slave_out: process(SPI_CLK, CS, BUF_IN, bit_cnt)
+-- begin
+-- if CS = '1' then
+-- bit_cnt <= 0;
+-- elsif falling_edge(SPI_CLK) then
+-- if bit_cnt < W-1 then
+-- bit_cnt <= bit_cnt + 1;
+-- if bit_cnt = 0 then
+-- miso_buffer <= BUF_IN;
+-- else
+-- miso_buffer <= miso_buffer(W-2 downto 0) & '0';
+-- end if;
+-- else
+-- bit_cnt <= 0;
+-- --miso_buffer <= BUF_IN;
+-- end if;
+-- end if;
+-- end process;
+
+end Behavioral;
\ No newline at end of file
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top.bin b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top.bin
new file mode 100644
index 0000000..38af89c
Binary files /dev/null and b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top.bin differ
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top.ucf b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top.ucf
new file mode 100644
index 0000000..b0c65f6
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top.ucf
@@ -0,0 +1,165 @@
+CONFIG VCCAUX = 3.3;
+# Global FPGA clock
+NET "CLK" PERIOD = 62.5 ns HIGH 50%;
+
+# Constraints for SPI interface to MCU
+NET "MCU_SCK" PERIOD = 23.52941176ns HIGH 50%;
+NET "MCU_MOSI" OFFSET = IN 2ns VALID 3ns BEFORE "MCU_SCK";
+NET "MCU_MISO" OFFSET = OUT 18.529ns VALID 10ns AFTER "MCU_SCK";
+NET "MCU_MISO" SLEW = FAST;
+
+# ADC constraints
+NET "REF_SCLK" PERIOD = 19.5ns HIGH 50%;
+NET "REF_SDO" OFFSET = IN 9ns VALID 9ns BEFORE "REF_SCLK";
+NET "PORT1_SCLK" PERIOD = 19.5ns HIGH 50%;
+NET "PORT1_SDO" OFFSET = IN 9ns VALID 9ns BEFORE "PORT1_SCLK";
+NET "PORT2_SCLK" PERIOD = 19.5ns HIGH 50%;
+NET "PORT2_SDO" OFFSET = IN 9ns VALID 9ns BEFORE "PORT2_SCLK";
+NET "PORT1_SCLK" SLEW = FAST;
+NET "PORT2_SCLK" SLEW = FAST;
+NET "REF_SCLK" SLEW = FAST;
+
+NET "ATTENUATION[6]" IOSTANDARD = LVCMOS33;
+NET "ATTENUATION[5]" IOSTANDARD = LVCMOS33;
+NET "ATTENUATION[4]" IOSTANDARD = LVCMOS33;
+NET "ATTENUATION[3]" IOSTANDARD = LVCMOS33;
+NET "ATTENUATION[2]" IOSTANDARD = LVCMOS33;
+NET "ATTENUATION[1]" IOSTANDARD = LVCMOS33;
+NET "ATTENUATION[0]" IOSTANDARD = LVCMOS33;
+
+NET "LEDS[7]" IOSTANDARD = LVCMOS33;
+NET "LEDS[6]" IOSTANDARD = LVCMOS33;
+NET "LEDS[5]" IOSTANDARD = LVCMOS33;
+NET "LEDS[4]" IOSTANDARD = LVCMOS33;
+NET "LEDS[3]" IOSTANDARD = LVCMOS33;
+NET "LEDS[2]" IOSTANDARD = LVCMOS33;
+NET "LEDS[1]" IOSTANDARD = LVCMOS33;
+NET "LEDS[0]" IOSTANDARD = LVCMOS33;
+
+NET "AMP_PWDN" IOSTANDARD = LVCMOS33;
+NET "CLK" IOSTANDARD = LVCMOS33;
+NET "FILT_IN_C2" IOSTANDARD = LVCMOS33;
+NET "FILT_IN_C1" IOSTANDARD = LVCMOS33;
+NET "FILT_OUT_C2" IOSTANDARD = LVCMOS33;
+NET "FILT_OUT_C1" IOSTANDARD = LVCMOS33;
+NET "LO1_CE" IOSTANDARD = LVCMOS33;
+NET "LO1_LD" IOSTANDARD = LVCMOS33;
+NET "LO1_LE" IOSTANDARD = LVCMOS33;
+NET "LO1_CLK" IOSTANDARD = LVCMOS33;
+NET "LO1_MOSI" IOSTANDARD = LVCMOS33;
+NET "LO1_MUX" IOSTANDARD = LVCMOS33;
+NET "MCU_AUX1" IOSTANDARD = LVCMOS33;
+NET "LO1_RF_EN" IOSTANDARD = LVCMOS33;
+NET "SOURCE_RF_EN" IOSTANDARD = LVCMOS33;
+NET "SOURCE_MUX" IOSTANDARD = LVCMOS33;
+NET "SOURCE_LE" IOSTANDARD = LVCMOS33;
+NET "SOURCE_MOSI" IOSTANDARD = LVCMOS33;
+NET "SOURCE_LD" IOSTANDARD = LVCMOS33;
+NET "SOURCE_CLK" IOSTANDARD = LVCMOS33;
+NET "SOURCE_CE" IOSTANDARD = LVCMOS33;
+NET "RESET" IOSTANDARD = LVCMOS33;
+NET "REF_SDO" IOSTANDARD = LVCMOS33;
+NET "REF_SCLK" IOSTANDARD = LVCMOS33;
+NET "REF_CONVSTART" IOSTANDARD = LVCMOS33;
+NET "PORT2_SDO" IOSTANDARD = LVCMOS33;
+NET "PORT2_SCLK" IOSTANDARD = LVCMOS33;
+NET "PORT2_CONVSTART" IOSTANDARD = LVCMOS33;
+NET "PORT1_SDO" IOSTANDARD = LVCMOS33;
+NET "PORT1_SCLK" IOSTANDARD = LVCMOS33;
+NET "PORT1_CONVSTART" IOSTANDARD = LVCMOS33;
+NET "MCU_SCK" IOSTANDARD = LVCMOS33;
+NET "MCU_NSS" IOSTANDARD = LVCMOS33;
+NET "MCU_MISO" IOSTANDARD = LVCMOS33;
+NET "MCU_MOSI" IOSTANDARD = LVCMOS33;
+NET "MCU_INTR" IOSTANDARD = LVCMOS33;
+NET "MCU_AUX2" IOSTANDARD = LVCMOS33;
+NET "MCU_AUX3" IOSTANDARD = LVCMOS33;
+NET "TRIGGER_IN" IOSTANDARD = LVCMOS33;
+NET "TRIGGER_OUT" IOSTANDARD = LVCMOS33;
+
+NET "ATTENUATION[6]" LOC = P9;
+NET "ATTENUATION[5]" LOC = P10;
+NET "ATTENUATION[4]" LOC = P11;
+NET "ATTENUATION[3]" LOC = P12;
+NET "ATTENUATION[2]" LOC = P14;
+NET "ATTENUATION[1]" LOC = P15;
+NET "ATTENUATION[0]" LOC = P16;
+NET "LEDS[0]" LOC = P87;
+NET "LEDS[1]" LOC = P92;
+NET "LEDS[2]" LOC = P93;
+NET "LEDS[3]" LOC = P88;
+NET "LEDS[4]" LOC = P85;
+NET "LEDS[5]" LOC = P84;
+NET "LEDS[6]" LOC = P83;
+NET "LEDS[7]" LOC = P82;
+NET "AMP_PWDN" LOC = P8;
+NET "BAND_SELECT_HIGH" LOC = P21;
+NET "BAND_SELECT_LOW" LOC = P17;
+NET "CLK" LOC = P50;
+NET "FILT_IN_C1" LOC = P26;
+NET "FILT_IN_C2" LOC = P24;
+NET "FILT_OUT_C1" LOC = P22;
+NET "FILT_OUT_C2" LOC = P23;
+NET "LO1_CE" LOC = P45;
+NET "LO1_CLK" LOC = P48;
+NET "LO1_LD" LOC = P56;
+NET "LO1_LE" LOC = P46;
+NET "LO1_MOSI" LOC = P47;
+NET "LO1_MUX" LOC = P51;
+NET "LO1_RF_EN" LOC = P55;
+NET "MCU_AUX1" LOC = P78;
+NET "MCU_AUX2" LOC = P75;
+NET "MCU_AUX3" LOC = P74;
+NET "TRIGGER_IN" LOC = P80;
+NET "TRIGGER_OUT" LOC = P81;
+NET "MCU_INTR" LOC = P59;
+NET "MCU_MISO" LOC = P62;
+NET "MCU_MOSI" LOC = P61;
+NET "MCU_NSS" LOC = P67;
+NET "MCU_SCK" LOC = P66;
+NET "MCU_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
+
+# PlanAhead Generated physical constraints
+
+NET "PORT1_CONVSTART" LOC = P139;
+NET "PORT1_MIX1_EN" LOC = P141;
+NET "PORT1_MIX2_EN" LOC = P140;
+NET "PORT1_SCLK" LOC = P137;
+NET "PORT1_SDO" LOC = P138;
+NET "PORT1_SELECT" LOC = P142;
+NET "PORT2_CONVSTART" LOC = P44;
+NET "PORT2_MIX1_EN" LOC = P58;
+NET "PORT2_MIX2_EN" LOC = P57;
+NET "PORT2_SCLK" LOC = P41;
+NET "PORT2_SDO" LOC = P43;
+NET "PORT2_SELECT" LOC = P40;
+NET "PORT_SELECT1" LOC = P6;
+NET "PORT_SELECT2" LOC = P7;
+NET "REF_CONVSTART" LOC = P5;
+NET "REF_MIX1_EN" LOC = P144;
+NET "REF_MIX2_EN" LOC = P143;
+NET "REF_SCLK" LOC = P1;
+NET "REF_SDO" LOC = P2;
+NET "RESET" LOC = P79;
+NET "SOURCE_CE" LOC = P27;
+NET "SOURCE_CLK" LOC = P32;
+NET "SOURCE_LD" LOC = P35;
+NET "SOURCE_LE" LOC = P29;
+NET "SOURCE_MOSI" LOC = P30;
+NET "SOURCE_MUX" LOC = P33;
+NET "SOURCE_RF_EN" LOC = P34;
+
+# PlanAhead Generated IO constraints
+
+NET "BAND_SELECT_HIGH" IOSTANDARD = LVCMOS33;
+NET "BAND_SELECT_LOW" IOSTANDARD = LVCMOS33;
+NET "PORT1_MIX1_EN" IOSTANDARD = LVCMOS33;
+NET "PORT1_MIX2_EN" IOSTANDARD = LVCMOS33;
+NET "PORT1_SELECT" IOSTANDARD = LVCMOS33;
+NET "PORT2_MIX1_EN" IOSTANDARD = LVCMOS33;
+NET "PORT2_MIX2_EN" IOSTANDARD = LVCMOS33;
+NET "PORT2_SELECT" IOSTANDARD = LVCMOS33;
+NET "PORT_SELECT1" IOSTANDARD = LVCMOS33;
+NET "PORT_SELECT2" IOSTANDARD = LVCMOS33;
+NET "REF_MIX1_EN" IOSTANDARD = LVCMOS33;
+NET "REF_MIX2_EN" IOSTANDARD = LVCMOS33;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top.vhd
new file mode 100644
index 0000000..2d23cae
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top.vhd
@@ -0,0 +1,858 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:47:31 05/05/2020
+-- Design Name:
+-- Module Name: top - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.BuildConfig.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+ Port ( CLK : in STD_LOGIC;
+ RESET : in STD_LOGIC;
+ MCU_MOSI : in STD_LOGIC;
+ MCU_NSS : in STD_LOGIC;
+ MCU_INTR : out STD_LOGIC;
+ MCU_SCK : in STD_LOGIC;
+ MCU_MISO : out STD_LOGIC;
+ MCU_AUX1 : in STD_LOGIC;
+ MCU_AUX2 : in STD_LOGIC;
+ MCU_AUX3 : in STD_LOGIC;
+ TRIGGER_IN : in STD_LOGIC;
+ TRIGGER_OUT : out STD_LOGIC;
+ PORT2_CONVSTART : out STD_LOGIC;
+ PORT2_SDO : in STD_LOGIC;
+ PORT2_SCLK : inout STD_LOGIC;
+ PORT2_MIX2_EN : out STD_LOGIC;
+ PORT2_MIX1_EN : out STD_LOGIC;
+ PORT1_CONVSTART : out STD_LOGIC;
+ PORT1_SDO : in STD_LOGIC;
+ PORT1_SCLK : inout STD_LOGIC;
+ PORT1_MIX2_EN : out STD_LOGIC;
+ PORT1_MIX1_EN : out STD_LOGIC;
+ LO1_MUX : in STD_LOGIC;
+ LO1_RF_EN : out STD_LOGIC;
+ LO1_LD : in STD_LOGIC;
+ LO1_CLK : out STD_LOGIC;
+ LO1_MOSI : out STD_LOGIC;
+ LO1_LE : out STD_LOGIC;
+ LO1_CE : out STD_LOGIC;
+ LEDS : out STD_LOGIC_VECTOR (7 downto 0);
+ REF_MIX2_EN : out STD_LOGIC;
+ REF_MIX1_EN : out STD_LOGIC;
+ ATTENUATION : out STD_LOGIC_VECTOR (6 downto 0);
+ AMP_PWDN : out STD_LOGIC;
+ PORT1_SELECT : out STD_LOGIC; -- Port 1 additional isolation switch enable
+ PORT2_SELECT : out STD_LOGIC; -- Port 2 additional isolation switch enable
+ PORT_SELECT1 : out STD_LOGIC; -- Enable source -> port 1 switch
+ PORT_SELECT2 : out STD_LOGIC; -- Enable source -> port 2 switch
+ BAND_SELECT_HIGH : out STD_LOGIC;
+ BAND_SELECT_LOW : out STD_LOGIC;
+ FILT_OUT_C1 : out STD_LOGIC;
+ FILT_OUT_C2 : out STD_LOGIC;
+ FILT_IN_C1 : out STD_LOGIC;
+ FILT_IN_C2 : out STD_LOGIC;
+ SOURCE_RF_EN : out STD_LOGIC;
+ SOURCE_LD : in STD_LOGIC;
+ SOURCE_MUX : in STD_LOGIC;
+ SOURCE_CLK : out STD_LOGIC;
+ SOURCE_MOSI : out STD_LOGIC;
+ SOURCE_LE : out STD_LOGIC;
+ SOURCE_CE : out STD_LOGIC;
+ REF_CONVSTART : out STD_LOGIC;
+ REF_SDO : in STD_LOGIC;
+ REF_SCLK : inout STD_LOGIC);
+end top;
+
+architecture Behavioral of top is
+ component PLL
+ port
+ (-- Clock in ports
+ CLK_IN1 : in std_logic;
+ -- Clock out ports
+ CLK_OUT1 : out std_logic;
+ -- Status and control signals
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+ end component;
+
+ COMPONENT ResetDelay
+ GENERIC(CLK_DELAY : integer);
+ PORT(
+ CLK : IN std_logic;
+ IN_RESET : IN std_logic;
+ OUT_RESET : OUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT Sweep
+ PORT(
+ CLK : IN std_logic;
+ RESET : IN std_logic;
+ NPOINTS : IN std_logic_vector(12 downto 0);
+ CONFIG_DATA : IN std_logic_vector(95 downto 0);
+ USER_NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
+ NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
+ SETTLING_TIME : in STD_LOGIC_VECTOR (19 downto 0);
+ SAMPLING_BUSY : in STD_LOGIC;
+ SAMPLING_DONE : IN std_logic;
+ MAX2871_DEF_4 : IN std_logic_vector(31 downto 0);
+ MAX2871_DEF_3 : IN std_logic_vector(31 downto 0);
+ MAX2871_DEF_1 : IN std_logic_vector(31 downto 0);
+ MAX2871_DEF_0 : IN std_logic_vector(31 downto 0);
+ PLL_RELOAD_DONE : IN std_logic;
+ PLL_LOCKED : IN std_logic;
+ CONFIG_ADDRESS : OUT std_logic_vector(12 downto 0);
+ START_SAMPLING : OUT std_logic;
+ BAND_SELECT : out STD_LOGIC;
+ SOURCE_REG_4 : OUT std_logic_vector(31 downto 0);
+ SOURCE_REG_3 : OUT std_logic_vector(31 downto 0);
+ SOURCE_REG_1 : OUT std_logic_vector(31 downto 0);
+ SOURCE_REG_0 : OUT std_logic_vector(31 downto 0);
+ LO_REG_4 : OUT std_logic_vector(31 downto 0);
+ LO_REG_3 : OUT std_logic_vector(31 downto 0);
+ LO_REG_1 : OUT std_logic_vector(31 downto 0);
+ LO_REG_0 : OUT std_logic_vector(31 downto 0);
+ RELOAD_PLL_REGS : OUT std_logic;
+ SWEEP_HALTED : out STD_LOGIC;
+ SWEEP_RESUME : in STD_LOGIC;
+ SYNC_ENABLED : in STD_LOGIC;
+ SYNC_MASTER : in STD_LOGIC;
+ TRIGGER_IN : in STD_LOGIC;
+ TRIGGER_OUT : out STD_LOGIC;
+ NEW_DATA : out STD_LOGIC;
+ ATTENUATOR : OUT std_logic_vector(6 downto 0);
+ SOURCE_FILTER : OUT std_logic_vector(1 downto 0);
+ STAGES : in STD_LOGIC_VECTOR (2 downto 0);
+ PORT1_STAGE : in STD_LOGIC_VECTOR (2 downto 0);
+ PORT2_STAGE : in STD_LOGIC_VECTOR (2 downto 0);
+
+ PORT1_ACTIVE : out STD_LOGIC;
+ PORT2_ACTIVE : out STD_LOGIC;
+ SOURCE_CE : out STD_LOGIC;
+ RESULT_INDEX : out STD_LOGIC_VECTOR (15 downto 0);
+ DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0)
+ );
+ END COMPONENT;
+
+ COMPONENT Windowing
+ PORT(
+ CLK : IN std_logic;
+ RESET : IN std_logic;
+ WINDOW_TYPE : IN std_logic_vector(1 downto 0);
+ PORT1_RAW : IN std_logic_vector(15 downto 0);
+ PORT2_RAW : IN std_logic_vector(15 downto 0);
+ REF_RAW : IN std_logic_vector(15 downto 0);
+ ADC_READY : IN std_logic;
+ NSAMPLES : IN std_logic_vector(12 downto 0);
+ PORT1_WINDOWED : OUT std_logic_vector(17 downto 0);
+ PORT2_WINDOWED : OUT std_logic_vector(17 downto 0);
+ REF_WINDOWED : OUT std_logic_vector(17 downto 0);
+ WINDOWING_DONE : OUT std_logic
+ );
+ END COMPONENT;
+
+ COMPONENT Sampling
+ Generic(CLK_CYCLES_PRE_DONE : integer);
+ PORT(
+ CLK : IN std_logic;
+ RESET : IN std_logic;
+ ADC_PRESCALER : in STD_LOGIC_VECTOR(7 downto 0);
+ PHASEINC : in STD_LOGIC_VECTOR(11 downto 0);
+ PORT1 : IN std_logic_vector(17 downto 0);
+ PORT2 : IN std_logic_vector(17 downto 0);
+ REF : IN std_logic_vector(17 downto 0);
+ NEW_SAMPLE : IN std_logic;
+ START : IN std_logic;
+ SAMPLES : IN std_logic_vector(12 downto 0);
+ ADC_START : OUT std_logic;
+ DONE : OUT std_logic;
+ PRE_DONE : OUT std_logic;
+ PORT1_I : OUT std_logic_vector(47 downto 0);
+ PORT1_Q : OUT std_logic_vector(47 downto 0);
+ PORT2_I : OUT std_logic_vector(47 downto 0);
+ PORT2_Q : OUT std_logic_vector(47 downto 0);
+ REF_I : OUT std_logic_vector(47 downto 0);
+ REF_Q : OUT std_logic_vector(47 downto 0);
+ ACTIVE : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT MCP33131
+ Generic(CLK_DIV : integer;
+ CONVCYCLES : integer);
+ PORT(
+ CLK : IN std_logic;
+ RESET : IN std_logic;
+ START : IN std_logic;
+ SDO : IN std_logic;
+ READY : OUT std_logic;
+ DATA : OUT std_logic_vector(15 downto 0);
+ MIN : out STD_LOGIC_VECTOR (15 downto 0);
+ MAX : out STD_LOGIC_VECTOR (15 downto 0);
+ RESET_MINMAX : in STD_LOGIC;
+ CONVSTART : OUT std_logic;
+ SCLK : INOUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT MAX2871
+ Generic (CLK_DIV : integer);
+ PORT(
+ CLK : IN std_logic;
+ RESET : IN std_logic;
+ REG4 : IN std_logic_vector(31 downto 0);
+ REG3 : IN std_logic_vector(31 downto 0);
+ REG1 : IN std_logic_vector(31 downto 0);
+ REG0 : IN std_logic_vector(31 downto 0);
+ RELOAD : IN std_logic;
+ CLK_OUT : OUT std_logic;
+ MOSI : OUT std_logic;
+ LE : OUT std_logic;
+ DONE : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT SPICommands
+ PORT(
+ CLK : IN std_logic;
+ RESET : IN std_logic;
+ SCLK : IN std_logic;
+ MOSI : IN std_logic;
+ NSS : IN std_logic;
+ NEW_SAMPLING_DATA : IN std_logic;
+ SAMPLING_RESULT : IN std_logic_vector(303 downto 0);
+ ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
+ SOURCE_UNLOCKED : IN std_logic;
+ LO_UNLOCKED : IN std_logic;
+ MISO : OUT std_logic;
+ MAX2871_DEF_4 : OUT std_logic_vector(31 downto 0);
+ MAX2871_DEF_3 : OUT std_logic_vector(31 downto 0);
+ MAX2871_DEF_1 : OUT std_logic_vector(31 downto 0);
+ MAX2871_DEF_0 : OUT std_logic_vector(31 downto 0);
+ SWEEP_DATA : OUT std_logic_vector(95 downto 0);
+ SWEEP_ADDRESS : OUT std_logic_vector(12 downto 0);
+ SWEEP_WRITE : OUT std_logic_vector(0 to 0);
+ SWEEP_POINTS : OUT std_logic_vector(12 downto 0);
+ NSAMPLES : OUT std_logic_vector(12 downto 0);
+ STAGES : out STD_LOGIC_VECTOR (2 downto 0);
+ SETTLING_TIME : out STD_LOGIC_VECTOR (19 downto 0);
+ SYNC_ENABLED : out STD_LOGIC;
+ SYNC_MASTER : out STD_LOGIC;
+ PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
+ PORT2_STAGE : out STD_LOGIC_VECTOR (2 downto 0);
+ PORT1_EN : out STD_LOGIC;
+ PORT2_EN : out STD_LOGIC;
+ REF_EN : out STD_LOGIC;
+ AMP_SHDN : out STD_LOGIC;
+ SOURCE_RF_EN : out STD_LOGIC;
+ LO_RF_EN : out STD_LOGIC;
+ SOURCE_CE_EN : out STD_LOGIC;
+ LO_CE_EN : out STD_LOGIC;
+ PORTSWITCH_EN : out STD_LOGIC;
+ LEDS : out STD_LOGIC_VECTOR(2 downto 0);
+ WINDOW_SETTING : out STD_LOGIC_VECTOR(1 downto 0);
+ ADC_PRESCALER : out STD_LOGIC_VECTOR(7 downto 0);
+ ADC_PHASEINC : out STD_LOGIC_VECTOR(11 downto 0);
+ INTERRUPT_ASSERTED : OUT std_logic;
+ RESET_MINMAX : out STD_LOGIC;
+ SWEEP_HALTED : in STD_LOGIC;
+ SWEEP_RESUME : out STD_LOGIC;
+ SPI_OVERWRITE_ENABLED : out STD_LOGIC;
+ SPI_OVERWRITE_DATA : out STD_LOGIC_VECTOR(14 downto 0);
+ DFT_BIN1_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
+ DFT_DIFFBIN_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
+ DFT_RESULT_READY : in STD_LOGIC;
+ DFT_OUTPUT : in STD_LOGIC_VECTOR (191 downto 0);
+ DFT_NEXT_OUTPUT : out STD_LOGIC;
+ DFT_ENABLE : out STD_LOGIC;
+ DEBUG_STATUS : in STD_LOGIC_VECTOR (10 downto 0)
+ );
+ END COMPONENT;
+
+ COMPONENT DFT
+ Generic (BINS : integer);
+ PORT(
+ CLK : IN std_logic;
+ RESET : IN std_logic;
+ PORT1 : IN std_logic_vector(17 downto 0);
+ PORT2 : IN std_logic_vector(17 downto 0);
+ NEW_SAMPLE : IN std_logic;
+ NSAMPLES : IN std_logic_vector(12 downto 0);
+ BIN1_PHASEINC : IN std_logic_vector(15 downto 0);
+ DIFFBIN_PHASEINC : IN std_logic_vector(15 downto 0);
+ NEXT_OUTPUT : IN std_logic;
+ RESULT_READY : OUT std_logic;
+ OUTPUT : OUT std_logic_vector(191 downto 0)
+ );
+ END COMPONENT;
+
+ COMPONENT SweepConfigMem
+ PORT (
+ clka : IN STD_LOGIC;
+ ena : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ COMPONENT Synchronizer
+ GENERIC(stages : integer);
+ PORT(
+ CLK : IN std_logic;
+ SYNC_IN : IN std_logic;
+ SYNC_OUT : OUT std_logic
+ );
+ END COMPONENT;
+
+ signal clk_pll : std_logic;
+ signal clk_locked : std_logic;
+ signal inv_clk_locked : std_logic;
+ signal int_reset : std_logic;
+
+ -- PLL signals
+ signal source_reg_4 : std_logic_vector(31 downto 0);
+ signal source_reg_3 : std_logic_vector(31 downto 0);
+ signal source_reg_1 : std_logic_vector(31 downto 0);
+ signal source_reg_0 : std_logic_vector(31 downto 0);
+ signal lo_reg_4 : std_logic_vector(31 downto 0);
+ signal lo_reg_3 : std_logic_vector(31 downto 0);
+ signal lo_reg_1 : std_logic_vector(31 downto 0);
+ signal lo_reg_0 : std_logic_vector(31 downto 0);
+ signal reload_plls : std_logic;
+ signal source_reloaded : std_logic;
+ signal lo_reloaded : std_logic;
+ signal plls_reloaded : std_logic;
+ signal plls_locked : std_logic;
+ signal source_unlocked : std_logic;
+ signal lo_unlocked : std_logic;
+
+ signal source_filter : std_logic_vector(1 downto 0);
+
+ -- ADC signals
+ signal adc_trigger_sample : std_logic;
+ signal adc_port1_ready : std_logic;
+ signal adc_port1_data : std_logic_vector(15 downto 0);
+ signal adc_port2_data : std_logic_vector(15 downto 0);
+ signal adc_ref_data : std_logic_vector(15 downto 0);
+ signal adc_minmax : std_logic_vector(95 downto 0);
+ signal adc_reset_minmax : std_logic;
+
+ signal port1_windowed : std_logic_vector(17 downto 0);
+ signal port2_windowed : std_logic_vector(17 downto 0);
+ signal ref_windowed : std_logic_vector(17 downto 0);
+ signal windowing_ready : std_logic;
+
+ -- Sampling signals
+ signal sampling_busy : std_logic;
+ signal sampling_done : std_logic;
+ signal sampling_start : std_logic;
+ signal sampling_samples : std_logic_vector(12 downto 0);
+ signal sampling_user_samples : std_logic_vector(12 downto 0);
+ signal sampling_result : std_logic_vector(303 downto 0);
+ signal sampling_window : std_logic_vector(1 downto 0);
+ signal sampling_prescaler : std_logic_vector(7 downto 0);
+ signal sampling_phaseinc : std_logic_vector(11 downto 0);
+
+ -- Sweep signals
+ signal sweep_points : std_logic_vector(12 downto 0);
+ signal sweep_stages : STD_LOGIC_VECTOR (2 downto 0);
+ signal sweep_sync_enabled: STD_LOGIC;
+ signal sweep_sync_master : STD_LOGIC;
+ signal sweep_port1_stage : STD_LOGIC_VECTOR (2 downto 0);
+ signal sweep_port2_stage : STD_LOGIC_VECTOR (2 downto 0);
+ signal sweep_config_data : std_logic_vector(95 downto 0);
+ signal sweep_config_address : std_logic_vector(12 downto 0);
+ signal sweep_source_filter : std_logic_vector(1 downto 0);
+ signal sweep_band : std_logic;
+ signal sweep_attenuator : std_logic_vector(6 downto 0);
+
+ signal sweep_config_write_address : std_logic_vector(12 downto 0);
+ signal sweep_config_write_data : std_logic_vector(95 downto 0);
+ signal sweep_config_write : std_logic_vector(0 downto 0);
+
+ signal sweep_reset : std_logic;
+ signal sweep_halted : std_logic;
+ signal sweep_resume : std_logic;
+
+ signal sweep_excite_port1 : std_logic;
+ signal sweep_excite_port2 : std_logic;
+
+ signal sweep_source_CE : std_logic;
+
+ signal sweep_trigger_in : std_logic;
+ signal sweep_trigger_out : std_logic;
+
+ -- Configuration signals
+ signal settling_time : std_logic_vector(19 downto 0);
+ signal def_reg_4 : std_logic_vector(31 downto 0);
+ signal def_reg_3 : std_logic_vector(31 downto 0);
+ signal def_reg_1 : std_logic_vector(31 downto 0);
+ signal def_reg_0 : std_logic_vector(31 downto 0);
+ signal user_leds : std_logic_vector(2 downto 0);
+ signal port1mix_en : std_logic;
+ signal port2mix_en : std_logic;
+ signal refmix_en : std_logic;
+ signal portswitch_en : std_logic;
+ signal SPI_source_CE : std_logic;
+ signal SPI_LO1_CE : std_logic;
+ signal SPI_LO1_RF_EN : std_logic;
+
+ -- PLL/SPI internal mux
+ signal fpga_select : std_logic;
+ signal fpga_source_SCK : std_logic;
+ signal fpga_source_MOSI : std_logic;
+ signal fpga_source_LE : std_logic;
+ signal fpga_LO1_SCK : std_logic;
+ signal fpga_LO1_MOSI : std_logic;
+ signal fpga_LO1_LE : std_logic;
+ signal fpga_miso : std_logic;
+
+ -- synchronized asynchronous inputs
+ signal aux1_sync : std_logic;
+ signal aux2_sync : std_logic;
+ signal aux3_sync : std_logic;
+ signal lo_ld_sync : std_logic;
+ signal source_ld_sync : std_logic;
+ signal nss_sync : std_logic;
+
+ signal debug : std_logic_vector(10 downto 0);
+ signal intr : std_logic;
+
+ -- HW overwrite signals
+ signal HW_overwrite_enabled : std_logic;
+ signal HW_overwrite_data : std_logic_vector(14 downto 0);
+
+ -- DFT signals
+ signal dft_bin1_phaseinc : std_logic_vector (15 downto 0);
+ signal dft_diffbin_phaseinc : std_logic_vector (15 downto 0);
+ signal dft_ready : std_logic;
+ signal dft_output : std_logic_vector (191 downto 0);
+ signal dft_next_output : std_logic;
+ signal dft_enable : std_logic;
+ signal dft_reset : std_logic;
+begin
+
+ -- Reference CLK LED
+ LEDS(0) <= user_leds(2);
+ -- Lock status of PLLs
+ LEDS(1) <= clk_locked;
+ LEDS(2) <= LO1_LD;
+ LEDS(3) <= SOURCE_LD;
+ -- Sweep and active port
+ PORT_SELECT2 <= (sweep_excite_port2 and portswitch_en) when HW_overwrite_enabled = '0' else HW_overwrite_data(3);
+ PORT2_SELECT <= (sweep_excite_port2 and portswitch_en) when HW_overwrite_enabled = '0' else HW_overwrite_data(3);
+ PORT_SELECT1 <= (sweep_excite_port1 and portswitch_en) when HW_overwrite_enabled = '0' else HW_overwrite_data(4);
+ PORT1_SELECT <= (sweep_excite_port1 and portswitch_en) when HW_overwrite_enabled = '0' else HW_overwrite_data(4);
+ BAND_SELECT_HIGH <= not sweep_band when HW_overwrite_enabled = '0' else not HW_overwrite_data(5);
+ BAND_SELECT_LOW <= sweep_band when HW_overwrite_enabled = '0' else HW_overwrite_data(5);
+ PORT1_MIX2_EN <= port1mix_en;
+ PORT1_MIX1_EN <= not port1mix_en;
+ PORT2_MIX2_EN <= port2mix_en;
+ PORT2_MIX1_EN <= not port2mix_en;
+ REF_MIX2_EN <= refmix_en;
+ REF_MIX1_EN <= not refmix_en;
+ LEDS(4) <= not (not sweep_reset and sweep_excite_port2 and portswitch_en) when HW_overwrite_enabled = '0' else not HW_overwrite_data(3);
+ LEDS(5) <= not (not sweep_reset and sweep_excite_port1 and portswitch_en) when HW_overwrite_enabled = '0' else not HW_overwrite_data(4);
+ -- Uncommitted LEDs
+ LEDS(7 downto 6) <= user_leds(1 downto 0);
+ --LEDS(7) <= '0';
+ MCU_INTR <= intr;
+ LO1_RF_EN <= '0' when EXTERNAL_MASTER_LO_SLAVE else SPI_LO1_RF_EN;
+ LO1_CE <= '0' when EXTERNAL_MASTER_LO_SLAVE else SPI_LO1_CE;
+ --LEDS(6) <= intr;
+
+ MainCLK : PLL
+ port map(
+ -- Clock in ports
+ CLK_IN1 => CLK,
+ -- Clock out ports
+ CLK_OUT1 => clk_pll,
+ -- Status and control signals
+ RESET => RESET,
+ LOCKED => clk_locked
+ );
+
+ inv_clk_locked <= not clk_locked and not RESET;
+
+ Inst_ResetDelay: ResetDelay
+ GENERIC MAP(CLK_DELAY => 100)
+ PORT MAP(
+ CLK => clk_pll,
+ IN_RESET => inv_clk_locked,
+ OUT_RESET => int_reset
+ );
+
+ Sync_AUX1 : Synchronizer
+ GENERIC MAP(stages => 2)
+ PORT MAP(
+ CLK => clk_pll,
+ SYNC_IN => MCU_AUX1,
+ SYNC_OUT => aux1_sync
+ );
+ Sync_AUX2 : Synchronizer
+ GENERIC MAP(stages => 2)
+ PORT MAP(
+ CLK => clk_pll,
+ SYNC_IN => MCU_AUX2,
+ SYNC_OUT => aux2_sync
+ );
+ Sync_AUX3 : Synchronizer
+ GENERIC MAP(stages => 2)
+ PORT MAP(
+ CLK => clk_pll,
+ SYNC_IN => MCU_AUX3,
+ SYNC_OUT => aux3_sync
+ );
+ Sync_LO_LD : Synchronizer
+ GENERIC MAP(stages => 2)
+ PORT MAP(
+ CLK => clk_pll,
+ SYNC_IN => LO1_LD,
+ SYNC_OUT => lo_ld_sync
+ );
+ Sync_SOURCE_LD : Synchronizer
+ GENERIC MAP(stages => 2)
+ PORT MAP(
+ CLK => clk_pll,
+ SYNC_IN => SOURCE_LD,
+ SYNC_OUT => source_ld_sync
+ );
+ Sync_NSS : Synchronizer
+ GENERIC MAP(stages => 2)
+ PORT MAP(
+ CLK => clk_pll,
+ SYNC_IN => MCU_NSS,
+ SYNC_OUT => nss_sync
+ );
+ Sync_TRIGGER_IN : Synchronizer
+ GENERIC MAP(stages => 2)
+ PORT MAP(
+ CLK => clk_pll,
+ SYNC_IN => TRIGGER_IN,
+ SYNC_OUT => sweep_trigger_in
+ );
+ Sync_TRIGGER_OUT : Synchronizer
+ GENERIC MAP(stages => 2)
+ PORT MAP(
+ CLK => clk_pll,
+ SYNC_IN => sweep_trigger_out,
+ SYNC_OUT => TRIGGER_OUT
+ );
+
+
+ Source: MAX2871
+ GENERIC MAP(CLK_DIV => 6)
+ PORT MAP(
+ CLK => clk_pll,
+ RESET => int_reset,
+ REG4 => source_reg_4,
+ REG3 => source_reg_3,
+ REG1 => source_reg_1,
+ REG0 => source_reg_0,
+ RELOAD => reload_plls,
+ CLK_OUT => fpga_source_SCK,
+ MOSI => fpga_source_MOSI,
+ LE => fpga_source_LE,
+ DONE => source_reloaded
+ );
+ LO1: MAX2871
+ GENERIC MAP(CLK_DIV => 6)
+ PORT MAP(
+ CLK => clk_pll,
+ RESET => int_reset,
+ REG4 => lo_reg_4,
+ REG3 => lo_reg_3,
+ REG1 => lo_reg_1,
+ REG0 => lo_reg_0,
+ RELOAD => reload_plls,
+ CLK_OUT => fpga_LO1_SCK,
+ MOSI => fpga_LO1_MOSI,
+ LE => fpga_LO1_LE,
+ DONE => lo_reloaded
+ );
+ plls_reloaded <= source_reloaded and lo_reloaded;
+ plls_locked <= source_ld_sync when EXTERNAL_MASTER_LO_SLAVE else source_ld_sync and lo_ld_sync;
+
+ Port1ADC: MCP33131
+ GENERIC MAP(CLK_DIV => 2,
+ CONVCYCLES => 77)
+ PORT MAP(
+ CLK => clk_pll,
+ RESET => int_reset,
+ START => adc_trigger_sample,
+ READY => adc_port1_ready,
+ DATA => adc_port1_data,
+ MIN => adc_minmax(15 downto 0),
+ MAX => adc_minmax(31 downto 16),
+ RESET_MINMAX => adc_reset_minmax,
+ SDO => PORT1_SDO,
+ CONVSTART => PORT1_CONVSTART,
+ SCLK => PORT1_SCLK
+ );
+ Port2ADC: MCP33131
+ GENERIC MAP(CLK_DIV => 2,
+ CONVCYCLES => 77)
+ PORT MAP(
+ CLK => clk_pll,
+ RESET => int_reset,
+ START => adc_trigger_sample,
+ READY => open, -- synchronous ADCs, ready indicated by port 1 ADC
+ DATA => adc_port2_data,
+ MIN => adc_minmax(47 downto 32),
+ MAX => adc_minmax(63 downto 48),
+ RESET_MINMAX => adc_reset_minmax,
+ SDO => PORT2_SDO,
+ CONVSTART => PORT2_CONVSTART,
+ SCLK => PORT2_SCLK
+ );
+ RefADC: MCP33131
+ GENERIC MAP(CLK_DIV => 2,
+ CONVCYCLES => 77)
+ PORT MAP(
+ CLK => clk_pll,
+ RESET => int_reset,
+ START => adc_trigger_sample,
+ READY => open, -- synchronous ADCs, ready indicated by port 1 ADC
+ DATA => adc_ref_data,
+ MIN => adc_minmax(79 downto 64),
+ MAX => adc_minmax(95 downto 80),
+ RESET_MINMAX => adc_reset_minmax,
+ SDO => REF_SDO,
+ CONVSTART => REF_CONVSTART,
+ SCLK => REF_SCLK
+ );
+
+
+ Windower: Windowing PORT MAP(
+ CLK => clk_pll,
+ RESET => sampling_start,
+ WINDOW_TYPE => sampling_window,
+ PORT1_RAW => adc_port1_data,
+ PORT2_RAW => adc_port2_data,
+ REF_RAW => adc_ref_data,
+ ADC_READY => adc_port1_ready,
+ PORT1_WINDOWED => port1_windowed,
+ PORT2_WINDOWED => port2_windowed,
+ REF_WINDOWED => ref_windowed,
+ WINDOWING_DONE => windowing_ready,
+ NSAMPLES => sampling_samples
+ );
+
+ Sampler: Sampling
+ GENERIC MAP(CLK_CYCLES_PRE_DONE => 0)
+ PORT MAP(
+ CLK => clk_pll,
+ RESET => sweep_reset,
+ ADC_PRESCALER => sampling_prescaler,
+ PHASEINC => sampling_phaseinc,
+ PORT1 => port1_windowed,
+ PORT2 => port2_windowed,
+ REF => ref_windowed,
+ ADC_START => adc_trigger_sample,
+ NEW_SAMPLE => windowing_ready,
+ DONE => open,
+ PRE_DONE => open,
+ START => sampling_start,
+ SAMPLES => sampling_samples,
+ PORT1_I => sampling_result(287 downto 240),
+ PORT1_Q => sampling_result(239 downto 192),
+ PORT2_I => sampling_result(191 downto 144),
+ PORT2_Q => sampling_result(143 downto 96),
+ REF_I => sampling_result(95 downto 48),
+ REF_Q => sampling_result(47 downto 0),
+ ACTIVE => sampling_busy
+ );
+
+ sweep_reset <= not aux3_sync;
+
+ SweepModule: Sweep PORT MAP(
+ CLK => clk_pll,
+ RESET => sweep_reset,
+ NPOINTS => sweep_points,
+ CONFIG_ADDRESS => sweep_config_address,
+ CONFIG_DATA => sweep_config_data,
+ USER_NSAMPLES => sampling_user_samples,
+ NSAMPLES => sampling_samples,
+ SETTLING_TIME => settling_time,
+ SAMPLING_BUSY => sampling_busy,
+ SAMPLING_DONE => sampling_done,
+ START_SAMPLING => sampling_start,
+ BAND_SELECT => sweep_band,
+ MAX2871_DEF_4 => def_reg_4,
+ MAX2871_DEF_3 => def_reg_3,
+ MAX2871_DEF_1 => def_reg_1,
+ MAX2871_DEF_0 => def_reg_0,
+ SOURCE_REG_4 => source_reg_4,
+ SOURCE_REG_3 => source_reg_3,
+ SOURCE_REG_1 => source_reg_1,
+ SOURCE_REG_0 => source_reg_0,
+ LO_REG_4 => lo_reg_4,
+ LO_REG_3 => lo_reg_3,
+ LO_REG_1 => lo_reg_1,
+ LO_REG_0 => lo_reg_0,
+ RELOAD_PLL_REGS => reload_plls,
+ PLL_RELOAD_DONE => plls_reloaded,
+ PLL_LOCKED => plls_locked,
+ SWEEP_HALTED => sweep_halted,
+ SWEEP_RESUME => sweep_resume,
+ SYNC_ENABLED => sweep_sync_enabled,
+ SYNC_MASTER => sweep_sync_master,
+ TRIGGER_IN => sweep_trigger_in,
+ TRIGGER_OUT => sweep_trigger_out,
+ NEW_DATA => sampling_done,
+ ATTENUATOR => sweep_attenuator,
+ SOURCE_FILTER => sweep_source_filter,
+ STAGES => sweep_stages,
+ PORT1_STAGE => sweep_port1_stage,
+ PORT2_STAGE => sweep_port2_stage,
+
+ PORT1_ACTIVE => sweep_excite_port1,
+ PORT2_ACTIVE => sweep_excite_port2,
+ SOURCE_CE => sweep_source_CE,
+ DEBUG_STATUS => debug,
+ RESULT_INDEX => sampling_result(303 downto 288)
+ );
+
+ -- Source filter mapping
+ source_filter <= sweep_source_filter when HW_overwrite_enabled = '0' else HW_overwrite_data(7 downto 6);
+ FILT_IN_C1 <= '0' when source_filter = "00" or source_filter = "10" else '1';
+ FILT_IN_C2 <= '0' when source_filter = "11" or source_filter = "10" else '1';
+ FILT_OUT_C1 <= '0' when source_filter = "00" or source_filter = "10" else '1';
+ FILT_OUT_C2 <= '0' when source_filter = "00" or source_filter = "01" else '1';
+
+ ATTENUATION <= sweep_attenuator when HW_overwrite_enabled = '0' else HW_overwrite_data(14 downto 8);
+
+ -- PLL/SPI mux
+ -- only select FPGA SPI slave when both AUX1 and AUX2 are low
+ fpga_select <= nss_sync when aux1_sync = '0' and aux2_sync = '0' else '1';
+ -- direct connection between MCU and SOURCE when AUX1 is high
+ SOURCE_CLK <= MCU_SCK when aux1_sync = '1' else fpga_source_SCK;
+ SOURCE_MOSI <= MCU_MOSI when aux1_sync = '1' else fpga_source_MOSI;
+ SOURCE_LE <= MCU_NSS when aux1_sync = '1' else fpga_source_LE;
+ -- Keep the LO1 synthesizer interface completely quiet on dedicated external-LO slaves.
+ -- In the normal build AUX2 still exposes the direct MCU->LO1 path for manual control/debug.
+ LO1_CLK <= '0' when EXTERNAL_MASTER_LO_SLAVE else MCU_SCK when aux2_sync = '1' else fpga_LO1_SCK;
+ LO1_MOSI <= '0' when EXTERNAL_MASTER_LO_SLAVE else MCU_MOSI when aux2_sync = '1' else fpga_LO1_MOSI;
+ LO1_LE <= '0' when EXTERNAL_MASTER_LO_SLAVE else MCU_NSS when aux2_sync = '1' else fpga_LO1_LE;
+ -- select MISO source
+ MCU_MISO <= SOURCE_MUX when aux1_sync = '1' else
+ LO1_MUX when aux2_sync = '1' else
+ fpga_miso when MCU_NSS = '0' else
+ 'Z';
+
+ SOURCE_CE <= SPI_source_CE when sweep_reset = '1' else sweep_source_CE;
+
+ lo_unlocked <= '0' when EXTERNAL_MASTER_LO_SLAVE else not lo_ld_sync;
+ source_unlocked <= not source_ld_sync;
+
+ SPI: SPICommands PORT MAP(
+ CLK => clk_pll,
+ RESET => int_reset,
+ SCLK => MCU_SCK,
+ MOSI => MCU_MOSI,
+ MISO => fpga_miso,
+ NSS => fpga_select,
+ NEW_SAMPLING_DATA => sampling_done,
+ SAMPLING_RESULT => sampling_result,
+ ADC_MINMAX => adc_minmax,
+ SOURCE_UNLOCKED => source_unlocked,
+ LO_UNLOCKED => lo_unlocked,
+ MAX2871_DEF_4 => def_reg_4,
+ MAX2871_DEF_3 => def_reg_3,
+ MAX2871_DEF_1 => def_reg_1,
+ MAX2871_DEF_0 => def_reg_0,
+ SWEEP_DATA => sweep_config_write_data,
+ SWEEP_ADDRESS => sweep_config_write_address,
+ SWEEP_WRITE => sweep_config_write,
+ SWEEP_POINTS => sweep_points,
+ NSAMPLES => sampling_user_samples,
+ PORT1_EN => port1mix_en,
+ PORT2_EN => port2mix_en,
+ REF_EN => refmix_en,
+ AMP_SHDN => AMP_PWDN,
+ SOURCE_RF_EN => SOURCE_RF_EN,
+ LO_RF_EN => SPI_LO1_RF_EN,
+ SOURCE_CE_EN => SPI_source_CE,
+ LO_CE_EN => SPI_LO1_CE,
+ PORTSWITCH_EN => portswitch_en,
+ LEDS => user_leds,
+ WINDOW_SETTING => sampling_window,
+ ADC_PRESCALER => sampling_prescaler,
+ ADC_PHASEINC => sampling_phaseinc,
+ INTERRUPT_ASSERTED => intr,
+ RESET_MINMAX => adc_reset_minmax,
+ SWEEP_HALTED => sweep_halted,
+ SWEEP_RESUME => sweep_resume,
+ STAGES => sweep_stages,
+ SETTLING_TIME => settling_time,
+ SYNC_ENABLED => sweep_sync_enabled,
+ SYNC_MASTER => sweep_sync_master,
+ PORT1_STAGE => sweep_port1_stage,
+ PORT2_STAGE => sweep_port2_stage,
+ SPI_OVERWRITE_ENABLED => HW_overwrite_enabled,
+ SPI_OVERWRITE_DATA => HW_overwrite_data,
+ DFT_BIN1_PHASEINC => dft_bin1_phaseinc,
+ DFT_DIFFBIN_PHASEINC => dft_diffbin_phaseinc,
+ DFT_RESULT_READY => dft_ready,
+ DFT_OUTPUT => dft_output,
+ DFT_NEXT_OUTPUT => dft_next_output,
+ DFT_ENABLE => dft_enable,
+ DEBUG_STATUS => debug
+ );
+
+ dft_reset <= not dft_enable;
+
+ SA_DFT: DFT GENERIC MAP(BINS => 96)
+ PORT MAP(
+ CLK => clk_pll,
+ RESET => dft_reset,
+ PORT1 => port1_windowed,
+ PORT2 => port2_windowed,
+ NEW_SAMPLE => windowing_ready,
+ NSAMPLES => sampling_samples,
+ BIN1_PHASEINC => dft_bin1_phaseinc,
+ DIFFBIN_PHASEINC => dft_diffbin_phaseinc,
+ RESULT_READY => dft_ready,
+ OUTPUT => dft_output,
+ NEXT_OUTPUT => dft_next_output
+ );
+
+ ConfigMem : SweepConfigMem
+ PORT MAP (
+ clka => clk_pll,
+ ena => '1',
+ wea => sweep_config_write,
+ addra => sweep_config_write_address,
+ dina => sweep_config_write_data,
+ clkb => clk_pll,
+ addrb => sweep_config_address,
+ doutb => sweep_config_data
+ );
+
+end Behavioral;
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top_external_lo_slave.bin b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top_external_lo_slave.bin
new file mode 100644
index 0000000..ce7e3d6
Binary files /dev/null and b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top_external_lo_slave.bin differ
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top_master.bin b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top_master.bin
new file mode 100644
index 0000000..25ae99e
Binary files /dev/null and b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/top_master.bin differ
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/window.vhd b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/window.vhd
new file mode 100644
index 0000000..5281e6f
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/VNA/window.vhd
@@ -0,0 +1,77 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 13:28:54 09/16/2020
+-- Design Name:
+-- Module Name: window - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity window is
+ Port ( CLK : in STD_LOGIC;
+ INDEX : in STD_LOGIC_VECTOR (6 downto 0);
+ WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
+ VALUE : out STD_LOGIC_VECTOR (15 downto 0));
+end window;
+
+architecture Behavioral of window is
+ type window_data is array(127 downto 0) of std_logic_vector(15 downto 0);
+
+ impure function InitWindowDataFromFile (RomFileName : in string) return window_data is
+ FILE romfile : text is in RomFileName;
+ variable RomFileLine : line;
+ variable rom : window_data;
+ begin
+ for i in window_data'range loop
+ readline(romfile, RomFileLine);
+ read(RomFileLine, rom(i));
+ end loop;
+ return rom;
+ end function;
+
+ constant hann : window_data := InitWindowDataFromFile("Hann.dat");
+ constant kaiser : window_data := InitWindowDataFromFile("Kaiser.dat");
+ constant flattop : window_data := InitWindowDataFromFile("Flattop.dat");
+ signal i : integer range 0 to 127;
+begin
+
+ i <= to_integer(unsigned(INDEX));
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ case WINDOW_TYPE is
+ when "00" => VALUE <= "0001000000000000";
+ when "01" => VALUE <= kaiser(i);
+ when "10" => VALUE <= hann(i);
+ when "11" => VALUE <= flattop(i);
+ when others => VALUE <= (others => '0');
+ end case;
+ end if;
+ end process;
+end Behavioral;
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/WindowCoefficientGenerator.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/WindowCoefficientGenerator.py
new file mode 100755
index 0000000..c6674ba
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/FPGA/WindowCoefficientGenerator.py
@@ -0,0 +1,76 @@
+#!/usr/bin/env python3
+
+import math
+import numpy as np
+
+# Adapt these constants to your window requirements
+NUMBER_OF_COEFFICIENTS = 128
+BITS_PER_COEFFICIENT = 16
+
+# If set to true, the coefficients will be scaled to include the window amplitude correction factor.
+# They will also be scaled to 1/8 to have enough headroom for the correction.
+INCLUDE_AMPLITUDE_CORRECTION = True
+
+# Don't change anything below this line
+
+def bindigits(n, bits):
+ s = bin(n & int("1"*bits, 2))[2:]
+ return ("{0:0>%s}" % (bits)).format(s)
+
+class Window:
+ def __init__(self, name, function, correction):
+ self.name = name
+ self.function = function
+ self.correction = correction
+ self.sum = 0
+ self.num_coeff = 0
+
+ def StartFile(self):
+ self.file = open(self.name+".dat", "w")
+
+ def AddCoefficient(self, normalized_index):
+ if not hasattr(self, 'file'):
+ self.StartFile()
+ value = self.function(normalized_index)
+ self.sum = self.sum + value
+ self.num_coeff = self.num_coeff + 1
+ if INCLUDE_AMPLITUDE_CORRECTION:
+ value = value * self.correction / 8.0
+ value = int(value * (2 ** (BITS_PER_COEFFICIENT-1)))
+ # prevent overflow
+ if value >= (2 ** (BITS_PER_COEFFICIENT-1)):
+ value = value - 1
+ output = bindigits(value, BITS_PER_COEFFICIENT)
+ self.file.write(output+"\n")
+
+ def CorrectionFactor(self):
+ return 1.0 / (self.sum / self.num_coeff)
+
+def calc_hann(i):
+ return math.sin(math.pi * i) ** 2
+
+def calc_kaiser(i):
+ return np.kaiser(NUMBER_OF_COEFFICIENTS, 9.4)[int(i * NUMBER_OF_COEFFICIENTS)]
+
+def calc_flattop(i):
+ a0 = 0.21557895
+ a1 = 0.41663158
+ a2 = 0.277263158
+ a3 = 0.083578947
+ a4 = 0.006947368
+ return a0 - a1 * math.cos(2*math.pi*i) + a2 * math.cos(4*math.pi*i) - a3 * math.cos(6*math.pi*i) + a4 * math.cos(8*math.pi*i)
+
+WindowList = []
+WindowList.append(Window("Hann", calc_hann, 2.00))
+WindowList.append(Window("Kaiser", calc_kaiser, 2.50))
+WindowList.append(Window("Flattop", calc_flattop, 4.64))
+
+
+for i in range(NUMBER_OF_COEFFICIENTS):
+ norm_i = (i+0.5) / NUMBER_OF_COEFFICIENTS
+ for w in WindowList:
+ w.AddCoefficient(norm_i)
+
+for w in WindowList:
+ print(w.CorrectionFactor())
+ w.file.close();
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/LICENSE b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/LICENSE
new file mode 100644
index 0000000..f288702
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/LICENSE
@@ -0,0 +1,674 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc.
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+ The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works. By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users. We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors. You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+them if you wish), that you receive source code or can get it if you
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+
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+certain responsibilities if you distribute copies of the software, or if
+you modify it: responsibilities to respect the freedom of others.
+
+ For example, if you distribute copies of such a program, whether
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+ The precise terms and conditions for copying, distribution and
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/__init__.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/__init__.py
new file mode 100644
index 0000000..095fdf8
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/__init__.py
@@ -0,0 +1,10 @@
+from .librevna_usb_transport import list_connected_device_serial_numbers
+from .multi_device_vna_controller import MultiDeviceVnaController
+from .sweep_measurement_models import SweepConfiguration, SweepMeasurementResult
+
+__all__ = [
+ "MultiDeviceVnaController",
+ "SweepConfiguration",
+ "SweepMeasurementResult",
+ "list_connected_device_serial_numbers",
+]
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/description.md b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/description.md
new file mode 100644
index 0000000..1354a54
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/description.md
@@ -0,0 +1,383 @@
+LibreVNA вообще, что именно делает наш текущий Python-код, какие пакеты мы используем, как они кодируются и парсятся, и почему `_power_level_centidecibels_milliwatt` сейчас не нужен.
+
+**1. Где вообще начинается протокол**
+У LibreVNA поверх USB идёт свой бинарный протокол, а не `tty/serial`. Это видно и в документации, и в firmware:
+- USB endpoints: [Device_protocol_v13.tex](/home/europa/Documents/LibreVNA/Documentation/DeveloperInfo/Device_protocol_v13.tex:176)
+- актуальный код firmware: [Protocol.hpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/Communication/Protocol.hpp:573)
+
+На USB уровне:
+- `0x01` — host -> device
+- `0x81` — device -> host
+- `0x82` — debug ASCII logs
+
+В нашем коде data transport работает только через:
+- [librevna_usb_transport.py](/home/europa/Documents/LibreVNA/Python/librevna_multi_device_driver/librevna_usb_transport.py)
+
+То есть:
+- мы шлём команды в `0x01`
+- читаем протокольные пакеты из `0x81`
+- `0x82` вообще не используем
+
+**2. Общая структура любого LibreVNA packet**
+Общий framing один и тот же для почти всех packet types. Это описано в docs и реализовано в firmware:
+- docs: [Device_protocol_v13.tex](/home/europa/Documents/LibreVNA/Documentation/DeveloperInfo/Device_protocol_v13.tex:208)
+- firmware decode/encode: [Protocol.cpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/Communication/Protocol.cpp:5)
+- field offsets/constants: [PacketConstants.h](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/Communication/PacketConstants.h:10)
+
+Структура такая:
+1. `Header` — 1 байт, всегда `0x5A`
+2. `Length` — 2 байта, общая длина всего packet целиком
+3. `Type` — 1 байт, номер packet type
+4. `Payload` — переменная длина
+5. `CRC32` — 4 байта
+
+В Python это делает:
+- `encode_protocol_frame(...)` в [librevna_device_protocol.py](/home/europa/Documents/LibreVNA/Python/librevna_multi_device_driver/librevna_device_protocol.py:31)
+- `extract_complete_protocol_frames(...)` в [librevna_device_protocol.py](/home/europa/Documents/LibreVNA/Python/librevna_multi_device_driver/librevna_device_protocol.py:45)
+
+`encode_protocol_frame(...)`:
+- считает `total_frame_length = 8 + len(payload)`
+- пакует header/length/type
+- считает CRC32
+- дописывает CRC в конец
+
+`extract_complete_protocol_frames(...)`:
+- получает поток байт, а не “готовый packet”
+- ищет `0x5A`
+- читает `length`
+- если полного frame ещё нет, оставляет хвост в буфере
+- если frame полный, возвращает `(packet_type, payload)`
+
+Очень важно:
+- наш Python сейчас **не проверяет CRC**
+- firmware проверяет CRC для почти всех пакетов, но для `VNADatapoint` у них особый случай: CRC всегда `0`, чтобы не тратить время на вычисление CRC для каждого datapoint, см. [Protocol.cpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/Communication/Protocol.cpp:69) и [Protocol.cpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/Communication/Protocol.cpp:147)
+
+То есть сейчас Python делает “framing by magic + length”, но не “integrity check”.
+
+**3. Какие packet types вообще бывают**
+Полный актуальный enum лежит тут:
+- [Protocol.hpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/Communication/Protocol.hpp:573)
+
+Там есть много типов:
+- `SweepSettings = 2`
+- `ManualStatus = 3`
+- `ManualControl = 4`
+- `DeviceInfo = 5`
+- `FirmwarePacket = 6`
+- `Ack = 7`
+- `ClearFlash = 8`
+- `PerformFirmwareUpdate = 9`
+- `Nack = 10`
+- `Reference = 11`
+- `Generator = 12`
+- `SpectrumAnalyzerSettings = 13`
+- `SpectrumAnalyzerResult = 14`
+- `RequestDeviceInfo = 15`
+- ...
+- `SetIdle = 20`
+- `DeviceStatus = 25`
+- `RequestDeviceStatus = 26`
+- `VNADatapoint = 27`
+- `SetTrigger = 28`
+- `ClearTrigger = 29`
+- `InitiateSweep = 32`
+- `PerformAction = 33`
+
+Но наш текущий драйвер использует только маленький поднабор. Это зашито в:
+- [librevna_device_protocol.py](/home/europa/Documents/LibreVNA/Python/librevna_multi_device_driver/librevna_device_protocol.py:9)
+
+Мы используем:
+- `SweepSettings = 2`
+- `Ack = 7`
+- `Nack = 10`
+- `Reference = 11`
+- `SetIdle = 20`
+- `VNADatapoint = 27`
+
+То есть текущий драйвер — это именно VNA sweep driver, а не “полная реализация всех режимов прибора”.
+
+**4. Какие именно пакеты использует наш драйвер**
+Разберу их по смыслу.
+
+**`ReferenceSettings` / packet type `11`**
+Структура в firmware:
+- [Protocol.hpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/Communication/Protocol.hpp:186)
+
+Поля:
+- `uint32 ExtRefOutputFreq`
+- битовое поле:
+ - `AutomaticSwitch`
+ - `UseExternalRef`
+
+В Python это строит:
+- `build_reference_settings_payload(...)` в [librevna_device_protocol.py](/home/europa/Documents/LibreVNA/Python/librevna_multi_device_driver/librevna_device_protocol.py:74)
+
+Сейчас мы шлём:
+- `output_frequency_hz = 0`
+- `force_external_reference = True`
+
+То есть:
+- никакой `Ref Out` не включаем
+- просто принудительно говорим устройству использовать внешний `10 MHz`
+
+Это применяется в controller:
+- [multi_device_vna_controller.py](/home/europa/Documents/LibreVNA/Python/librevna_multi_device_driver/multi_device_vna_controller.py:183)
+
+**`SweepSettings` / packet type `2`**
+Структура в firmware:
+- [Protocol.hpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/Communication/Protocol.hpp:155)
+
+Поля:
+- `f_start`
+- `f_stop`
+- `points`
+- `if_bandwidth`
+- `cdbm_excitation_start`
+- bitfield config:
+ - `standby`
+ - `syncMaster`
+ - `suppressPeaks`
+ - `fixedPowerSetting`
+ - `logSweep`
+ - `syncMode`
+- stage mapping bitfield
+- `cdbm_excitation_stop`
+- `dwell_time`
+
+В Python это строит:
+- `build_sweep_settings_payload(...)` в [librevna_device_protocol.py](/home/europa/Documents/LibreVNA/Python/librevna_multi_device_driver/librevna_device_protocol.py:92)
+
+Что мы туда кладём:
+- start/stop/points/ifbw — из `SweepConfiguration`
+- power start/stop — одинаковые
+- `fixedPowerSetting = 1`
+- `suppressPeaks = 1`
+- `logSweep = 0`
+- `syncMode = 3`, если есть slaves
+- `syncMaster = 1` только у master
+- `port_1_stimulus_stage = 0` для master, `1` для slave
+
+Смысл:
+- master возбуждает `Port 1`
+- slaves только принимают
+- sync идёт через hardware trigger path
+
+Этот packet реально запускает VNA setup в firmware:
+- [App.cpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/App.cpp:126)
+
+**`SetIdle` / packet type `20`**
+Очень простой packet, без payload.
+В firmware:
+- [App.cpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/App.cpp:196)
+
+Он переводит устройство в idle:
+- выключает активный режим
+- останавливает sweep path
+
+У нас он используется только как service-command:
+- остановить continuous sweep
+- cleanup при ошибке
+- `close()`
+
+Это делает controller:
+- [multi_device_vna_controller.py](/home/europa/Documents/LibreVNA/Python/librevna_multi_device_driver/multi_device_vna_controller.py:173)
+
+**`Ack` / `Nack` / packet types `7` и `10`**
+Это ответы устройства на команды host.
+В firmware:
+- enum: [Protocol.hpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/Communication/Protocol.hpp:581)
+- отправка `Ack`/`Nack`: [App.cpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/App.cpp:129)
+
+В transport:
+- `wait_for_acknowledgement(...)` в [librevna_usb_transport.py](/home/europa/Documents/LibreVNA/Python/librevna_multi_device_driver/librevna_usb_transport.py:62)
+
+Логика:
+- читаем входящие пакеты
+- если пришёл `Ack`, команда считается применённой
+- если пришёл `Nack`, бросаем exception
+- прочие asynchronous packets просто пропускаем
+
+**`VNADatapoint` / packet type `27`**
+Это главный поток измерения.
+Структура в firmware:
+- template `VNADatapoint`: [Protocol.hpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/Communication/Protocol.hpp:25)
+- декодирование: [Protocol.cpp](/home/europa/Documents/LibreVNA/Software/VNA_embedded/Application/Communication/Protocol.cpp:79)
+
+Payload такой:
+1. `frequency` — `uint64`, 8 байт
+2. `cdBm` — `int16`, 2 байта
+3. `pointNum` — `uint16`, 2 байта
+4. `real_values` — `n * float32`
+5. `imag_values` — `n * float32`
+6. `descr_values` — `n * uint8`
+
+То есть фиксированный header payload имеет длину 12 байт:
+- `8 + 2 + 2`
+
+А дальше идёт `n` значений, каждое занимает:
+- `4` байта real
+- `4` байта imag
+- `1` байт descriptor
+- итого `9` байт на одно значение
+
+В Python это парсится тут:
+- `parse_vna_datapoint_payload(...)` в [librevna_device_protocol.py](/home/europa/Documents/LibreVNA/Python/librevna_multi_device_driver/librevna_device_protocol.py:134)
+
+Алгоритм:
+- читаем `frequency_hz`, `power`, `point_index` через `struct.unpack_from(" bytes:
+ """Wrap a packet payload in the LibreVNA transport frame."""
+
+ total_frame_length = 8 + len(payload)
+ frame_without_crc = struct.pack(
+ " tuple[list[tuple[int, bytes]], bytes]:
+ """
+ Extract every complete protocol frame from a byte stream buffer.
+
+ Returns a tuple of:
+ 1. a list of `(packet_type, payload)` tuples
+ 2. the unconsumed trailing bytes that do not yet form a full frame
+ """
+
+ extracted_packets: list[tuple[int, bytes]] = []
+ while len(buffered_bytes) >= 4:
+ if buffered_bytes[0] != FRAME_HEADER_MAGIC:
+ buffered_bytes = buffered_bytes[1:]
+ continue
+
+ total_frame_length = struct.unpack_from(" bytes:
+ """Build the ReferenceSettings payload."""
+
+ automatic_reference_switch = 0
+ external_input_configuration_bits = (
+ automatic_reference_switch << 0
+ | force_external_reference << 1
+ )
+ return struct.pack(
+ " bytes:
+ """Build the current protocol-v14 SweepSettings payload."""
+
+ excitation_power_centidecibels_milliwatt = int(sweep_configuration.power_dbm * 100)
+ dwell_time_microseconds = max(
+ 0,
+ min(int(sweep_configuration.dwell_us), 0xFFFF),
+ )
+ synchronization_mode = (
+ SYNC_MODE_HARDWARE_TRIGGER if synchronization_enabled else 0
+ )
+
+ configuration_bits = (
+ 0 << 0
+ | is_synchronization_master << 1
+ | 1 << 2
+ | 1 << 3
+ | 0 << 4
+ | synchronization_mode << 5
+ )
+
+ port_1_stimulus_stage = 0 if is_synchronization_master else 1
+ stage_configuration_bits = 0 | port_1_stimulus_stage << 3 | 1 << 6
+
+ return struct.pack(
+ " Optional[ParsedVnaDatapoint]:
+ """Decode one VNADatapoint payload into a structured Python object."""
+
+ fixed_header_length_bytes = 12
+ per_value_storage_length_bytes = 9
+
+ if len(payload) < fixed_header_length_bytes:
+ return None
+
+ frequency_hz, _power_level_centidecibels_milliwatt, point_index = struct.unpack_from(
+ " Optional[complex]:
+ """Look up one complex receiver value by stage, receiver type, and port number."""
+
+ required_port_bit = (1 << (required_port_number - 1)) if required_port_number else 0
+ for description_mask, complex_value in receiver_values_by_description_mask.items():
+ if (description_mask >> 5) != stage_index:
+ continue
+ if bool(description_mask & 0x10) != is_reference_receiver:
+ continue
+ if required_port_bit and not (description_mask & required_port_bit):
+ continue
+ return complex_value
+ return None
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/librevna_usb_transport.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/librevna_usb_transport.py
new file mode 100644
index 0000000..8e72b50
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/librevna_usb_transport.py
@@ -0,0 +1,169 @@
+import logging
+import queue
+import threading
+import time
+
+import usb.core
+import usb.util
+
+try:
+ import libusb_package
+except ImportError:
+ libusb_package = None
+
+from .librevna_device_protocol import (
+ PacketType,
+ encode_protocol_frame,
+ extract_complete_protocol_frames,
+)
+
+
+USB_VENDOR_ID = 0x1209
+USB_PRODUCT_ID = 0x4121
+USB_DATA_ENDPOINT_OUT = 0x01
+USB_DATA_ENDPOINT_IN = 0x81
+
+transport_logger = logging.getLogger(__name__)
+
+
+class LibreVnaUsbBackendError(RuntimeError):
+ """Raised when PyUSB cannot access a libusb backend."""
+
+
+def _build_missing_backend_message() -> str:
+ return (
+ "PyUSB could not find a libusb backend. "
+ "On Windows, install the Python USB backend with "
+ "`python -m pip install -r Python/requirements.txt` from the repository root "
+ "or `python -m pip install libusb-package` inside the active virtual environment. "
+ "If the LibreVNA GUI already sees the device, the USB driver is likely fine and "
+ "only the Python libusb DLL is missing."
+ )
+
+
+def _usb_find(**kwargs):
+ if libusb_package is not None:
+ return libusb_package.find(**kwargs)
+
+ try:
+ return usb.core.find(**kwargs)
+ except usb.core.NoBackendError as exc:
+ raise LibreVnaUsbBackendError(_build_missing_backend_message()) from exc
+
+
+class LibreVnaUsbBulkConnection:
+ """USB bulk transport wrapper for one LibreVNA device."""
+
+ _USB_TRANSFER_TIMEOUT_MS = 1_000
+
+ def __init__(self, serial_number: str) -> None:
+ usb_device = _usb_find(
+ idVendor=USB_VENDOR_ID,
+ idProduct=USB_PRODUCT_ID,
+ serial_number=serial_number,
+ )
+ if usb_device is None:
+ raise RuntimeError(f"LibreVNA with serial {serial_number!r} not found on USB")
+
+ try:
+ if usb_device.is_kernel_driver_active(0):
+ usb_device.detach_kernel_driver(0)
+ except (usb.core.USBError, NotImplementedError):
+ pass
+
+ usb_device.set_configuration()
+
+ self.serial_number = serial_number
+ self._usb_device = usb_device
+ self._received_packets: queue.Queue[tuple[int, bytes]] = queue.Queue()
+ self._stop_requested = threading.Event()
+ self._transmit_lock = threading.Lock()
+ self._receive_thread = threading.Thread(
+ target=self._receive_packets_forever,
+ daemon=True,
+ name=f"vna-rx-{serial_number[:8]}",
+ )
+ self._receive_thread.start()
+
+ def close(self) -> None:
+ self._stop_requested.set()
+ self._receive_thread.join(timeout=0.5)
+ usb.util.dispose_resources(self._usb_device)
+
+ def drain_received_packets(self) -> list[tuple[int, bytes]]:
+ """Remove all already-buffered packets without blocking."""
+
+ drained_packets: list[tuple[int, bytes]] = []
+ while True:
+ try:
+ drained_packets.append(self._received_packets.get_nowait())
+ except queue.Empty:
+ return drained_packets
+
+ def send_packet(self, packet_type: int, payload: bytes = b"") -> None:
+ with self._transmit_lock:
+ self._usb_device.write(
+ USB_DATA_ENDPOINT_OUT,
+ encode_protocol_frame(packet_type, payload),
+ timeout=self._USB_TRANSFER_TIMEOUT_MS,
+ )
+
+ def receive_packet(self, timeout_seconds: float = 2.0) -> tuple[int, bytes]:
+ """Wait for the next received packet."""
+
+ return self._received_packets.get(timeout=timeout_seconds)
+
+ def wait_for_acknowledgement(self, timeout_seconds: float = 2.0) -> None:
+ """Wait for an ACK packet while ignoring unrelated asynchronous packets."""
+
+ end_time_monotonic = time.monotonic() + timeout_seconds
+ while True:
+ remaining_seconds = end_time_monotonic - time.monotonic()
+ if remaining_seconds <= 0:
+ raise TimeoutError(f"ACK not received within {timeout_seconds} s")
+
+ packet_type, _payload = self.receive_packet(timeout_seconds=remaining_seconds)
+ if packet_type == PacketType.ACKNOWLEDGE:
+ return
+ if packet_type == PacketType.NEGATIVE_ACKNOWLEDGE:
+ raise RuntimeError("Device returned NACK")
+
+ def _receive_packets_forever(self) -> None:
+ buffered_bytes = b""
+ while not self._stop_requested.is_set():
+ try:
+ usb_chunk = bytes(
+ self._usb_device.read(
+ USB_DATA_ENDPOINT_IN,
+ 4096,
+ timeout=100,
+ )
+ )
+ except usb.core.USBTimeoutError:
+ continue
+ except Exception as exc:
+ if not self._stop_requested.is_set():
+ transport_logger.error(
+ "USB read error on %s: %s",
+ self.serial_number,
+ exc,
+ )
+ break
+
+ buffered_bytes += usb_chunk
+ extracted_packets, buffered_bytes = extract_complete_protocol_frames(
+ buffered_bytes
+ )
+ for packet in extracted_packets:
+ self._received_packets.put(packet)
+
+
+def list_connected_device_serial_numbers() -> list[str]:
+ """Return the serial numbers of all connected LibreVNA devices."""
+
+ connected_devices = _usb_find(
+ idVendor=USB_VENDOR_ID,
+ idProduct=USB_PRODUCT_ID,
+ find_all=True,
+ )
+ return [device.serial_number for device in (connected_devices or [])]
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/multi_device_vna_controller.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/multi_device_vna_controller.py
new file mode 100644
index 0000000..e46f47b
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/multi_device_vna_controller.py
@@ -0,0 +1,223 @@
+import time
+from collections.abc import Iterator, Sequence
+from dataclasses import replace
+from typing import Optional
+
+from .librevna_device_protocol import (
+ PacketType,
+ build_reference_settings_payload,
+ build_sweep_settings_payload,
+)
+from .librevna_usb_transport import (
+ LibreVnaUsbBulkConnection,
+)
+from .running_sweep_cycle_collection import collect_complete_running_sweep_cycles
+from .sweep_measurement_models import SweepConfiguration, SweepMeasurementResult
+
+
+class MultiDeviceVnaController:
+ """
+ Multi-device LibreVNA controller for synchronized forward S-parameter sweeps.
+
+ Port mapping:
+ master Port 1 / Port 2 → S11 / S21
+ slave 0 Port 1 / Port 2 → S31 / S41
+ slave 1 Port 1 / Port 2 → S51 / S61
+ """
+
+ def __init__(
+ self,
+ master_serial_number: str,
+ slave_serial_numbers: Sequence[str] = (),
+ force_external_reference: bool = True,
+ ) -> None:
+ self._master_device = LibreVnaUsbBulkConnection(master_serial_number)
+ self._slave_devices = [
+ LibreVnaUsbBulkConnection(slave_serial_number)
+ for slave_serial_number in slave_serial_numbers
+ ]
+ self._all_devices = [self._master_device, *self._slave_devices]
+ self._synchronization_enabled = len(self._slave_devices) > 0
+ self._force_external_reference = force_external_reference
+ self._reference_configuration_applied = False
+ self._last_applied_sweep_configuration: Optional[SweepConfiguration] = None
+ self._sweep_is_running = False
+ self._is_closed = False
+
+ def __enter__(self):
+ return self
+
+ def __exit__(self, *_):
+ self.close()
+
+ def close(self) -> None:
+ if self._is_closed:
+ return
+
+ self._is_closed = True
+ self._send_idle_to_all_devices()
+ for device_connection in self._all_devices:
+ device_connection.close()
+
+ def stop_continuous_sweep(self) -> None:
+ """Stop the currently running sweep without closing the controller."""
+
+ if self._is_closed:
+ return
+ self._send_idle_to_all_devices()
+
+ def configure_continuous_sweep(
+ self,
+ sweep_configuration: SweepConfiguration,
+ ) -> None:
+ """
+ Apply reference and sweep settings and leave the devices sweeping.
+
+ Reapplying the same sweep configuration is a no-op.
+ """
+
+ if self._is_closed:
+ raise RuntimeError("Controller is already closed")
+
+ if not self._reference_configuration_applied:
+ self._configure_reference_clocks()
+
+ if (
+ self._sweep_is_running
+ and self._last_applied_sweep_configuration == sweep_configuration
+ ):
+ return
+
+ if self._sweep_is_running:
+ self._send_idle_to_all_devices()
+ time.sleep(0.05)
+
+ self._drain_all_received_packets()
+ self._configure_sweep_on_all_devices(sweep_configuration)
+
+ def collect_running_sweep_cycles(
+ self,
+ cycle_count: int = 1,
+ ) -> SweepMeasurementResult:
+ """
+ Collect one or more complete cycles from the already-running sweep.
+
+ Call configure_continuous_sweep() first. The driver aligns itself to the
+ next full cycle in the incoming datapoint stream and then captures
+ exactly `cycle_count` complete cycles.
+ """
+
+ if self._is_closed:
+ raise RuntimeError("Controller is already closed")
+ if not self._sweep_is_running or self._last_applied_sweep_configuration is None:
+ raise RuntimeError(
+ "No running sweep is configured. Call configure_continuous_sweep() first."
+ )
+
+ try:
+ return collect_complete_running_sweep_cycles(
+ master_device_connection=self._master_device,
+ slave_device_connections=self._slave_devices,
+ active_sweep_configuration=self._last_applied_sweep_configuration,
+ cycle_count=cycle_count,
+ )
+ except Exception:
+ self._send_idle_to_all_devices()
+ raise
+
+ def iter_running_sweep_cycles(self) -> Iterator[SweepMeasurementResult]:
+ """Yield complete sweep cycles forever from the already-running sweep."""
+
+ while True:
+ yield self.collect_running_sweep_cycles(1)
+
+ def _send_command_and_wait_for_acknowledgement(
+ self,
+ device_connection: LibreVnaUsbBulkConnection,
+ packet_type: int,
+ payload: bytes = b"",
+ timeout_seconds: float = 3.0,
+ retry_count: int = 1,
+ ) -> None:
+ last_error: Optional[Exception] = None
+ for _attempt_index in range(retry_count + 1):
+ device_connection.send_packet(packet_type, payload)
+ try:
+ device_connection.wait_for_acknowledgement(
+ timeout_seconds=timeout_seconds
+ )
+ return
+ except Exception as exc:
+ last_error = exc
+
+ assert last_error is not None
+ raise last_error
+
+ def _try_send_command_without_failing(
+ self,
+ device_connection: LibreVnaUsbBulkConnection,
+ packet_type: int,
+ payload: bytes = b"",
+ timeout_seconds: float = 3.0,
+ retry_count: int = 1,
+ ) -> None:
+ try:
+ self._send_command_and_wait_for_acknowledgement(
+ device_connection,
+ packet_type,
+ payload,
+ timeout_seconds=timeout_seconds,
+ retry_count=retry_count,
+ )
+ except Exception:
+ pass
+
+ def _send_idle_to_all_devices(self) -> None:
+ for device_connection in self._all_devices:
+ self._try_send_command_without_failing(
+ device_connection,
+ PacketType.SET_IDLE,
+ timeout_seconds=3.0,
+ retry_count=1,
+ )
+ self._sweep_is_running = False
+
+ def _configure_reference_clocks(self) -> None:
+ for device_connection in self._all_devices:
+ self._send_command_and_wait_for_acknowledgement(
+ device_connection,
+ PacketType.REFERENCE_SETTINGS,
+ build_reference_settings_payload(0, self._force_external_reference),
+ timeout_seconds=3.0,
+ retry_count=1,
+ )
+
+ time.sleep(0.05)
+ self._reference_configuration_applied = True
+
+ def _configure_sweep_on_all_devices(
+ self,
+ sweep_configuration: SweepConfiguration,
+ ) -> None:
+ sweep_configuration_commands = [
+ *[(slave_device, False) for slave_device in self._slave_devices],
+ (self._master_device, True),
+ ]
+ for device_connection, is_synchronization_master in sweep_configuration_commands:
+ self._send_command_and_wait_for_acknowledgement(
+ device_connection,
+ PacketType.SWEEP_SETTINGS,
+ build_sweep_settings_payload(
+ sweep_configuration,
+ is_synchronization_master=is_synchronization_master,
+ synchronization_enabled=self._synchronization_enabled,
+ ),
+ timeout_seconds=3.0,
+ retry_count=1,
+ )
+ self._last_applied_sweep_configuration = replace(sweep_configuration)
+ self._sweep_is_running = True
+
+ def _drain_all_received_packets(self) -> None:
+ for device_connection in self._all_devices:
+ device_connection.drain_received_packets()
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/running_sweep_cycle_collection.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/running_sweep_cycle_collection.py
new file mode 100644
index 0000000..0d0c795
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/running_sweep_cycle_collection.py
@@ -0,0 +1,284 @@
+import queue
+import threading
+import time
+from collections.abc import Callable, Sequence
+from typing import Optional
+
+import numpy as np
+
+from .librevna_device_protocol import (
+ PacketType,
+ ParsedVnaDatapoint,
+ find_receiver_value,
+ parse_vna_datapoint_payload,
+)
+from .librevna_usb_transport import LibreVnaUsbBulkConnection
+from .sweep_measurement_models import SweepConfiguration, SweepMeasurementResult
+
+
+def collect_complete_running_sweep_cycles(
+ master_device_connection: LibreVnaUsbBulkConnection,
+ slave_device_connections: Sequence[LibreVnaUsbBulkConnection],
+ active_sweep_configuration: SweepConfiguration,
+ cycle_count: int,
+) -> SweepMeasurementResult:
+ """Collect complete cycles from an already-running synchronized sweep."""
+
+ cycle_count = int(cycle_count)
+ if cycle_count < 1:
+ raise ValueError("cycle_count must be >= 1")
+
+ all_device_connections = [master_device_connection, *slave_device_connections]
+ point_count = active_sweep_configuration.points
+ frequencies_hz = np.zeros(point_count, dtype=np.float64)
+ raw_receiver_measurements_by_s_parameter = {
+ s_parameter_name: np.full(
+ (cycle_count, point_count),
+ np.nan + 1j * np.nan,
+ dtype=complex,
+ )
+ for s_parameter_name in build_forward_s_parameter_names(len(slave_device_connections))
+ }
+ master_reference_measurements = np.full(
+ (cycle_count, point_count),
+ np.nan + 1j * np.nan,
+ dtype=complex,
+ )
+ collection_errors: list[Exception] = []
+ datapoint_counts_by_device_serial = {
+ device_connection.serial_number: 0
+ for device_connection in all_device_connections
+ }
+ stop_collection_requested = threading.Event()
+ datapoint_timeout_seconds = max(
+ 10.0,
+ active_sweep_configuration.dwell_us / 1_000_000 + 2.0,
+ )
+
+ def collect_datapoints_from_device(
+ device_connection: LibreVnaUsbBulkConnection,
+ handle_datapoint: Callable[[ParsedVnaDatapoint], bool],
+ ) -> None:
+ datapoints_received = 0
+ expected_datapoint_count = cycle_count * point_count
+ last_datapoint_timestamp = time.monotonic()
+
+ while datapoints_received < expected_datapoint_count:
+ if stop_collection_requested.is_set():
+ return
+
+ remaining_timeout_seconds = (
+ last_datapoint_timestamp + datapoint_timeout_seconds
+ ) - time.monotonic()
+ if remaining_timeout_seconds <= 0:
+ collection_errors.append(
+ TimeoutError(
+ f"No datapoints from {device_connection.serial_number} for "
+ f"{datapoint_timeout_seconds:.1f} s "
+ f"(received {datapoints_received}/{point_count})"
+ )
+ )
+ stop_collection_requested.set()
+ return
+
+ try:
+ packet_type, payload = device_connection.receive_packet(
+ timeout_seconds=min(1.0, remaining_timeout_seconds)
+ )
+ except (queue.Empty, TimeoutError) as exc:
+ if stop_collection_requested.is_set():
+ return
+ if isinstance(exc, queue.Empty):
+ continue
+ collection_errors.append(exc)
+ stop_collection_requested.set()
+ return
+
+ if packet_type != PacketType.VNA_DATAPOINT:
+ continue
+
+ parsed_datapoint = parse_vna_datapoint_payload(payload)
+ if parsed_datapoint and 0 <= parsed_datapoint.point_index < point_count:
+ last_datapoint_timestamp = time.monotonic()
+ datapoint_was_consumed = handle_datapoint(parsed_datapoint)
+ if datapoint_was_consumed:
+ datapoint_counts_by_device_serial[device_connection.serial_number] += 1
+ datapoints_received += 1
+
+ def build_cycle_tracking_handler(
+ cycle_aware_handler: Callable[[ParsedVnaDatapoint, int], None],
+ ) -> Callable[[ParsedVnaDatapoint], bool]:
+ cycle_tracking_state = {
+ "current_cycle_index": 0,
+ "previous_point_index": -1,
+ "has_seen_cycle_start": False,
+ }
+
+ def handle_datapoint(parsed_datapoint: ParsedVnaDatapoint) -> bool:
+ current_point_index = parsed_datapoint.point_index
+ if not cycle_tracking_state["has_seen_cycle_start"]:
+ if current_point_index != 0:
+ cycle_tracking_state["previous_point_index"] = current_point_index
+ return False
+ cycle_tracking_state["has_seen_cycle_start"] = True
+
+ if (
+ cycle_tracking_state["previous_point_index"] >= 0
+ and current_point_index < cycle_tracking_state["previous_point_index"]
+ ):
+ cycle_tracking_state["current_cycle_index"] += 1
+
+ cycle_tracking_state["previous_point_index"] = current_point_index
+ current_cycle_index = cycle_tracking_state["current_cycle_index"]
+ if current_cycle_index >= cycle_count:
+ return False
+
+ cycle_aware_handler(parsed_datapoint, current_cycle_index)
+ return True
+
+ return handle_datapoint
+
+ def handle_master_datapoint(
+ parsed_datapoint: ParsedVnaDatapoint,
+ cycle_index: int,
+ ) -> None:
+ point_index = parsed_datapoint.point_index
+ reference_receiver_value = find_receiver_value(
+ parsed_datapoint.receiver_values_by_description_mask,
+ stage_index=0,
+ is_reference_receiver=True,
+ )
+ if reference_receiver_value is None:
+ return
+
+ frequencies_hz[point_index] = parsed_datapoint.frequency_hz
+ master_reference_measurements[cycle_index, point_index] = reference_receiver_value
+
+ for receiver_port_number, s_parameter_name in ((1, "S11"), (2, "S21")):
+ port_receiver_value = find_receiver_value(
+ parsed_datapoint.receiver_values_by_description_mask,
+ stage_index=0,
+ is_reference_receiver=False,
+ required_port_number=receiver_port_number,
+ )
+ if port_receiver_value is not None:
+ raw_receiver_measurements_by_s_parameter[s_parameter_name][
+ cycle_index,
+ point_index,
+ ] = port_receiver_value
+
+ def build_slave_datapoint_handler(
+ slave_index: int,
+ ) -> Callable[[ParsedVnaDatapoint], bool]:
+ first_s_parameter_name = f"S{2 * slave_index + 3}1"
+ second_s_parameter_name = f"S{2 * slave_index + 4}1"
+
+ def handle_slave_datapoint(
+ parsed_datapoint: ParsedVnaDatapoint,
+ cycle_index: int,
+ ) -> None:
+ point_index = parsed_datapoint.point_index
+ for receiver_port_number, s_parameter_name in (
+ (1, first_s_parameter_name),
+ (2, second_s_parameter_name),
+ ):
+ port_receiver_value = find_receiver_value(
+ parsed_datapoint.receiver_values_by_description_mask,
+ stage_index=0,
+ is_reference_receiver=False,
+ required_port_number=receiver_port_number,
+ )
+ if port_receiver_value is not None:
+ raw_receiver_measurements_by_s_parameter[s_parameter_name][
+ cycle_index,
+ point_index,
+ ] = port_receiver_value
+
+ return build_cycle_tracking_handler(handle_slave_datapoint)
+
+ collection_threads = [
+ threading.Thread(
+ target=collect_datapoints_from_device,
+ args=(
+ master_device_connection,
+ build_cycle_tracking_handler(handle_master_datapoint),
+ ),
+ daemon=True,
+ name="collect-master",
+ ),
+ ]
+ for slave_index, slave_device_connection in enumerate(slave_device_connections):
+ collection_threads.append(
+ threading.Thread(
+ target=collect_datapoints_from_device,
+ args=(slave_device_connection, build_slave_datapoint_handler(slave_index)),
+ daemon=True,
+ name=f"collect-slave{slave_index}",
+ )
+ )
+
+ for collection_thread in collection_threads:
+ collection_thread.start()
+ for collection_thread in collection_threads:
+ collection_thread.join()
+
+ if collection_errors:
+ raise RuntimeError(
+ f"Sweep collection failed: {collection_errors[0]}"
+ ) from collection_errors[0]
+
+ if slave_device_connections and min(datapoint_counts_by_device_serial.values(), default=0) == 0:
+ raise RuntimeError(
+ "No datapoints received from at least one device; "
+ "hardware trigger sync did not start. Check Trigger Out/In loop "
+ "and 10 MHz reference wiring."
+ )
+
+ return SweepMeasurementResult(
+ frequencies_hz=frequencies_hz,
+ s_parameters=calculate_last_cycle_s_parameters(
+ raw_receiver_measurements_by_s_parameter,
+ master_reference_measurements,
+ ),
+ )
+
+
+def calculate_last_cycle_s_parameters(
+ raw_receiver_measurements_by_s_parameter: dict[str, np.ndarray],
+ master_reference_measurements: np.ndarray,
+) -> dict[str, np.ndarray]:
+ """Convert raw receiver captures from the final sweep cycle into S-parameters."""
+
+ if np.isnan(master_reference_measurements).any():
+ missing_reference_count = int(np.isnan(master_reference_measurements).sum())
+ raise RuntimeError(
+ f"Master reference missing for {missing_reference_count} datapoints"
+ )
+
+ s_parameters: dict[str, np.ndarray] = {}
+ for s_parameter_name, raw_receiver_measurements in (
+ raw_receiver_measurements_by_s_parameter.items()
+ ):
+ if np.isnan(raw_receiver_measurements).any():
+ missing_measurement_count = int(np.isnan(raw_receiver_measurements).sum())
+ raise RuntimeError(
+ f"Measurement {s_parameter_name} missing for "
+ f"{missing_measurement_count} datapoints"
+ )
+ s_parameters[s_parameter_name] = (
+ raw_receiver_measurements[-1] / master_reference_measurements[-1]
+ )
+
+ return s_parameters
+
+
+def build_forward_s_parameter_names(slave_device_count: int) -> list[str]:
+ """Return S-parameter names for the configured forward multi-device topology."""
+
+ s_parameter_names = ["S11", "S21"]
+ for slave_index in range(slave_device_count):
+ s_parameter_names += [
+ f"S{2 * slave_index + 3}1",
+ f"S{2 * slave_index + 4}1",
+ ]
+ return s_parameter_names
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/sweep_measurement_models.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/sweep_measurement_models.py
new file mode 100644
index 0000000..ea225dd
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/librevna_multi_device_driver/sweep_measurement_models.py
@@ -0,0 +1,23 @@
+from dataclasses import dataclass
+
+import numpy as np
+
+
+@dataclass
+class SweepConfiguration:
+ """User-facing configuration for one VNA sweep."""
+
+ start_hz: int = 100_000
+ stop_hz: int = 3_000_000_000
+ points: int = 201
+ if_bandwidth: int = 1_000
+ power_dbm: float = -10.0
+ dwell_us: int = 0
+
+
+@dataclass
+class SweepMeasurementResult:
+ """Measured sweep data from one or more complete sweep cycles."""
+
+ frequencies_hz: np.ndarray
+ s_parameters: dict[str, np.ndarray]
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/requirements.txt b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/requirements.txt
new file mode 100644
index 0000000..1eb0353
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/requirements.txt
@@ -0,0 +1,4 @@
+pyusb
+libusb-package; platform_system == "Windows"
+numpy
+matplotlib
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/sweep_result.csv b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/sweep_result.csv
new file mode 100644
index 0000000..fcf475c
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/sweep_result.csv
@@ -0,0 +1,1002 @@
+Frequency_Hz,S11_real,S11_imag,S21_real,S21_imag,S31_real,S31_imag,S41_real,S41_imag
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/sweep_result.png b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/sweep_result.png
new file mode 100644
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/sweep_result1.png b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/sweep_result1.png
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index 0000000..f6116a1
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/sweep_result_after.png b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/sweep_result_after.png
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/sweep_result_before.png b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/sweep_result_before.png
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/test_sweep.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/test_sweep.py
new file mode 100644
index 0000000..e5363f9
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Python/test_sweep.py
@@ -0,0 +1,336 @@
+"""
+test_sweep.py - run synchronized sweeps continuously and draw the latest cycle live.
+
+Usage
+-----
+List connected devices:
+ python test_sweep.py
+
+Single device (S11, S21):
+ python test_sweep.py
+
+Two devices - master + one slave (S11, S21, S31, S41):
+ python test_sweep.py
+
+Multi-device runs always use hardware trigger synchronization.
+Close the plot window or press Ctrl+C to stop the live sweep.
+"""
+
+import signal
+import sys
+import time
+from dataclasses import dataclass
+
+import matplotlib.pyplot as plt
+import numpy as np
+from matplotlib.axes import Axes
+from matplotlib.figure import Figure
+from matplotlib.lines import Line2D
+from matplotlib.text import Text
+
+from librevna_multi_device_driver import (
+ MultiDeviceVnaController,
+ SweepConfiguration,
+ SweepMeasurementResult,
+ list_connected_device_serial_numbers,
+)
+
+
+# Set to "internal" to keep each device on its own reference clock.
+DEFAULT_REFERENCE_SOURCE = "external"
+DEFAULT_SWEEP_CONFIGURATION = SweepConfiguration(
+ start_hz=100_000_000,
+ stop_hz=6_000_000_000,
+ points=501,
+ if_bandwidth=10000,
+ power_dbm=-10.0,
+)
+
+_ACTIVE_MEASUREMENT_CONTROLLER: MultiDeviceVnaController | None = None
+
+
+@dataclass
+class LiveSweepPlot:
+ figure: Figure
+ status_text: Text
+ magnitude_axis: Axes
+ phase_axes: list[Axes]
+ magnitude_lines: dict[str, Line2D]
+ phase_lines: dict[str, Line2D]
+
+
+def _force_external_reference_from_default_source() -> bool:
+ if DEFAULT_REFERENCE_SOURCE == "external":
+ return True
+ if DEFAULT_REFERENCE_SOURCE == "internal":
+ return False
+ raise ValueError(
+ "DEFAULT_REFERENCE_SOURCE must be either 'external' or 'internal'"
+ )
+
+
+def _parse_device_serial_numbers_from_command_line(
+ command_line_arguments: list[str],
+) -> list[str]:
+ for command_line_argument in command_line_arguments:
+ if command_line_argument.startswith("--"):
+ raise SystemExit(f"Unknown option: {command_line_argument}")
+ return command_line_arguments
+
+
+def _print_usage() -> None:
+ try:
+ connected_device_serial_numbers = list_connected_device_serial_numbers()
+ except RuntimeError as exc:
+ print(exc)
+ return
+
+ if not connected_device_serial_numbers:
+ print("No LibreVNA devices found. Check the USB connection and OS USB access.")
+ return
+
+ print("Connected LibreVNA devices:")
+ for connected_device_serial_number in connected_device_serial_numbers:
+ print(f" {connected_device_serial_number}")
+ print(f"\nUsage: {sys.argv[0]} [slave_serial ...]")
+
+
+def _install_termination_signal_handlers():
+ def handle_stop_signal(received_signal_number, _current_stack_frame) -> None:
+ global _ACTIVE_MEASUREMENT_CONTROLLER
+ if _ACTIVE_MEASUREMENT_CONTROLLER is not None:
+ try:
+ print(
+ f"\nSignal {received_signal_number} received, stopping devices...",
+ flush=True,
+ )
+ _ACTIVE_MEASUREMENT_CONTROLLER.close()
+ except Exception:
+ pass
+ raise SystemExit(128 + received_signal_number)
+
+ previous_sigint_handler = signal.getsignal(signal.SIGINT)
+ previous_sigterm_handler = signal.getsignal(signal.SIGTERM)
+ signal.signal(signal.SIGINT, handle_stop_signal)
+ signal.signal(signal.SIGTERM, handle_stop_signal)
+ return previous_sigint_handler, previous_sigterm_handler
+
+
+def _restore_termination_signal_handlers(
+ previous_sigint_handler,
+ previous_sigterm_handler,
+) -> None:
+ signal.signal(signal.SIGINT, previous_sigint_handler)
+ signal.signal(signal.SIGTERM, previous_sigterm_handler)
+
+
+def _print_run_header(
+ master_serial_number: str,
+ slave_serial_numbers: list[str],
+ sweep_configuration: SweepConfiguration,
+) -> None:
+ print(f"Master : {master_serial_number}")
+ for slave_index, slave_serial_number in enumerate(slave_serial_numbers):
+ print(f"Slave {slave_index} : {slave_serial_number}")
+ print(
+ "Sync : hardware trigger"
+ if slave_serial_numbers
+ else "Sync : disabled (single device)"
+ )
+ print(f"Ref : {DEFAULT_REFERENCE_SOURCE} on all devices")
+ print("Sweeps : continuous until Ctrl+C or the plot window is closed")
+ print(
+ f"Sweep : {sweep_configuration.start_hz / 1e6:.3f} MHz - "
+ f"{sweep_configuration.stop_hz / 1e6:.3f} MHz, "
+ f"{sweep_configuration.points} points, "
+ f"IF BW {sweep_configuration.if_bandwidth} Hz"
+ )
+ print("Running live sweep...")
+
+
+def main() -> None:
+ global _ACTIVE_MEASUREMENT_CONTROLLER
+
+ device_serial_numbers = _parse_device_serial_numbers_from_command_line(
+ sys.argv[1:]
+ )
+ if not device_serial_numbers:
+ _print_usage()
+ return
+
+ master_serial_number = device_serial_numbers[0]
+ slave_serial_numbers = device_serial_numbers[1:]
+ sweep_configuration = DEFAULT_SWEEP_CONFIGURATION
+ force_external_reference = _force_external_reference_from_default_source()
+ sweep_cycle_durations_seconds: list[float] = []
+
+ _print_run_header(
+ master_serial_number,
+ slave_serial_numbers,
+ sweep_configuration,
+ )
+ previous_sigint_handler, previous_sigterm_handler = (
+ _install_termination_signal_handlers()
+ )
+
+ try:
+ with MultiDeviceVnaController(
+ master_serial_number,
+ slave_serial_numbers,
+ force_external_reference=force_external_reference,
+ ) as measurement_controller:
+ _ACTIVE_MEASUREMENT_CONTROLLER = measurement_controller
+ measurement_controller.configure_continuous_sweep(sweep_configuration)
+ plt.ion()
+
+ live_plot: LiveSweepPlot | None = None
+ sweep_cycle_count = 0
+ print("Waiting for the first complete sweep cycle...")
+
+ while True:
+ if live_plot is not None and not plt.fignum_exists(live_plot.figure.number):
+ print("\nPlot window closed, stopping sweep.", flush=True)
+ break
+
+ cycle_collection_start_time = time.monotonic()
+ sweep_measurement_result = measurement_controller.collect_running_sweep_cycles(
+ 1,
+ )
+ cycle_duration_seconds = time.monotonic() - cycle_collection_start_time
+ sweep_cycle_durations_seconds.append(cycle_duration_seconds)
+ sweep_cycle_count += 1
+
+ if (
+ live_plot is not None
+ and not plt.fignum_exists(live_plot.figure.number)
+ ):
+ print("\nPlot window closed, stopping sweep.", flush=True)
+ break
+
+ if live_plot is None:
+ live_plot = _create_live_sweep_plot(sweep_measurement_result)
+
+ _update_live_sweep_plot(
+ live_plot,
+ sweep_measurement_result,
+ sweep_cycle_count=sweep_cycle_count,
+ last_cycle_duration_seconds=cycle_duration_seconds,
+ average_cycle_duration_seconds=float(
+ np.mean(sweep_cycle_durations_seconds)
+ ),
+ )
+ finally:
+ _ACTIVE_MEASUREMENT_CONTROLLER = None
+ _restore_termination_signal_handlers(
+ previous_sigint_handler,
+ previous_sigterm_handler,
+ )
+
+ if sweep_cycle_durations_seconds:
+ average_sweep_duration_seconds = float(np.mean(sweep_cycle_durations_seconds))
+ minimum_sweep_duration_seconds = float(np.min(sweep_cycle_durations_seconds))
+ maximum_sweep_duration_seconds = float(np.max(sweep_cycle_durations_seconds))
+ print(
+ "Sweep time (steady-state): "
+ f"{average_sweep_duration_seconds:.6f} s avg, "
+ f"{minimum_sweep_duration_seconds:.6f}-"
+ f"{maximum_sweep_duration_seconds:.6f} s "
+ f"over {len(sweep_cycle_durations_seconds)} cycles"
+ )
+ else:
+ print("Sweep time (steady-state): not enough repeated cycles to estimate")
+
+ print("Sweep stopped.")
+
+
+def _create_live_sweep_plot(
+ sweep_measurement_result: SweepMeasurementResult,
+) -> LiveSweepPlot:
+ frequencies_mhz = sweep_measurement_result.frequencies_hz / 1e6
+ s_parameter_names = sorted(sweep_measurement_result.s_parameters)
+ figure_height_inches = 3.5 + 2.5 * len(s_parameter_names)
+ figure, axes = plt.subplots(
+ 1 + len(s_parameter_names),
+ 1,
+ figsize=(10, figure_height_inches),
+ sharex=True,
+ )
+ axes = np.atleast_1d(axes)
+ magnitude_axis = axes[0]
+ phase_axes = list(axes[1:])
+ magnitude_lines: dict[str, Line2D] = {}
+ phase_lines: dict[str, Line2D] = {}
+
+ for s_parameter_name in s_parameter_names:
+ magnitude_line, = magnitude_axis.plot(
+ frequencies_mhz,
+ np.zeros_like(frequencies_mhz),
+ label=s_parameter_name,
+ linewidth=0.9,
+ )
+ magnitude_lines[s_parameter_name] = magnitude_line
+
+ magnitude_axis.set_title("Multi-port S-parameters (forward, Port 1 stimulus)")
+ magnitude_axis.set_ylabel("Magnitude (dB)")
+ magnitude_axis.set_ylim(-25, 0)
+ magnitude_axis.grid(True, alpha=0.4)
+ magnitude_axis.legend(loc="lower left")
+
+ for phase_axis, s_parameter_name in zip(phase_axes, s_parameter_names):
+ phase_line, = phase_axis.plot(
+ frequencies_mhz,
+ np.zeros_like(frequencies_mhz),
+ label=s_parameter_name,
+ linewidth=0.9,
+ )
+ phase_lines[s_parameter_name] = phase_line
+ phase_axis.set_ylabel("Phase (deg)")
+ phase_axis.set_title(f"{s_parameter_name} phase")
+ phase_axis.set_ylim(-180, 180)
+ phase_axis.grid(True, alpha=0.4)
+ phase_axis.legend(loc="lower left")
+
+ phase_axes[-1].set_xlabel("Frequency (MHz)")
+
+ status_text = figure.suptitle("")
+ figure.tight_layout(rect=(0, 0, 1, 0.97))
+ if figure.canvas.manager is not None:
+ figure.canvas.manager.set_window_title("LibreVNA Live Sweep")
+ plt.show(block=False)
+
+ return LiveSweepPlot(
+ figure=figure,
+ status_text=status_text,
+ magnitude_axis=magnitude_axis,
+ phase_axes=phase_axes,
+ magnitude_lines=magnitude_lines,
+ phase_lines=phase_lines,
+ )
+
+
+def _update_live_sweep_plot(
+ live_plot: LiveSweepPlot,
+ sweep_measurement_result: SweepMeasurementResult,
+ sweep_cycle_count: int,
+ last_cycle_duration_seconds: float,
+ average_cycle_duration_seconds: float,
+) -> None:
+ for s_parameter_name, complex_trace in sweep_measurement_result.s_parameters.items():
+ magnitude_db = 20 * np.log10(np.abs(complex_trace) + 1e-15)
+ phase_degrees = np.rad2deg(np.angle(complex_trace))
+ live_plot.magnitude_lines[s_parameter_name].set_ydata(magnitude_db)
+ live_plot.phase_lines[s_parameter_name].set_ydata(phase_degrees)
+
+ live_plot.status_text.set_text(
+ "Cycle "
+ f"{sweep_cycle_count} | "
+ f"Last {last_cycle_duration_seconds:.3f} s | "
+ f"Avg {average_cycle_duration_seconds:.3f} s"
+ )
+ live_plot.figure.canvas.draw_idle()
+ live_plot.figure.canvas.flush_events()
+ plt.pause(0.001)
+
+
+if __name__ == "__main__":
+ main()
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/README.md b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/README.md
new file mode 100644
index 0000000..8792869
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/README.md
@@ -0,0 +1,93 @@
+# LibreVNA
+
+  
+
+
+
+**100kHz to 6GHz VNA**
+
+This is the improved version of my [first attempt](https://www.github.com/jankae/VNA) at a VNA.
+
+
+
+## GUI Installation
+
+### Windows
+* Download the latest [Release](https://github.com/jankae/LibreVNA/releases) and unpack the zip file
+* Start the included LibreVNA-GUI.exe
+* No installation or driver is required, simply move the extracted folder somewhere convenient
+
+### Ubuntu
+* Download the latest [Release](https://github.com/jankae/LibreVNA/releases) and unpack the zip file
+* Install the required libraries:
+```console
+sudo apt install qt6-base-dev libqt6svg6
+```
+* Install the udev rule (otherwise you don't have the permissions to access the USB device):
+```console
+wget https://raw.githubusercontent.com/jankae/LibreVNA/master/Software/PC_Application/51-vna.rules
+sudo cp 51-vna.rules /etc/udev/rules.d
+```
+* Either reboot or reload the udev rules manually:
+```console
+sudo udevadm control --reload-rules
+sudo udevadm trigger
+```
+* You can now start GUI:
+```console
+cd $UNPACKED_ZIP_FOLDER$
+./LibreVNA-GUI
+```
+
+### MacOS
+* Download the latest [Release](https://github.com/jankae/LibreVNA/releases)
+ * If you are using MacOS 14+ use the release with `latest` in the name.
+ * If you are using MacOS >13.7 use the release with `13.7` in the name.
+* Unpack the zip file and move LibreVNA-GUI.app to your `/Applications` folder.
+* Start LibreVNA-GUI.app and add a security exception to allow the Mac to run the app with an "untrusted" signing key.
+* Launch app again.
+
+## Quick Start
+* You can find released versions of the GUI application and the device firmware [here](https://github.com/jankae/LibreVNA/releases).
+* If you would like to try out the newest features, the compiled versions of each commit can be found [here](https://github.com/jankae/LibreVNA/actions) (but keep in mind that some features might be unstable or incomplete). If you are having trouble downloading them, please refer to this [guide](Documentation/DeveloperInfo/DownloadActionBuilds.md).
+* An (incomplete) [user manual](Documentation/UserManual/manual.pdf) is also available.
+* If you would like to control the LibreVNA with a script, see the [SCPI Programming Guide](Documentation/UserManual/ProgrammingGuide.pdf).
+
+Please also take a look at the [FAQ](Documentation/FAQ.md).
+
+If you notice bugs or have ideas for improvements, please create an issue for that.
+
+For general questions or discussions, the [LibreVNA group](https://groups.io/g/LibreVNA-support/) is probably the best place.
+
+### Preliminary specifications
+Some [specifications](Documentation/UserManual/specsheet.pdf) are available but this project is still under development and the specifications might change.
+
+There are also some initial [example measurements](Documentation/Measurements/Measurements.md).
+
+## How does it work?
+The PCB is really only the RF frontend with some processing power. Everything else is handled in the PC application once the data is transferred via USB. You can try out the application without the PCB (obviously no measurements are possible, but you can import provided example measurements and get an idea about what it can and can't do).
+### RF path:
+
+
+* The main clock source is an Si5351C, providing all the required clocks for the different blocks. It also serves as the stimulus source for frequencies below 25MHz. Its own reference clock is either a 26MHz crystal or an external 10MHz signal.
+* The stimulus source for frequencies above 25MHz is a MAX2871. Its output signal is slightly filtered to reduce the amount of harmonics.
+* The stimulus signal power can be adjusted between approximately -42 and -10dbm with a digital attenuator (RFSA3714).
+* After the amplifier(TRF37A73) the signal is split and the weaker part of it fed into the reference receiver.
+* The stronger part of the signal can be routed to either port. In each signal path, two RF switches are used in series to achieve higher isolation between the ports.
+* Instead of directional couplers, resistive return-loss-bridges are used (easier to implement for wide bandwidth).
+* Both ports have completely separated receive paths. This increases BOM cost but allows measuring two parameters at once (S11 and S21 or S22 and S12). It also avoids potential isolation issues that could arise if the receive paths would merge into a single mixer/ADC.
+* Each receiver consists of two down-convert mixers. The 1.IF sits at 60MHz, the 2.IF 250kHz.
+* The ADCs are sampling the final IF with 16bit@800kHz.
+
+### Digital section:
+
+
+* The central element is the Spartan6 FPGA. It handles all communication with the RF blocks and samples the ADCs. This allows for nearly instant switching of the measurement frequency, only limited by the settling time of the PLLs.
+* The microcontroller handles the setup of the sweep in the FPGA, extracts and preprocesses the measurements and passes them on through USB.
+* The flash contains the FPGA bitstream. Because the microcontroller has access to the flash, no FPGA-related hardware tools (such as JTAG programmers) are needed, everything can be updated via USB.
+
+### Power supply:
+
+
+* Everything is powered from USB (or optionally by external 5V DC)
+* Almost every RF block has its own local regulater, preventing noise and signals coupling into the supply lines from propagating across the whole PCB
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/.gitignore b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/.gitignore
new file mode 100644
index 0000000..f7f8214
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/.gitignore
@@ -0,0 +1,5 @@
+/.metadata/
+RemoteSystemsTempFiles
+build-*
+*.pyc
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/.cproject b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/.cproject
new file mode 100644
index 0000000..0a0b02f
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/.cproject
@@ -0,0 +1,256 @@
+
+
+
+
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/.gitignore b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/.gitignore
new file mode 100644
index 0000000..3df573f
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/.gitignore
@@ -0,0 +1 @@
+/Debug/
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/.project b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/.project
new file mode 100644
index 0000000..261faf8
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/.project
@@ -0,0 +1,27 @@
+
+
+ SignalIDSamplerates
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.core.ccnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/.settings/language.settings.xml b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/.settings/language.settings.xml
new file mode 100644
index 0000000..0c22135
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/.settings/language.settings.xml
@@ -0,0 +1,48 @@
+
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/src/SignalIDSamplerates.cpp b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/src/SignalIDSamplerates.cpp
new file mode 100644
index 0000000..1bad090
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/HelperTools/SignalIDSamplerates/src/SignalIDSamplerates.cpp
@@ -0,0 +1,117 @@
+//============================================================================
+// Name : SignalIDSamplerates.cpp
+// Author :
+// Version :
+// Copyright : Your copyright notice
+// Description : Hello World in C++, Ansi-style
+//============================================================================
+
+#include
+#include
+#include
+#include
+using namespace std;
+
+constexpr int32_t freqRange = 20000000;
+constexpr int32_t freqStep = 4000;
+constexpr int32_t FPGA_CLK = 102400000;
+constexpr int32_t IF_freq = 250000;
+constexpr int32_t minAliasDistance = 100000;
+
+constexpr uint8_t minPrescaler = 112;
+constexpr uint8_t maxPrescaler = 180;
+constexpr uint8_t maxPrescalers = 5;
+
+int bestDistance;
+vector bestPrescalers;
+
+int Alias(int f, int f_s) {
+ // move into f_s range
+ f %= f_s;
+ if (f < 0) {
+ f += f_s;
+ }
+ // fold at half the samplerate
+ if(f >= f_s / 2) {
+ f = f_s - f;
+ }
+ return f;
+}
+
+int DistanceToIF(double f, double f_s) {
+ auto alias = Alias(f, f_s);
+ return abs(int(alias - IF_freq));
+}
+
+int farthestDistanceForFrequency(double f, vector &prescalers) {
+ int highestDistance = numeric_limits::min();
+
+ for(auto p : prescalers) {
+ double f_s = (double) FPGA_CLK / p;
+ auto dist = DistanceToIF(f, f_s);
+ if(dist > highestDistance) {
+ highestDistance = dist;
+ }
+ }
+ return highestDistance;
+}
+
+void checkPrescalers(vector &prescalers) {
+// cout << "Checking [" << prescalers[0];
+// for (auto i = prescalers.begin() + 1; i != prescalers.end(); i++) {
+// cout << ',' << *i;
+// }
+// cout << "]... ";
+ int lowestDistance = numeric_limits::max();
+ for(int freq = minAliasDistance + freqStep;freq < freqRange; freq += freqStep) {
+ int dist = farthestDistanceForFrequency(IF_freq + freq, prescalers);
+ if(dist < lowestDistance) {
+ lowestDistance = dist;
+ }
+ if(freq > 2*IF_freq + minAliasDistance) {
+ int dist = farthestDistanceForFrequency(IF_freq - freq, prescalers);
+ if(dist < lowestDistance) {
+ lowestDistance = dist;
+ }
+ }
+ if(lowestDistance < bestDistance) {
+ break;
+ }
+ }
+// cout << lowestDistance << endl;
+ if(lowestDistance > bestDistance) {
+ bestDistance = lowestDistance;
+ bestPrescalers = prescalers;
+ }
+}
+
+void recursivePrescalersTest(vector &prescalers, int depth) {
+ if(prescalers.size() >= depth) {
+ checkPrescalers(prescalers);
+ } else {
+ prescalers.push_back(0);
+ int start = minPrescaler;
+ if(prescalers.size() > 1) {
+ start = prescalers[prescalers.size() - 2] + 1;
+ }
+ for (int i = start; i <= maxPrescaler; i++) {
+ prescalers.back() = i;
+ recursivePrescalersTest(prescalers, depth);
+ }
+ prescalers.pop_back();
+ }
+}
+
+int main() {
+ vector prescalers = {112};
+ for(int d = 2;d<=maxPrescalers;d++) {
+ bestDistance = 0;
+ recursivePrescalersTest(prescalers, d);
+ cout << "Depth " << d <<": best distance: " << bestDistance << " Prescalers: [" << bestPrescalers[0];
+ for (auto i = bestPrescalers.begin() + 1; i != bestPrescalers.end(); i++) {
+ cout << ',' << *i;
+ }
+ cout << "]" << endl;
+ }
+ return 0;
+}
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/DUMMY.CALKIT b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/DUMMY.CALKIT
new file mode 100644
index 0000000..cbff17e
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/DUMMY.CALKIT
@@ -0,0 +1,60 @@
+{
+ "Description": "Dummy ideal calibration kit",
+ "Manufacturer": "LibreVNA",
+ "Serialnumber": "1234",
+ "standards": [
+ {
+ "params": {
+ "C0": 0.0,
+ "C1": 0.0,
+ "C2": 0.0,
+ "C3": 0.0,
+ "Z0": 50.0,
+ "delay": 0.0,
+ "id": 13726173464103258082,
+ "loss": 0.0,
+ "name": "Default"
+ },
+ "type": "Open"
+ },
+ {
+ "params": {
+ "L0": 0.0,
+ "L1": 0.0,
+ "L2": 0.0,
+ "L3": 0.0,
+ "Z0": 50.0,
+ "delay": 0.0,
+ "id": 13573063103112146609,
+ "loss": 0.0,
+ "name": "Default"
+ },
+ "type": "Short"
+ },
+ {
+ "params": {
+ "Cfirst": true,
+ "Cparallel": 0.0,
+ "Lseries": 0.0,
+ "Z0": 50.0,
+ "delay": 0.0,
+ "id": 11987083411312060381,
+ "loss": 0.0,
+ "name": "Default",
+ "resistance": 50.0
+ },
+ "type": "Load"
+ },
+ {
+ "params": {
+ "Z0": 50.0,
+ "delay": 0.0,
+ "id": 2916288069679020801,
+ "loss": 0.0,
+ "name": "Default"
+ },
+ "type": "Through"
+ }
+ ],
+ "version": "1.5.0-alpha.1-9b7f457aa"
+}
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/Integrationtest.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/Integrationtest.py
new file mode 100644
index 0000000..9ab9166
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/Integrationtest.py
@@ -0,0 +1,38 @@
+import unittest
+import glob, os
+
+testmodules = [
+ 'tests.TestUpdate', # Must go first because it updates the connected VNA to the firwmare which should be tested
+ 'tests.TestConnect',
+ 'tests.TestStatusRegisters',
+ 'tests.TestMode',
+ 'tests.TestTemperature',
+ 'tests.TestSync',
+ 'tests.TestVNASweep',
+ 'tests.TestCalibration',
+ 'tests.TestGenerator',
+ 'tests.TestSASweep',
+ 'tests.TestRST',
+ ]
+
+suite = unittest.TestSuite()
+
+# Clean up potential error logs from previous test runs
+for f in glob.glob("errorlog_*"):
+ os.remove(f)
+for f in glob.glob("packetlog_*"):
+ os.remove(f)
+
+for t in testmodules:
+ try:
+ # If the module defines a suite() function, call it to get the suite.
+ mod = __import__(t, globals(), locals(), ['suite'])
+ suitefn = getattr(mod, 'suite')
+ suite.addTest(suitefn())
+ except (ImportError, AttributeError):
+ # else, just load all the test cases from the module.
+ suite.addTest(unittest.defaultTestLoader.loadTestsFromName(t))
+
+result = unittest.TextTestRunner(verbosity=2).run(suite)
+exit(int(not result.wasSuccessful()))
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/LIBRECAL.cal b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/LIBRECAL.cal
new file mode 100644
index 0000000..5a96bb7
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/LIBRECAL.cal
@@ -0,0 +1,117652 @@
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+ ],
+ "frequency": 5964006000.0
+ },
+ {
+ "Sparams": [
+ {
+ "imag": -0.19168,
+ "real": 0.213315
+ }
+ ],
+ "frequency": 5976004000.0
+ },
+ {
+ "Sparams": [
+ {
+ "imag": -0.198697,
+ "real": 0.215553
+ }
+ ],
+ "frequency": 5988002000.0
+ },
+ {
+ "Sparams": [
+ {
+ "imag": -0.201435,
+ "real": 0.220324
+ }
+ ],
+ "frequency": 6000000000.0
+ }
+ ],
+ "filename": "LibreCAL/P4_LOAD",
+ "ports": 1
+ }
+ },
+ "type": "Load"
+ }
+ ],
+ "version": "1.5.0-alpha.1-2b9cc78e5"
+ },
+ "device": "208939A23350",
+ "format": 3,
+ "measurements": [
+ {
+ "data": {
+ "points": null,
+ "port": 1,
+ "standard": 5762845714384679112,
+ "timestamp": -3600
+ },
+ "type": "Open"
+ },
+ {
+ "data": {
+ "points": null,
+ "port": 1,
+ "standard": 3508904253150165021,
+ "timestamp": -3600
+ },
+ "type": "Short"
+ },
+ {
+ "data": {
+ "points": null,
+ "port": 1,
+ "standard": 10623207317598837575,
+ "timestamp": -3600
+ },
+ "type": "Load"
+ },
+ {
+ "data": {
+ "points": null,
+ "port": 2,
+ "standard": 5265997809752029671,
+ "timestamp": -3600
+ },
+ "type": "Open"
+ },
+ {
+ "data": {
+ "points": null,
+ "port": 2,
+ "standard": 5569943011892084756,
+ "timestamp": -3600
+ },
+ "type": "Short"
+ },
+ {
+ "data": {
+ "points": null,
+ "port": 2,
+ "standard": 5506100953055748068,
+ "timestamp": -3600
+ },
+ "type": "Load"
+ },
+ {
+ "data": {
+ "points": null,
+ "port1": 1,
+ "port2": 2,
+ "reverseStandard": true,
+ "standard": 14293876623961490041,
+ "timestamp": -3600
+ },
+ "type": "Through"
+ }
+ ],
+ "ports": null,
+ "type": "None",
+ "version": "1.5.0-alpha.1-2b9cc78e5"
+}
\ No newline at end of file
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/errorlog_20250106173311.txt b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/errorlog_20250106173311.txt
new file mode 100644
index 0000000..5dee19d
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/errorlog_20250106173311.txt
@@ -0,0 +1,22 @@
+ 0.027: [debug] Application start
+ 0.045: [info] Listening on port 19544
+ 0.060: [debug] Activating mode "Vector Network Analyzer"
+ 0.068: [debug] Updated device list, found 1
+ 0.068: [debug] Trying to connect to "208A367A4B42"
+ 0.068: [debug] Attempting to connect to device...
+ 0.075: [info] USB connection established
+ 0.075: [debug] Receive thread started
+ 0.075: [debug] Transmission started (packet type 15 ), queue at 1
+ 0.078: [info] Connected to "208A367A4B42"
+ 0.079: [debug] Transmission started (packet type 26 ), queue at 1
+ 0.082: [debug] No default calibration file set for this device
+ 0.082: [debug] Transmission started (packet type 11 ), queue at 1
+ 0.187: [debug] Transmission started (packet type 2 ), queue at 1
+ 0.533: [debug] Attempting to open calibration from file "LIBRECAL.cal"
+ 0.533: [debug] Associated calibration kit expected in "LIBRECAL.calkit"
+ 0.533: [debug] Opening calkit to file "LIBRECAL.calkit"
+ 0.533: [debug] Parsing of calibration kit failed while opening calibration file: Unable to open file (ignore for calibration format >= 3)
+ 0.899: [debug] Transmission started (packet type 2 ), queue at 1
+ 1.007: [debug] Deactivated mode "Vector Network Analyzer"
+ 1.007: [debug] Transmission started (packet type 20 ), queue at 1
+ 1.050: [debug] Disconnected, receive thread exiting
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/libreCAL.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/libreCAL.py
new file mode 100644
index 0000000..33cf78a
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/libreCAL.py
@@ -0,0 +1,88 @@
+import serial
+import serial.tools.list_ports
+from enum import Enum
+
+class libreCAL:
+ def __init__(self, serialnum = ''):
+ self.ser = None
+ for p in serial.tools.list_ports.comports():
+ if (p.vid == 0x0483 and p.pid == 0x4122) or (p.vid == 0x1209 and p.pid == 0x4122):
+ self.ser = serial.Serial(p.device, timeout = 1)
+ idn = self.SCPICommand("*IDN?").split(",")
+ if idn[0] != "LibreCAL":
+ self.ser = None
+ continue
+ self.serial = idn[2]
+ if len(serialnum) > 0:
+ # serial number specified, compare
+ if self.serial != serialnum:
+ self.ser = None
+ continue
+ break
+ if self.ser == None:
+ if len(serialnum) > 0:
+ raise Exception("LibreCAL with serial number '"+serialnum+"' not detected")
+ else:
+ raise Exception("No LibreCAL device detected")
+
+ def getSerial(self) -> str:
+ return self.serial
+
+ class Standard(Enum):
+ NONE = 0,
+ OPEN = 1,
+ SHORT = 2,
+ LOAD = 3,
+ THROUGH = 4
+
+ def reset(self):
+ self.SCPICommand(":PORT 1 NONE")
+ self.SCPICommand(":PORT 2 NONE")
+ self.SCPICommand(":PORT 3 NONE")
+ self.SCPICommand(":PORT 4 NONE")
+
+ def setPort(self, s : Standard, port, port2 = -1):
+ if s == self.Standard.THROUGH and port2 == -1:
+ raise Exception("When setting a port to THROUGH, the destination port must also be specified")
+ cmd = ":PORT "+str(port)+" "+s.name
+ if s == self.Standard.THROUGH:
+ cmd += " "+str(port2)
+ if len(self.SCPICommand(cmd)) == 0:
+ return True
+ else:
+ return False
+
+ def getPort(self, port):
+ resp = self.SCPICommand(":PORT? "+str(port)).split(" ")[0]
+ try:
+ s = self.Standard[resp]
+ return s
+ except:
+ raise Exception("LibreCAL reported unknown standard '"+resp+"'")
+
+ def getTemperature(self):
+ return float(self.SCPICommand(":TEMP?"))
+
+ def isStable(self) -> bool:
+ if self.SCPICommand(":TEMP:STABLE?") == "TRUE":
+ return True
+ else:
+ return False
+
+ def getHeaterPower(self):
+ return float(self.SCPICommand(":HEAT:POW?"))
+
+ def getDateTimeUTC(self):
+ return self.SCPICommand(":DATE_TIME?")
+
+ def setDateTimeUTC(self, date_time_utc):
+ return self.SCPICommand(":DATE_TIME "+ date_time_utc)
+
+ def SCPICommand(self, cmd: str) -> str:
+ self.ser.write((cmd+"\r\n").encode())
+ resp = self.ser.readline().decode("ascii")
+ if len(resp) == 0:
+ raise Exception("Timeout occurred in communication with LibreCAL")
+ if resp.strip() == "ERROR":
+ raise Exception("LibreCAL returned 'ERROR' for command '"+cmd+"'")
+ return resp.strip()
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/packetlog_20250106173310.vnalog b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/packetlog_20250106173310.vnalog
new file mode 100644
index 0000000..1919889
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/packetlog_20250106173310.vnalog
@@ -0,0 +1 @@
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\ No newline at end of file
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestBase.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestBase.py
new file mode 100644
index 0000000..b8f6cac
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestBase.py
@@ -0,0 +1,75 @@
+import unittest
+from tests.libreVNA import libreVNA as libreVNA
+import tests.definitions as defs
+import subprocess
+import time
+import select
+import os
+from signal import SIGINT
+
+class TestBase(unittest.TestCase):
+ def setUp(self):
+ f = open("log.txt", "w")
+ self.gui = subprocess.Popen([defs.GUI_PATH, '-p', '19544', '--reset-preferences', '--no-gui', '-platform', 'offscreen'], stdout=f, stderr=subprocess.STDOUT)
+
+ # wait for the SCPI server to become available
+ timeout = time.time() + 3;
+ fread = open("log.txt", "r")
+ while True:
+ text = fread.read()
+ if text and "Listening on port 19544" in text:
+ break
+ if time.time() >= timeout:
+ self.tearDown()
+ raise AssertionError("Timed out waiting for SCPI server")
+
+ self.vna = libreVNA('localhost', 19544, timeout=4)
+ try:
+ self.vna.cmd("*CLS")
+ except Exception as e:
+ self.tearDown()
+ raise e
+ if self.vna.query(":DEV:CONN?") == "Not connected":
+ self.tearDown()
+ raise AssertionError("Not connected")
+
+
+ def tearDown(self):
+ if hasattr(self._outcome, 'errors'):
+ # Python 3.4 - 3.10 (These two methods have no side effects)
+ result = self.defaultTestResult()
+ self._feedErrorsToResult(result, self._outcome.errors)
+ else:
+ # Python 3.11+
+ result = self._outcome.result
+ ok = all(test != self for test, text in result.errors + result.failures)
+
+ if not ok:
+ try:
+ # Try to grab the packet log and save it
+ packetlog = self.vna.query(":DEV:PACKETLOG?", timeout=5)
+ f = open("packetlog_"+time.strftime("%Y%m%d%H%M%S.vnalog"), "w")
+ f.write(packetlog)
+ f.close()
+ except:
+ pass
+
+ # make sure the GUI did not crash during the test
+ crashed = self.gui.poll() is not None
+ self.gui.send_signal(SIGINT)
+ try:
+ self.gui.wait(timeout = 3)
+ except subprocess.TimeoutExpired:
+ self.gui.kill()
+
+
+ if ok and not crashed:
+ # remove log file
+ os.remove("log.txt")
+ else:
+ os.rename("log.txt", "errorlog_"+time.strftime("%Y%m%d%H%M%S.txt"))
+
+ if(crashed):
+ raise Exception("GUI crashed")
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestCalibration.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestCalibration.py
new file mode 100644
index 0000000..3ed3709
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestCalibration.py
@@ -0,0 +1,175 @@
+from tests.TestBase import TestBase
+from libreCAL import libreCAL
+import time
+import math
+
+class TestCalibration(TestBase):
+ def cal_measure(self, number, timeout = 3):
+ self.vna.cmd(":VNA:CAL:MEAS "+str(number))
+ # wait for the measurement to finish
+ assert self.vna.query(":VNA:CAL:BUSY?") == "TRUE"
+ self.vna.cmd("*WAI", timeout=timeout)
+ assert self.vna.query(":VNA:CAL:BUSY?") == "FALSE"
+
+ def test_dummy_calibration(self):
+ # This test just iterates through the calibration steps. As no actual standards
+ # are applied to the ports, the calibration result is just random data
+ # Set up the sweep first
+ self.vna.cmd(":DEV:MODE VNA")
+ self.vna.cmd(":VNA:SWEEP FREQUENCY")
+ self.vna.cmd(":VNA:STIM:LVL -10")
+ self.vna.cmd(":VNA:ACQ:IFBW 50000")
+ self.vna.cmd(":VNA:ACQ:AVG 1")
+ self.vna.cmd(":VNA:ACQ:POINTS 501")
+ self.vna.cmd(":VNA:FREQuency:START 1000000")
+ self.vna.cmd(":VNA:FREQuency:STOP 6000000000")
+
+ self.vna.cmd(":VNA:CAL:RESET")
+
+ # No measurements yet, activating should fail
+ self.vna.cmd(":VNA:CAL:ACT SOLT_1", check=False)
+ self.assertTrue(self.vna.get_status() & 0x3C)
+
+ # Load calibration kit
+ self.assertEqual(self.vna.query(":VNA:CAL:KIT:LOAD? DUMMY.CALKIT"), "TRUE")
+
+ # Lets take the measurements for port 1 first
+ self.vna.cmd(":VNA:CAL:ADD OPEN")
+ self.vna.cmd(":VNA:CAL:ADD SHORT")
+ self.vna.cmd(":VNA:CAL:ADD LOAD")
+ self.vna.cmd(":VNA:CAL:PORT 0 1")
+ self.vna.cmd(":VNA:CAL:PORT 1 1")
+ self.vna.cmd(":VNA:CAL:PORT 2 1")
+
+ self.cal_measure(0)
+ self.cal_measure(1)
+ self.cal_measure(2)
+
+ # SOLT_1 should now be available
+ self.vna.cmd(":VNA:CAL:ACT SOLT_1", check=False)
+ self.assertFalse(self.vna.get_status() & 0x3C)
+
+ # SOLT_2 and SOLT_12 should still be unavailable
+ self.vna.cmd(":VNA:CAL:ACT SOLT_2", check=False)
+ self.assertTrue(self.vna.get_status() & 0x3C)
+ self.vna.cmd(":VNA:CAL:ACT SOLT_12", check=False)
+ self.assertTrue(self.vna.get_status() & 0x3C)
+
+ # Take measurements for SOLT_2
+ self.vna.cmd(":VNA:CAL:ADD OPEN")
+ self.vna.cmd(":VNA:CAL:ADD SHORT")
+ self.vna.cmd(":VNA:CAL:ADD LOAD")
+ self.vna.cmd(":VNA:CAL:PORT 3 2")
+ self.vna.cmd(":VNA:CAL:PORT 4 2")
+ self.vna.cmd(":VNA:CAL:PORT 5 2")
+
+ self.cal_measure(3)
+ self.cal_measure(4)
+ self.cal_measure(5)
+
+ # SOLT_1 and SOLT_2 should now be available
+ self.vna.cmd(":VNA:CAL:ACT SOLT_1", check=False)
+ self.assertFalse(self.vna.get_status() & 0x3C)
+ self.vna.cmd(":VNA:CAL:ACT SOLT_2", check=False)
+ self.assertFalse(self.vna.get_status() & 0x3C)
+
+ # SOLT_12 should still be unavailable
+ self.vna.cmd(":VNA:CAL:ACT SOLT_12", check=False)
+ self.assertTrue(self.vna.get_status() & 0x3C)
+
+ # Take the final through measurement for SOLT_12
+ self.vna.cmd(":VNA:CAL:ADD THROUGH")
+ self.vna.cmd(":VNA:CAL:PORT 6 1 2")
+
+ self.cal_measure(6)
+
+ # SOLT_1, SOLT_2 and SOLT_12 should now be available
+ self.vna.cmd(":VNA:CAL:ACT SOLT_1", check=False)
+ self.assertFalse(self.vna.get_status() & 0x3C)
+ self.vna.cmd(":VNA:CAL:ACT SOLT_2", check=False)
+ self.assertFalse(self.vna.get_status() & 0x3C)
+ self.vna.cmd(":VNA:CAL:ACT SOLT_12", check=False)
+ self.assertFalse(self.vna.get_status() & 0x3C)
+
+ def assertTrace_dB(self, trace, dB_nominal, dB_deviation):
+ for S in trace:
+ dB = 20*math.log10(abs(S[1]))
+ self.assertLessEqual(dB, dB_nominal + dB_deviation)
+ self.assertGreaterEqual(dB, dB_nominal - dB_deviation)
+
+ def test_SOLT_calibration(self):
+ # This test performs a 2-port SOLT calibration with a connected LibreCAL
+ # Afterwqrds, the calibration is checked with a 6dB attenuator
+ # Set up the sweep first
+ self.vna.cmd(":DEV:MODE VNA")
+ self.vna.cmd(":VNA:SWEEP FREQUENCY")
+ self.vna.cmd(":VNA:STIM:LVL -10")
+ self.vna.cmd(":VNA:ACQ:IFBW 1000")
+ self.vna.cmd(":VNA:ACQ:AVG 1")
+ self.vna.cmd(":VNA:ACQ:POINTS 501")
+ self.vna.cmd(":VNA:FREQuency:START 50000000")
+ self.vna.cmd(":VNA:FREQuency:STOP 6000000000")
+
+ self.vna.cmd(":VNA:CAL:RESET")
+
+ # Load calibration file (only for standard and measurement setup, no
+ # measurements are included)
+ self.assertEqual(self.vna.query(":VNA:CAL:LOAD? LIBRECAL.CAL"), "TRUE")
+
+ # Take the measurements
+
+ cal = libreCAL()
+ # Connections:
+ # LibreVNA -> LibreCAL
+ # 1 -> 3
+ # 2 -> 1
+ cal.reset()
+ cal.setPort(cal.Standard.OPEN, 1)
+ cal.setPort(cal.Standard.OPEN, 3)
+ self.cal_measure(0, 15)
+ self.cal_measure(3, 15)
+
+ cal.setPort(cal.Standard.SHORT, 1)
+ cal.setPort(cal.Standard.SHORT, 3)
+ self.cal_measure(1, 15)
+ self.cal_measure(4, 15)
+
+ cal.setPort(cal.Standard.LOAD, 1)
+ cal.setPort(cal.Standard.LOAD, 3)
+ self.cal_measure(2, 15)
+ self.cal_measure(5, 15)
+
+ cal.setPort(cal.Standard.THROUGH, 1, 3)
+ self.cal_measure(6, 15)
+
+ # activate calibration
+ self.vna.cmd(":VNA:CAL:ACT SOLT_12", check=False)
+ self.assertFalse(self.vna.get_status() & 0x3C)
+
+ # switch in 6dB attenuator
+ cal.setPort(cal.Standard.THROUGH, 1, 2)
+ cal.setPort(cal.Standard.THROUGH, 3, 4)
+
+ # Start measurement and grab data
+ self.vna.cmd(":VNA:ACQ:SINGLE TRUE")
+ self.assertEqual(self.vna.query(":VNA:ACQ:FIN?"), "FALSE")
+ self.vna.cmd("*WAI", timeout=3)
+ self.assertEqual(self.vna.query(":VNA:ACQ:FIN?"), "TRUE")
+
+ cal.reset()
+
+ # grab trace data
+ S11 = self.vna.parse_VNA_trace_data(self.vna.query(":VNA:TRACE:DATA? S11"))
+ S12 = self.vna.parse_VNA_trace_data(self.vna.query(":VNA:TRACE:DATA? S12"))
+ S21 = self.vna.parse_VNA_trace_data(self.vna.query(":VNA:TRACE:DATA? S21"))
+ S22 = self.vna.parse_VNA_trace_data(self.vna.query(":VNA:TRACE:DATA? S22"))
+
+ # Attenuation is frequency dependent, use excessively large limits
+ # TODO: use smaller limits based on frequency
+ self.assertTrace_dB(S12, -13, 5)
+ self.assertTrace_dB(S21, -13, 5)
+
+ # Reflection should be below -10dB (much lower for most frequencies)
+ self.assertTrace_dB(S11, -100, 91)
+ self.assertTrace_dB(S22, -100, 91)
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestConnect.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestConnect.py
new file mode 100644
index 0000000..196bbdc
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestConnect.py
@@ -0,0 +1,13 @@
+from tests.TestBase import TestBase
+
+class TestConnect(TestBase):
+ def test_connection(self):
+ self.vna.cmd(":DEV:DISC")
+ self.assertEqual(self.vna.query(":DEV:CONN?"), "Not connected")
+ self.vna.cmd(":DEV:CONN")
+ self.assertNotEqual(self.vna.query(":DEV:CONN?"), "Not connected")
+
+ def test_list(self):
+ list = self.vna.query(":DEV:LIST?")
+ serials = list.split(',')
+ self.assertEqual(len(serials), 1)
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestGenerator.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestGenerator.py
new file mode 100644
index 0000000..463e974
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestGenerator.py
@@ -0,0 +1,16 @@
+from tests.TestBase import TestBase
+
+class TestGenerator(TestBase):
+ def test_Generator(self):
+ self.vna.cmd(":DEV:MODE GEN")
+ self.assertEqual(self.vna.query(":DEV:MODE?"), "GEN")
+
+ self.vna.cmd(":GEN:FREQ 2000000000")
+ self.assertEqual(float(self.vna.query(":GEN:FREQ?")), 2000000000)
+
+ self.vna.cmd(":GEN:LVL -12.34")
+ self.assertEqual(float(self.vna.query(":GEN:LVL?")), -12.34)
+
+ self.assertEqual(self.vna.query(":GEN:PORT?"), "0")
+ self.vna.cmd(":GEN:PORT 2")
+ self.assertEqual(self.vna.query(":GEN:PORT?"), "2")
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestMode.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestMode.py
new file mode 100644
index 0000000..78fcf8a
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestMode.py
@@ -0,0 +1,8 @@
+from tests.TestBase import TestBase
+
+class TestMode(TestBase):
+ def test_Mode(self):
+ modes = ["VNA", "GEN", "SA"]
+ for m in modes:
+ self.vna.cmd(":DEV:MODE "+m)
+ self.assertEqual(self.vna.query(":DEV:MODE?"), m)
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestRST.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestRST.py
new file mode 100644
index 0000000..3471934
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestRST.py
@@ -0,0 +1,245 @@
+import re
+from tests.TestBase import TestBase
+import time
+
+float_re = re.compile(r'^[-+]?(\d+(\.\d*)?|\.\d+)([eE][-+]\d+)?$')
+int_re = re.compile(r'^\d+$')
+lowerq_re = re.compile('[a-z?]')
+
+queries = [
+ # Limits used to validate other parameters
+ ("float", "DEVice:INFo:LIMits:MINFrequency?"),
+ ("float", "DEVice:INFo:LIMits:MAXFrequency?"),
+ ("float", "DEVice:INFo:LIMits:MINIFBW?"),
+ ("float", "DEVice:INFo:LIMits:MAXIFBW?"),
+ ("int", "DEVice:INFo:LIMits:MAXPoints?"),
+ ("float", "DEVice:INFo:LIMits:MINPOWer?"),
+ ("float", "DEVice:INFo:LIMits:MAXPOWer?"),
+ ("float", "DEVice:INFo:LIMits:MINRBW?"),
+ ("float", "DEVice:INFo:LIMits:MAXRBW?"),
+
+ # Settable parameters without query arguments
+ ("str", "DEVice:MODE?"),
+ ("str", "DEVice:REFerence:IN?"),
+ ("str", "DEVice:REFerence:OUT?"),
+ ("float", "GENerator:FREQuency?"),
+ ("float", "GENerator:LVL?"),
+ ("int", "GENerator:PORT?"),
+ ("int", "SA:ACQuisition:AVG?"),
+ ("str", "SA:ACQuisition:DETector?"),
+ ("float", "SA:ACQuisition:RBW?"),
+ ("bool", "SA:ACQuisition:RUN?"),
+ ("bool", "SA:ACQuisition:SINGLE?"),
+ ("str", "SA:ACQuisition:WINDow?"),
+ ("float", "SA:FREQuency:CENTer?"),
+ ("float", "SA:FREQuency:SPAN?"),
+ ("float", "SA:FREQuency:START?"),
+ ("float", "SA:FREQuency:STOP?"),
+ ("bool", "SA:TRACKing:ENable?"),
+ ("float", "SA:TRACKing:LVL?"),
+ ("bool", "SA:TRACKing:NORMalize:ENable?"),
+ ("float", "SA:TRACKing:NORMalize:LVL?"),
+ ("float", "SA:TRACKing:OFFset?"),
+ ("int", "SA:TRACKing:Port?"),
+ ("int", "VNA:ACQuisition:AVG?"),
+ ("float", "VNA:ACQuisition:IFBW?"),
+ ("int", "VNA:ACQuisition:POINTS?"),
+ ("bool", "VNA:ACQuisition:RUN?"),
+ ("bool", "VNA:ACQuisition:SINGLE?"),
+ ("str", "VNA:CALibration:ACTivate?"),
+ ("int", "VNA:DEEMBedding:NUMber?"),
+ ("float", "VNA:FREQuency:CENTer?"),
+ ("float", "VNA:FREQuency:SPAN?"),
+ ("float", "VNA:FREQuency:START?"),
+ ("float", "VNA:FREQuency:STOP?"),
+ ("float", "VNA:POWer:START?"),
+ ("float", "VNA:POWer:STOP?"),
+ ("float", "VNA:STIMulus:FREQuency?"),
+ ("float", "VNA:STIMulus:LVL?"),
+ ("str", "VNA:SWEEP?"),
+]
+
+
+class TestRST(TestBase):
+ def query_settings(self) -> dict:
+ result = dict()
+ for qtype, query in queries:
+ resp = self.vna.query(query)
+ if qtype == "float":
+ self.assertTrue(float_re.match(resp),
+ f"Expected float from {query}; got: '{resp}'")
+ value = float(resp)
+ elif qtype == "int":
+ self.assertTrue(int_re.match(resp),
+ f"Expected int from {query}; got: '{resp}'")
+ value = int(resp)
+ elif qtype == "bool":
+ self.assertTrue(resp == "TRUE" or resp == "FALSE",
+ f"Expected bool from {query}; got: '{resp}'")
+ value = True if resp == "TRUE" else False
+ elif qtype == "str":
+ value = resp
+ else:
+ assert False, "invalid type in table"
+
+ query = re.sub(lowerq_re, r'', query)
+ result[query] = value
+
+ return result
+
+ def validate_settings(self, settings):
+ # Copy limits into local vars
+ f_min = settings["DEV:INF:LIM:MINF"]
+ f_max = settings["DEV:INF:LIM:MAXF"]
+ ifbw_min = settings["DEV:INF:LIM:MINIFBW"]
+ ifbw_max = settings["DEV:INF:LIM:MAXIFBW"]
+ points_max = settings["DEV:INF:LIM:MAXP"]
+ pwr_min = settings["DEV:INF:LIM:MINPOW"]
+ pwr_max = settings["DEV:INF:LIM:MAXPOW"]
+ rbw_min = settings["DEV:INF:LIM:MINRBW"]
+ rbw_max = settings["DEV:INF:LIM:MAXRBW"]
+
+ # Validate select settings
+ self.assertEqual(settings["DEV:MODE"], "VNA")
+ self.assertEqual(settings["DEV:REF:IN"], "INT")
+ self.assertEqual(settings["DEV:REF:OUT"], "OFF") # can't source pwr
+
+ f = settings["GEN:FREQ"]
+ self.assertGreaterEqual(f, f_min)
+ self.assertLessEqual(f, f_max)
+
+ pwr = settings["GEN:LVL"]
+ self.assertGreaterEqual(pwr, pwr_min)
+ self.assertLessEqual(pwr, pwr_max)
+
+ self.assertEqual(settings["SA:ACQ:AVG"], 1)
+
+ rbw = settings["SA:ACQ:RBW"]
+ self.assertGreaterEqual(rbw, rbw_min)
+ self.assertLessEqual(rbw, rbw_max)
+
+ f_center = settings["SA:FREQ:CENT"]
+ f_span = settings["SA:FREQ:SPAN"]
+ f_start = settings["SA:FREQ:START"]
+ f_stop = settings["SA:FREQ:STOP"]
+ self.assertGreaterEqual(f_start, f_min)
+ self.assertLessEqual(f_start, f_stop)
+ self.assertLessEqual(f_stop, f_max)
+ f_granularity = (f_max - f_min) / points_max
+ self.assertTrue(abs(f_stop - f_start - f_span) < f_granularity)
+ self.assertTrue(abs((f_start + f_stop) / 2 - f_center) < f_granularity)
+
+ self.assertFalse(settings["SA:TRACK:EN"])
+ pwr = settings["SA:TRACK:LVL"]
+ self.assertGreaterEqual(pwr, pwr_min)
+ self.assertLessEqual(pwr, pwr_max)
+
+ pwr = settings["SA:TRACK:NORM:LVL"]
+ self.assertGreaterEqual(pwr, pwr_min)
+ self.assertLessEqual(pwr, pwr_max)
+
+ self.assertGreaterEqual(settings["SA:TRACK:P"], 1)
+
+ ifbw = settings["VNA:ACQ:IFBW"]
+ self.assertGreaterEqual(ifbw, ifbw_min)
+ self.assertLessEqual(ifbw, ifbw_max)
+
+ points = settings["VNA:ACQ:POINTS"]
+ self.assertGreaterEqual(points, 1)
+ self.assertLessEqual(points, points_max)
+
+ # TODO-check: In standard SCPI, the instrument does not source
+ # power from its ports after *RST. Automation program enables
+ # the output only after completing its setup.
+ #self.assertFalse(settings["VNA:ACQ:RUN"]) # can't source pwr
+ self.assertEqual(settings["VNA:DEEMB:NUM"], 0)
+
+ f_center = settings["VNA:FREQ:CENT"]
+ f_span = settings["VNA:FREQ:SPAN"]
+ f_start = settings["VNA:FREQ:START"]
+ f_stop = settings["VNA:FREQ:STOP"]
+ self.assertGreaterEqual(f_start, f_min)
+ self.assertLessEqual(f_start, f_stop)
+ self.assertLessEqual(f_stop, f_max)
+ self.assertTrue(abs(f_stop - f_start - f_span) < f_granularity)
+ self.assertTrue(abs((f_start + f_stop) / 2 - f_center) < f_granularity)
+
+ pwr_start = settings["VNA:POW:START"]
+ pwr_stop = settings["VNA:POW:STOP"]
+ self.assertGreaterEqual(pwr_start, pwr_min)
+ self.assertLess(pwr_start, pwr_stop)
+ self.assertLessEqual(pwr_stop, pwr_max)
+
+ f = settings["VNA:STIM:FREQ"]
+ self.assertGreaterEqual(f, f_min)
+ self.assertLessEqual(f, f_max)
+
+ pwr = settings["VNA:STIM:LVL"]
+ self.assertGreaterEqual(pwr, pwr_min)
+ self.assertLessEqual(pwr, pwr_max)
+
+ self.assertEqual(settings["VNA:SWEEP"], "FREQUENCY")
+
+ def test_rst_basic(self):
+ self.vna.cmd("*RST")
+ settings = self.query_settings()
+ self.validate_settings(settings)
+
+ def test_rst_hard(self):
+ self.vna.cmd("*RST")
+ settings1 = self.query_settings()
+ self.validate_settings(settings1)
+
+ # Get limits.
+ f_min = settings1["DEV:INF:LIM:MINF"]
+ f_max = settings1["DEV:INF:LIM:MAXF"]
+ f_1_3 = (2 * f_min + f_max) / 3
+ f_1_2 = (f_min + f_max) / 2
+ f_2_3 = (f_min + 2 * f_max) / 3
+ ifbw_min = settings1["DEV:INF:LIM:MINIFBW"]
+ ifbw_max = settings1["DEV:INF:LIM:MAXIFBW"]
+ ifbw_1_2 = (ifbw_min + ifbw_max) / 2
+ points_max = settings1["DEV:INF:LIM:MAXP"]
+ pwr_min = settings1["DEV:INF:LIM:MINPOW"]
+ pwr_max = settings1["DEV:INF:LIM:MAXPOW"]
+ pwr_1_3 = (2 * pwr_min + pwr_max) / 3
+ pwr_2_3 = (pwr_min + 2 * pwr_max) / 3
+ pwr_1_2 = (pwr_min + pwr_max) / 2
+ rbw_min = settings1["DEV:INF:LIM:MINRBW"]
+ rbw_max = settings1["DEV:INF:LIM:MAXRBW"]
+ rbw_1_2 = (rbw_max + rbw_max) / 2
+
+ # Change parameters.
+ self.vna.cmd("DEV:MODE SA")
+ self.vna.cmd("DEV:REF:IN AUTO")
+ self.vna.cmd("DEV:REF:OUT 10")
+ self.vna.cmd(f"GEN:FREQ {f_1_2}")
+ self.vna.cmd(f"GEN:LVL {pwr_1_2}")
+ self.vna.cmd("GEN:PORT 2")
+ self.vna.cmd("SA:ACQ:AVG 3")
+ self.vna.cmd("SA:ACQ:DET -PEAK")
+ self.vna.cmd(f"SA:ACQ:RBW {rbw_1_2}")
+ self.vna.cmd("SA:ACQ:SINGLE TRUE")
+ self.vna.cmd("SA:ACQ:WIND HANN")
+ self.vna.cmd(f"SA:FREQ:START {f_1_3} STOP {f_2_3}")
+ self.vna.cmd("SA:TRACK:EN TRUE")
+ self.vna.cmd(f"SA:TRACK:LVL {pwr_1_2}")
+ self.vna.cmd("SA:TRACK:NORM:EN TRUE")
+ self.vna.cmd(f"SA:TRACK:NORM:LVL {pwr_1_3}")
+ self.vna.cmd("SA:TRACK:OFF 1.0e+6;PORT 2")
+ self.vna.cmd("VNA:ACQ:AVG 10")
+ self.vna.cmd(f"VNA:ACQ:IFBW {ifbw_1_2}")
+ self.vna.cmd(f"VNA:ACQ:POINTS 100")
+ self.vna.cmd("VNA:ACQ:SINGLE TRUE")
+ self.vna.cmd(f"VNA:FREQ:START {f_1_2};STOP {f_max}")
+ self.vna.cmd(f"VNA:POW:START {pwr_1_3};STOP {pwr_2_3}")
+ self.vna.cmd(f"VNA:STIM:FREQ {f_1_3}")
+ self.vna.cmd(f"VNA:STIM:LVL {pwr_min}")
+ self.vna.cmd("VNA:SWEEP POWER")
+
+ # Reset and verify all settings revert.
+ self.vna.cmd("*RST")
+
+ settings2 = self.query_settings()
+ for key, value in settings1.items():
+ self.assertEqual(value, settings2[key])
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestSASweep.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestSASweep.py
new file mode 100644
index 0000000..79303fb
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestSASweep.py
@@ -0,0 +1,98 @@
+from tests.TestBase import TestBase
+import time
+
+class TestSASweep(TestBase):
+ def waitSweepTimeout(self, timeout = 1):
+ self.assertEqual(self.vna.query(":SA:ACQ:FIN?"), "FALSE")
+ stoptime = time.time() + timeout
+ while self.vna.query(":SA:ACQ:FIN?") == "FALSE":
+ if time.time() > stoptime:
+ raise AssertionError("Sweep timed out")
+
+ def assertTrace_dB(self, trace, dB_nominal, dB_deviation):
+ for S in trace:
+ self.assertLessEqual(S[1], dB_nominal + dB_deviation)
+ self.assertGreaterEqual(S[1], dB_nominal - dB_deviation)
+
+ def test_sweep_frequency(self):
+ self.vna.cmd(":DEV:MODE SA")
+ self.vna.cmd(":SA:FREQ:CENT 2000000000")
+ self.vna.cmd(":SA:FREQ:SPAN 200000")
+
+ self.assertEqual(float(self.vna.query(":SA:FREQ:START?")), 1999900000)
+ self.assertEqual(float(self.vna.query(":SA:FREQ:STOP?")), 2000100000)
+
+ self.vna.cmd(":SA:ACQ:RBW 10000")
+ self.waitSweepTimeout(10)
+
+ port1 = self.vna.parse_SA_trace_data(self.vna.query(":SA:TRACE:DATA? PORT1"))
+ port2 = self.vna.parse_SA_trace_data(self.vna.query(":SA:TRACE:DATA? PORT2"))
+
+ self.assertEqual(port1[0][0], 1999900000)
+ self.assertEqual(port1[-1][0], 2000100000)
+ self.assertEqual(port2[0][0], 1999900000)
+ self.assertEqual(port2[-1][0], 2000100000)
+
+ # No signal present, signal level should be very low
+ self.assertTrace_dB(port1, -140, 60)
+ self.assertTrace_dB(port2, -140, 60)
+
+ def test_sweep_zerospan(self):
+ self.vna.cmd(":DEV:MODE SA")
+ self.vna.cmd(":SA:FREQ:CENT 2000000000")
+ self.vna.cmd(":SA:FREQ:SPAN 0")
+
+ self.assertEqual(float(self.vna.query(":SA:FREQ:START?")), 2000000000)
+ self.assertEqual(float(self.vna.query(":SA:FREQ:STOP?")), 2000000000)
+
+ self.vna.cmd(":SA:ACQ:RBW 10000")
+ self.waitSweepTimeout(10)
+
+ port1 = self.vna.parse_SA_trace_data(self.vna.query(":SA:TRACE:DATA? PORT1"))
+ port2 = self.vna.parse_SA_trace_data(self.vna.query(":SA:TRACE:DATA? PORT2"))
+
+ self.assertEqual(port1[0][0], 0.0)
+ self.assertGreater(port1[-1][0], 4)
+ self.assertLess(port1[-1][0], 8)
+ self.assertEqual(port2[0][0], 0.0)
+ self.assertGreater(port2[-1][0], 4)
+ self.assertLess(port2[-1][0], 8)
+
+ # No signal present, signal level should be very low
+ self.assertTrace_dB(port1, -140, 60)
+ self.assertTrace_dB(port2, -140, 60)
+
+ def test_tracking_generator(self):
+ self.vna.cmd(":DEV:MODE SA")
+ self.vna.cmd(":SA:FREQ:CENT 1930000000")
+ self.vna.cmd(":SA:FREQ:SPAN 200000")
+ self.vna.cmd(":SA:ACQ:RBW 10000")
+ self.vna.cmd(":SA:TRACK:PORT 1")
+ self.assertEqual(self.vna.query(":SA:TRACK:PORT?"), "1")
+ self.vna.cmd(":SA:TRACK:LVL -20")
+ self.vna.cmd(":SA:TRACK:OFFSET 0")
+ self.vna.cmd(":SA:TRACK:EN TRUE")
+ self.waitSweepTimeout(10)
+
+ port1 = self.vna.parse_SA_trace_data(self.vna.query(":SA:TRACE:DATA? PORT1"))
+
+ level = port1[0][1]
+ self.assertGreater(level, -30)
+ self.assertLess(level, -10)
+ # check tracking generator signal
+ self.assertTrace_dB(port1, level, 5)
+
+ # Enable normalization
+ self.vna.cmd(":SA:TRACK:NORM:LVL -10")
+ self.vna.cmd(":SA:TRACK:NORM:EN TRUE")
+ # wait for normalization to finish
+ self.waitSweepTimeout(10)
+
+ # trigger the next sweep
+ self.vna.cmd(":SA:ACQ:SINGLE TRUE")
+ self.waitSweepTimeout(10)
+
+ # Reported level on port1 should match normalization very closely now
+ port1 = self.vna.parse_SA_trace_data(self.vna.query(":SA:TRACE:DATA? PORT1"))
+ self.assertTrace_dB(port1, -10, 1)
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestStatusRegisters.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestStatusRegisters.py
new file mode 100644
index 0000000..c4e3ae4
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestStatusRegisters.py
@@ -0,0 +1,56 @@
+import re
+from tests.TestBase import TestBase
+
+
+class TestStatusRegisters(TestBase):
+ def query_stb(self):
+ resp = self.vna.query("*STB?")
+ self.assertTrue(re.match(r"^\d+$", resp))
+ value = int(resp)
+ self.assertTrue(value >= 0 and value <= 255)
+ return value
+
+ def test_invalid_command(self):
+ status = self.vna.get_status()
+ self.assertEqual(status, 0)
+ self.vna.default_check_cmds = False
+ self.vna.cmd("INVALID:COMMAND")
+ status = self.vna.get_status()
+ self.assertEqual(status & 0x3C, 0x20)
+ status = self.vna.get_status()
+ self.assertEqual(status, 0)
+
+ def test_invalid_query(self):
+ status = self.vna.get_status()
+ self.assertEqual(status, 0)
+ self.vna.default_check_cmds = False
+ self.vna.cmd("INVALID:QUERY?") # send as cmd to avoid timeout
+ status = self.vna.get_status()
+ self.assertTrue(status & 0x20) # expect CME
+ status = self.vna.get_status()
+ self.assertEqual(status, 0)
+
+ def test_stb(self):
+ self.vna.default_check_cmds = False
+ self.vna.cmd("*SRE 0")
+ status = self.vna.get_status()
+ if status & 0x20:
+ self.skipTest("Skipping test: *SRE, *SRE?, *STB? not implemented")
+ self.vna.cmd("*RST")
+ self.vna.cmd("VNA:ACQ:SINGLE TRUE")
+ self.vna.cmd("*WAI")
+ status = self.vna.get_status()
+ self.assertEqual(status, 0)
+ self.vna.cmd("OPC") # should set OPC
+ self.vna.cmd(f"*ESE {0x21:d}") # mask is CME|OPC
+ self.assertEqual(self.query_stb() & 0x60, 0x20) # expect !MSS, ESB
+ self.assertEqual(self.query_stb() & 0x60, 0x20) # shouldn't clear
+ self.vna.cmd(f"*SRE {0x20:d}") # unmask ESB
+ self.assertEqual(self.query_stb() & 0x60, 0x60) # expect MSS, ESB
+ self.vna.cmd(f"*ESE {0x20:d}") # mask is CME only
+ self.assertEqual(self.query_stb() & 0x60, 0) # expect !MSS, !ESB
+ self.vna.cmd("INVALID:COMMAND") # should set CME
+ self.assertEqual(self.query_stb() & 0x60, 0x60) # expect MSS, ESB
+ status = self.get_status()
+ self.assertEqual(status, 0x21) # expect CMD|OPC, clears
+ self.assertEqual(self.query_stb() & 0x60, 0) # expect !MSS, !ESB
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestSync.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestSync.py
new file mode 100644
index 0000000..4b9bf19
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestSync.py
@@ -0,0 +1,52 @@
+from tests.TestBase import TestBase
+import time
+
+
+class TestSync(TestBase):
+ def test_wai(self):
+ self.vna.cmd("*RST")
+ self.vna.cmd("VNA:ACQ:SINGLE TRUE")
+ self.assertEqual(self.vna.query(":VNA:ACQ:FIN?"), "FALSE")
+ self.vna.cmd("*WAI", timeout=3)
+ self.assertEqual(self.vna.query(":VNA:ACQ:FIN?"), "TRUE")
+
+ def test_opc_query(self):
+ self.vna.cmd("*RST")
+ self.vna.cmd("VNA:ACQ:SINGLE TRUE")
+ self.assertEqual(self.vna.query(":VNA:ACQ:FIN?"), "FALSE")
+ resp = self.vna.query("*OPC?", timeout=3)
+ self.assertEqual(resp, "1")
+ self.assertEqual(self.vna.query(":VNA:ACQ:FIN?"), "TRUE")
+
+ def test_opc_poll(self):
+ self.vna.cmd("*RST")
+ self.vna.cmd("VNA:ACQ:SINGLE TRUE")
+ self.vna.cmd("*OPC")
+ self.assertEqual(self.vna.query(":VNA:ACQ:FIN?"), "FALSE")
+ time_limit = time.time() + 4
+ while True:
+ status = self.vna.get_status()
+ if status & 0x01:
+ break
+ if time.time() >= time_limit:
+ raise Exception("Timeout waiting for OPC")
+ time.sleep(0.05)
+ self.assertEqual(self.vna.query(":VNA:ACQ:FIN?"), "TRUE")
+ self.assertEqual(self.vna.get_status(), 0)
+
+ def test_idle_waits(self):
+ '''
+ Test that *WAI and *OPC? don't hang when device is idle. Test
+ that *OPC query sets the OPC status bit immediately.
+ '''
+ self.vna.cmd("*RST")
+ self.vna.cmd("VNA:ACQ:SINGLE TRUE")
+ self.vna.cmd("*WAI", timeout=3)
+ self.assertEqual(self.vna.get_status(), 0)
+ self.assertEqual(self.vna.query(":VNA:ACQ:FIN?"), "TRUE")
+ self.vna.cmd("*WAI")
+ resp = self.vna.query("*OPC?")
+ self.assertEqual(resp, "1")
+ self.assertEqual(self.vna.get_status(), 0)
+ self.assertEqual(self.vna.cmd("*OPC"), 0x01) # should return OPC
+ self.assertEqual(self.vna.get_status(), 0)
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestTemperature.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestTemperature.py
new file mode 100644
index 0000000..28f5dce
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestTemperature.py
@@ -0,0 +1,9 @@
+from tests.TestBase import TestBase
+
+class TestConnect(TestBase):
+ def test_temperature(self):
+ res = self.vna.query(":DEV:INF:TEMP?")
+ self.assertEqual(len(res.split("/")), 3)
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestUpdate.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestUpdate.py
new file mode 100644
index 0000000..8e13f40
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestUpdate.py
@@ -0,0 +1,18 @@
+from tests.TestBase import TestBase
+import time
+import subprocess
+
+class TestUpdate(TestBase):
+ def test_Update(self):
+ # first update: actually update to the firmware version we want to test
+ self.vna.cmd("DEV:UPDATE ../../combined.vnafw", timeout=60)
+ # second update: check that we still have a working firmware update with this version
+ self.vna.cmd("DEV:UPDATE ../../combined.vnafw", timeout=60)
+
+ reported = self.vna.query("DEV:INF:FWREVISION?")
+ major = subprocess.check_output("grep -oP '(?<=FW_MAJOR=)[0-9]+' ../VNA_embedded/Makefile", shell=True).strip()
+ minor = subprocess.check_output("grep -oP '(?<=FW_MINOR=)[0-9]+' ../VNA_embedded/Makefile", shell=True).strip()
+ patch = subprocess.check_output("grep -oP '(?<=FW_PATCH=)[0-9]+' ../VNA_embedded/Makefile", shell=True).strip()
+ expected = major.decode("utf-8") + "." + minor.decode("utf-8") + "." + patch.decode("utf-8")
+ self.assertEqual(reported, expected)
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestVNASweep.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestVNASweep.py
new file mode 100644
index 0000000..3e0a87d
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/TestVNASweep.py
@@ -0,0 +1,85 @@
+from tests.TestBase import TestBase
+import time
+
+class TestVNASweep(TestBase):
+ def waitSweepTimeout(self, timeout = 1):
+ self.assertEqual(self.vna.query(":VNA:ACQ:FIN?"), "FALSE")
+ self.vna.cmd("*WAI", timeout=timeout)
+ self.assertEqual(self.vna.query(":VNA:ACQ:FIN?"), "TRUE")
+
+ def test_sweep_frequency(self):
+ self.vna.cmd(":DEV:MODE VNA")
+ self.vna.cmd(":VNA:SWEEP FREQUENCY")
+ self.vna.cmd(":VNA:STIM:LVL -10")
+ self.vna.cmd(":VNA:ACQ:IFBW 10000")
+ self.vna.cmd(":VNA:ACQ:AVG 1")
+ self.vna.cmd(":VNA:ACQ:POINTS 501")
+ self.vna.cmd(":VNA:FREQuency:START 1000000")
+ self.vna.cmd(":VNA:FREQuency:STOP 6000000000")
+ self.waitSweepTimeout(2)
+
+ S11 = self.vna.parse_VNA_trace_data(self.vna.query(":VNA:TRACE:DATA? S11"))
+ self.assertEqual(S11[0][0], 1000000)
+ self.assertEqual(S11[-1][0], 6000000000)
+
+ def test_sweep_zerospan(self):
+ self.vna.cmd(":DEV:MODE VNA")
+ self.vna.cmd(":VNA:SWEEP FREQUENCY")
+ self.vna.cmd(":VNA:STIM:LVL -10")
+ self.vna.cmd(":VNA:ACQ:IFBW 10000")
+ self.vna.cmd(":VNA:ACQ:AVG 1")
+ self.vna.cmd(":VNA:ACQ:POINTS 501")
+ self.vna.cmd(":VNA:FREQuency:START 500000000")
+ self.vna.cmd(":VNA:FREQuency:STOP 1500000000")
+ self.vna.cmd(":VNA:FREQuency:ZERO 1500000000")
+ self.waitSweepTimeout(2)
+
+ S11 = self.vna.parse_VNA_trace_data(self.vna.query(":VNA:TRACE:DATA? S11"))
+ self.assertEqual(S11[0][0], 0.0)
+ # Sweep should take about 0.125 seconds
+ self.assertGreater(S11[-1][0], 0.1)
+ self.assertLess(S11[-1][0], 0.5)
+
+ def test_sweep_power(self):
+ self.vna.cmd(":DEV:MODE VNA")
+ self.vna.cmd(":VNA:SWEEP POWER")
+ self.vna.cmd(":VNA:STIM:LVL -10")
+ self.vna.cmd(":VNA:ACQ:IFBW 10000")
+ self.vna.cmd(":VNA:ACQ:AVG 1")
+ self.vna.cmd(":VNA:ACQ:POINTS 501")
+ self.vna.cmd(":VNA:POWER:START -30")
+ self.vna.cmd(":VNA:POWER:STOP -10")
+ self.waitSweepTimeout(2)
+
+ S11 = self.vna.parse_VNA_trace_data(self.vna.query(":VNA:TRACE:DATA? S11"))
+ self.assertEqual(S11[0][0], -30)
+ self.assertEqual(S11[-1][0], -10)
+
+ def test_fast_single_sweeps(self):
+ self.vna.cmd(":DEV:MODE VNA")
+ self.vna.cmd(":VNA:SWEEP FREQUENCY")
+ self.vna.cmd(":VNA:STIM:LVL -10")
+ self.vna.cmd(":VNA:ACQ:IFBW 50000")
+ self.vna.cmd(":VNA:ACQ:AVG 1")
+ self.vna.cmd(":VNA:ACQ:POINTS 501")
+ self.vna.cmd(":VNA:FREQuency:START 1000000")
+ self.vna.cmd(":VNA:FREQuency:STOP 6000000000")
+
+ for i in range(10):
+ # Change something irrelevant (to force reconfiguration of device)
+ self.vna.cmd(":VNA:FREQuency:START "+str(1000000+i))
+ self.waitSweepTimeout(2)
+
+ def test_segmented_sweep(self):
+ self.vna.cmd(":DEV:MODE VNA")
+ self.vna.cmd(":VNA:SWEEP FREQUENCY")
+ self.vna.cmd(":VNA:STIM:LVL -10")
+ self.vna.cmd(":VNA:ACQ:IFBW 50000")
+ self.vna.cmd(":VNA:ACQ:AVG 1")
+ self.vna.cmd(":VNA:ACQ:POINTS 10000")
+ self.vna.cmd(":VNA:FREQuency:START 1000000")
+ self.vna.cmd(":VNA:FREQuency:STOP 6000000000")
+ self.waitSweepTimeout(10)
+
+ S11 = self.vna.parse_VNA_trace_data(self.vna.query(":VNA:TRACE:DATA? S11"))
+ self.assertEqual(len(S11), 10000)
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/__init__.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/definitions.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/definitions.py
new file mode 100644
index 0000000..1684691
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/definitions.py
@@ -0,0 +1 @@
+GUI_PATH = "../PC_Application/LibreVNA-GUI/LibreVNA-GUI"
\ No newline at end of file
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/libreVNA.py b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/libreVNA.py
new file mode 100644
index 0000000..d17ab80
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/Integrationtests/tests/libreVNA.py
@@ -0,0 +1 @@
+../../../Documentation/UserManual/SCPI_Examples/libreVNA.py
\ No newline at end of file
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/.gitignore b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/.gitignore
new file mode 100644
index 0000000..2d49f02
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/.gitignore
@@ -0,0 +1,87 @@
+# This file is used to ignore files which are generated
+# ----------------------------------------------------------------------------
+
+*~
+*.autosave
+*.a
+*.core
+*.moc
+*.o
+*.obj
+*.orig
+*.rej
+*.so
+*.so.*
+*_pch.h.cpp
+*_resource.rc
+*.qm
+.#*
+*.*#
+core
+!core/
+tags
+.DS_Store
+.directory
+*.debug
+Makefile*
+*.prl
+*.app
+moc_*.cpp
+moc_*.h
+ui_*.h
+qrc_*.cpp
+Thumbs.db
+*.res
+*.rc
+/.qmake.cache
+/.qmake.stash
+
+# qtcreator generated files
+*.pro.user*
+
+# xemacs temporary files
+*.flc
+
+# Vim temporary files
+.*.swp
+
+# Visual Studio generated files
+*.ib_pdb_index
+*.idb
+*.ilk
+*.pdb
+*.sln
+*.suo
+*.vcproj
+*vcproj.*.*.user
+*.ncb
+*.sdf
+*.opensdf
+*.vcxproj
+*vcxproj.*
+
+# MinGW generated files
+*.Debug
+*.Release
+
+# Python byte code
+*.pyc
+
+# Binaries
+# --------
+*.dll
+*.exe
+Application
+/build-*
+/LibreVNA-GUI/LibreVNA-GUI
+/LibreVNA-Test/LibreVNA-Test
+/LibreVNA-GUI/users*appdatalocaltemp*
+/LibreVNA/build
+LibreVNA-GUI/build
+
+# qmake.stash
+LibreVNA-GUI/.qmake.stash
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/51-vna.rules b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/51-vna.rules
new file mode 100644
index 0000000..4661e80
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/51-vna.rules
@@ -0,0 +1,3 @@
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="564e", MODE:="0666"
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="4121", MODE:="0666"
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="1209", ATTRS{idProduct}=="4121", MODE:="0666"
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardLineEditDialog.ui b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardLineEditDialog.ui
new file mode 100644
index 0000000..92681e7
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardLineEditDialog.ui
@@ -0,0 +1,147 @@
+
+
+ CalStandardLineEditDialog
+
+
+
+ 0
+ 0
+ 383
+ 202
+
+
+
+ Edit Line Standard
+
+
+ true
+
+
+ -
+
+
-
+
+
+ Name:
+
+
+
+ -
+
+
+
+
+ -
+
+
-
+
+
+ Z0:
+
+
+
+ -
+
+
+ false
+
+
+
+ -
+
+
+ Delay:
+
+
+
+ -
+
+
+ -
+
+
+ Minimum usable frequency:
+
+
+
+ -
+
+
+ false
+
+
+
+ -
+
+
+ Maximum usable frequency:
+
+
+
+ -
+
+
+ false
+
+
+
+
+
+ -
+
+
+ Qt::Horizontal
+
+
+ QDialogButtonBox::Cancel|QDialogButtonBox::Ok
+
+
+
+
+
+
+
+ SIUnitEdit
+ QLineEdit
+ CustomWidgets/siunitedit.h
+
+
+
+
+
+ buttonBox
+ accepted()
+ CalStandardLineEditDialog
+ accept()
+
+
+ 248
+ 254
+
+
+ 157
+ 274
+
+
+
+
+ buttonBox
+ rejected()
+ CalStandardLineEditDialog
+ reject()
+
+
+ 316
+ 260
+
+
+ 286
+ 274
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardLoadEditDialog.ui b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardLoadEditDialog.ui
new file mode 100644
index 0000000..6aebdf9
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardLoadEditDialog.ui
@@ -0,0 +1,254 @@
+
+
+ CalStandardLoadEditDialog
+
+
+
+ 0
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+ 344
+ 386
+
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+
+ Edit Load Standard
+
+
+ true
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-
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+
+ Coefficients
+
+
+ buttonGroup
+
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+ Measurement file
+
+
+ buttonGroup
+
+
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+
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-
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-
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+ Resistance:
+
+
+
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+
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+
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+ Z0:
+
+
+
+ -
+
+
+ true
+
+
+
+ -
+
+
+ Offset delay [ps]:
+
+
+
+ -
+
+
+ -
+
+
+ Offset loss [GΩ/s]:
+
+
+
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+
+
+ -
+
+
+ Parallel C:
+
+
+
+ -
+
+
+ -
+
+
+ Series L:
+
+
+
+ -
+
+
+
+
+ -
+
+
+ Load Parameter Model
+
+
+
-
+
+
+ Series L first
+
+
+ buttonGroup_2
+
+
+
+ -
+
+
+ Shunt C first
+
+
+ buttonGroup_2
+
+
+
+
+
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+
+
+
+
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+ false
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+
+
+
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+
+
+
+
+
+
+ -
+
+
+ Qt::Horizontal
+
+
+ QDialogButtonBox::Cancel|QDialogButtonBox::Ok
+
+
+
+
+
+
+
+ SIUnitEdit
+ QLineEdit
+ CustomWidgets/siunitedit.h
+
+
+ TouchstoneImport
+ QWidget
+ CustomWidgets/touchstoneimport.h
+ 1
+
+
+
+
+
+ buttonBox
+ accepted()
+ CalStandardLoadEditDialog
+ accept()
+
+
+ 248
+ 254
+
+
+ 157
+ 274
+
+
+
+
+ buttonBox
+ rejected()
+ CalStandardLoadEditDialog
+ reject()
+
+
+ 316
+ 260
+
+
+ 286
+ 274
+
+
+
+
+
+
+
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardOpenEditDialog.ui b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardOpenEditDialog.ui
new file mode 100644
index 0000000..f3fdcfb
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardOpenEditDialog.ui
@@ -0,0 +1,230 @@
+
+
+ CalStandardOpenEditDialog
+
+
+
+ 0
+ 0
+ 358
+ 342
+
+
+
+ Edit Open Standard
+
+
+ true
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+
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+
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-
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+ Name:
+
+
+
+ -
+
+
+
+
+ -
+
+
-
+
+
+ Coefficients
+
+
+ buttonGroup
+
+
+
+ -
+
+
+ Measurement file
+
+
+ buttonGroup
+
+
+
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+
+
+ 0
+
+
+
+
-
+
+
+ Z0:
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+
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+ true
+
+
+
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+
+
+ Offset delay [ps]:
+
+
+
+ -
+
+
+ -
+
+
+ Offset loss [GΩ/s]:
+
+
+
+ -
+
+
+ -
+
+
+ C0 [10<sup>-15</sup>F]:
+
+
+
+ -
+
+
+ -
+
+
+ C1 [10<sup>-27</sup>F/Hz]:
+
+
+
+ -
+
+
+ -
+
+
+ C2 [10<sup>-36</sup>F/Hz<sup>2</sup>]:
+
+
+
+ -
+
+
+ -
+
+
+ <html><head/><body><p>C3 [10<span style=" vertical-align:super;">-45</span>F/Hz<span style=" vertical-align:super;">3</span>]:</p></body></html>
+
+
+
+ -
+
+
+
+
+
+
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+
+
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+ false
+
+
+ Update from file
+
+
+
+ -
+
+
+
+
+
+
+ -
+
+
+ Qt::Horizontal
+
+
+ QDialogButtonBox::Cancel|QDialogButtonBox::Ok
+
+
+
+
+
+
+
+ SIUnitEdit
+ QLineEdit
+ CustomWidgets/siunitedit.h
+
+
+ TouchstoneImport
+ QWidget
+ CustomWidgets/touchstoneimport.h
+ 1
+
+
+
+
+
+ buttonBox
+ accepted()
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+ accept()
+
+
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+ CalStandardOpenEditDialog
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diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardReflectEditDialog.ui b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardReflectEditDialog.ui
new file mode 100644
index 0000000..486ae8b
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardReflectEditDialog.ui
@@ -0,0 +1,106 @@
+
+
+ CalStandardReflectEditDialog
+
+
+
+ 0
+ 0
+ 291
+ 109
+
+
+
+ Edit Reflect Standard
+
+
+ true
+
+
+ -
+
+
-
+
+
+ Name:
+
+
+
+ -
+
+
+
+
+ -
+
+
-
+
+
+ Reflection type:
+
+
+
+ -
+
+
-
+
+ Open
+
+
+ -
+
+ Short
+
+
+
+
+
+
+ -
+
+
+ Qt::Horizontal
+
+
+ QDialogButtonBox::Cancel|QDialogButtonBox::Ok
+
+
+
+
+
+
+
+
+ buttonBox
+ accepted()
+ CalStandardReflectEditDialog
+ accept()
+
+
+ 248
+ 254
+
+
+ 157
+ 274
+
+
+
+
+ buttonBox
+ rejected()
+ CalStandardReflectEditDialog
+ reject()
+
+
+ 316
+ 260
+
+
+ 286
+ 274
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardShortEditDialog.ui b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardShortEditDialog.ui
new file mode 100644
index 0000000..594cb06
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardShortEditDialog.ui
@@ -0,0 +1,230 @@
+
+
+ CalStandardShortEditDialog
+
+
+
+ 0
+ 0
+ 358
+ 342
+
+
+
+ Edit Short Standard
+
+
+ true
+
+
+ -
+
+
-
+
+
+ Name:
+
+
+
+ -
+
+
+
+
+ -
+
+
-
+
+
+ Coefficients
+
+
+ buttonGroup
+
+
+
+ -
+
+
+ Measurement file
+
+
+ buttonGroup
+
+
+
+
+
+ -
+
+
+ 0
+
+
+
+
-
+
+
+ Z0:
+
+
+
+ -
+
+
+ true
+
+
+
+ -
+
+
+ Offset delay [ps]:
+
+
+
+ -
+
+
+ -
+
+
+ Offset loss [GΩ/s]:
+
+
+
+ -
+
+
+ -
+
+
+ <html><head/><body><p>L0 [10<span style=" vertical-align:super;">-12</span>H]:</p></body></html>
+
+
+
+ -
+
+
+ -
+
+
+ <html><head/><body><p>L1 [10<span style=" vertical-align:super;">-24</span>H/Hz]:</p></body></html>
+
+
+
+ -
+
+
+ -
+
+
+ <html><head/><body><p>L2 [10<span style=" vertical-align:super;">-33</span>H/Hz<span style=" vertical-align:super;">2</span>]:</p></body></html>
+
+
+
+ -
+
+
+ -
+
+
+ <html><head/><body><p>L3 [10<span style=" vertical-align:super;">-42</span>H/Hz<span style=" vertical-align:super;">3</span>]:</p></body></html>
+
+
+
+ -
+
+
+
+
+
+
+ -
+
+
+
+
+
+
+ -
+
+
+ false
+
+
+ Update from file
+
+
+
+ -
+
+
+
+
+
+
+ -
+
+
+ Qt::Horizontal
+
+
+ QDialogButtonBox::Cancel|QDialogButtonBox::Ok
+
+
+
+
+
+
+
+ SIUnitEdit
+ QLineEdit
+ CustomWidgets/siunitedit.h
+
+
+ TouchstoneImport
+ QWidget
+ CustomWidgets/touchstoneimport.h
+ 1
+
+
+
+
+
+ buttonBox
+ accepted()
+ CalStandardShortEditDialog
+ accept()
+
+
+ 248
+ 254
+
+
+ 157
+ 274
+
+
+
+
+ buttonBox
+ rejected()
+ CalStandardShortEditDialog
+ reject()
+
+
+ 316
+ 260
+
+
+ 286
+ 274
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardThroughEditDialog.ui b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardThroughEditDialog.ui
new file mode 100644
index 0000000..4746bd0
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/CalStandardThroughEditDialog.ui
@@ -0,0 +1,190 @@
+
+
+ CalStandardThroughEditDialog
+
+
+
+ 0
+ 0
+ 358
+ 342
+
+
+
+ Edit Through Standard
+
+
+ true
+
+
+ -
+
+
-
+
+
+ Name:
+
+
+
+ -
+
+
+
+
+ -
+
+
-
+
+
+ Coefficients
+
+
+ buttonGroup
+
+
+
+ -
+
+
+ Measurement file
+
+
+ buttonGroup
+
+
+
+
+
+ -
+
+
+ 0
+
+
+
+
-
+
+
+ Z0:
+
+
+
+ -
+
+
+ true
+
+
+
+ -
+
+
+ Delay [ps]:
+
+
+
+ -
+
+
+ -
+
+
+ Loss [GΩ/s]:
+
+
+
+ -
+
+
+
+
+
+
+ -
+
+
+
+
+
+
+ -
+
+
+ false
+
+
+ Update from file
+
+
+
+ -
+
+
+
+
+
+
+ -
+
+
+ Qt::Horizontal
+
+
+ QDialogButtonBox::Cancel|QDialogButtonBox::Ok
+
+
+
+
+
+
+
+ SIUnitEdit
+ QLineEdit
+ CustomWidgets/siunitedit.h
+
+
+ TouchstoneImport
+ QWidget
+ CustomWidgets/touchstoneimport.h
+ 1
+
+
+
+
+
+ buttonBox
+ accepted()
+ CalStandardThroughEditDialog
+ accept()
+
+
+ 248
+ 254
+
+
+ 157
+ 274
+
+
+
+
+ buttonBox
+ rejected()
+ CalStandardThroughEditDialog
+ reject()
+
+
+ 316
+ 260
+
+
+ 286
+ 274
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/caldevice.cpp b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/caldevice.cpp
new file mode 100644
index 0000000..229a295
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/caldevice.cpp
@@ -0,0 +1,1017 @@
+#include "caldevice.h"
+
+#include "Util/util.h"
+#include "ui_factoryUpdateDialog.h"
+#include "Util/QMicroz/qmicroz.h"
+#include "CustomWidgets/informationbox.h"
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+using namespace std;
+
+static const QStringList factoryProblemSerials = {
+ "5mNkR0s+NzMA", "5mNkR0s2DTcA", "5mNkR0s2gzcA", "5mNkR0s2HTMA", "5mNkR0s2STMA",
+ "5mNkR0s3pzcA", "5mNkR0s8ijcA", "5mNkR0s9jjMA", "5mNkR0sGdCsA", "5mNkR0slqjEA",
+ "5mNkR0srVDMA", "5mNkR0sssjcA", "5mNkR0suHDcA", "5mNkR0svOTcA", "5mNkR0svrzcA",
+ "5mNkR0swkTcA", "5mNkR0s_JzMA", "5mNkR0t+HTUA", "5mNkR0t+JzcA", "5mNkR0t+mjUA",
+ "5mNkR0t0IzIA", "5mNkR0t0TjAA", "5mNkR0t1bTAA", "5mNkR0t1cjUA", "5mNkR0t1HDAA",
+ "5mNkR0t2oTIA", "5mNkR0t2rTAA", "5mNkR0t2uyoA", "5mNkR0t3HC0A", "5mNkR0t3HjIA",
+ "5mNkR0t3MS0A", "5mNkR0t3vC0A", "5mNkR0t3VzUA", "5mNkR0t4aS0A", "5mNkR0t4nDUA",
+ "5mNkR0t5fDcA", "5mNkR0t6cDcA", "5mNkR0t9kzcA", "5mNkR0t9OTcA", "5mNkR0t9UTUA",
+ "5mNkR0tbPTUA", "5mNkR0tbqTUA", "5mNkR0tcHzUA", "5mNkR0tctDUA", "5mNkR0tcwjcA",
+ "5mNkR0tdrDUA", "5mNkR0telDUA", "5mNkR0tgaTkA", "5mNkR0tgRzcA", "5mNkR0tgWTkA",
+ "5mNkR0tikTUA", "5mNkR0tivDcA", "5mNkR0tIXS8A", "5mNkR0tLOTkA", "5mNkR0tqtTkA",
+ "5mNkR0tshS0A", "5mNkR0tsnioA", "5mNkR0tSOzQA", "5mNkR0tSqjQA", "5mNkR0tThjUA",
+ "5mNkR0tTxTUA", "5mNkR0tuVS0A", "5mNkR0tvGC0A", "5mNkR0tvYyoA", "5mNkR0tWljIA",
+ "5mNkR0tXMDIA", "5mNkR0t_UzUA", "5mNkR0uBiC0A", "5mNkR0uBNS0A", "5mNkR0uCPTYA",
+ "5mNkR0uCrTYA", "5mNkR0uDgDIA", "5mNkR0uFjTUA", "5mNkR0uFTjUA", "5mNkR0ugbCoA",
+ "5mNkR0uGIy0A", "5mNkR0uGkzUA", "5mNkR0uGpi0A", "5mNkR0uGRC0A", "5mNkR0uGrjUA",
+ "5mNkR0uGSzUA", "5mNkR0uGVCoA", "5mNkR0uHIyoA", "5mNkR0uHJjUA", "5mNkR0uHmC0A",
+ "5mNkR0uHpzUA", "5mNkR0uHTzUA", "5mNkR0uIdzUA", "5mNkR0uIPDYA", "5mNkR0uIpy0A",
+ "5mNkR0uIqioA", "5mNkR0uISioA", "5mNkR0uITjUA", "5mNkR0uIVi0A", "5mNkR0uJejYA",
+ "5mNkR0uJSDUA", "5mNkR0uKNDYA", "5mNkR0uKnzYA", "5mNkR0uLfTIA", "5mNkR0uLPjIA",
+ "5mNkR0uMbTIA", "5mNkR0uNpy0A", "5mNkR0uOTzAA", "5mNkR0uPhTAA", "5mOUNss0EysA",
+ "5mOUNss1XisA", "5mOUNsseICwA", "5mOUNssiNiwA", "5mOUNssnISwA", "5mOUNssnIyUA",
+ "5mOUNssrmCQA", "5mOUNssRmicA", "5mOUNssUlycA", "5mOUNssURCcA", "5mOUNssvjyQA",
+ "5mOUNssvNSUA", "5mOUNssVXSwA", "5mOUNsszOiQA", "5mOUNst9liQA", "5mOUNstAhSsA",
+ "5mOUNstFSysA", "5mOUNstFwCsA", "5mOUNstGmCUA", "5mOUNstHaCUA", "5mOUNstJkScA",
+ "5mOUNstOxysA", "5mOUNstsYiIA", "5mOUNstYRi0A", "5mOUNsuHqioA", "5mOUNsuhVSgA",
+ "5mOUNsuJLSoA", "5mOUNsuJrioA", "5mOUNsuVdCcA", "5mNkR0s1sjMA", "5mNkR0s3MjMA",
+ "5mNkR0s3XDcA", "5mNkR0slWjEA", "5mNkR0sxkC8A", "5mNkR0t+bzcA", "5mNkR0t1azIA",
+ "5mNkR0taKzUA", "5mNkR0tbbTcA", "5mNkR0tgGTkA", "5mNkR0thGDcA", "5mNkR0thiTcA",
+ "5mNkR0thKDcA", "5mNkR0tRYzQA", "5mNkR0tWBTIA", "5mNkR0uCpDYA", "5mNkR0uDXDYA",
+ "5mNkR0uJUDUA", "5mNkR0uLfjYA", "5mNkR0uMfjIA",
+};
+
+static QString getLocalDateTimeWithUtcOffset()
+{
+ QDateTime currentDateTime = QDateTime::currentDateTime();
+ int year = currentDateTime.date().year();
+ int month = currentDateTime.date().month();
+ int day = currentDateTime.date().day();
+ int hour = currentDateTime.time().hour();
+ int minute = currentDateTime.time().minute();
+ int second = currentDateTime.time().second();
+ int utcOffset = currentDateTime.offsetFromUtc() / 3600;
+ int utcOffsetMinute = (currentDateTime.offsetFromUtc() % 3600) / 60;
+ QString dateTimeString = QString("%1/%2/%3 %4:%5:%6 UTC%7%8:%9")
+ .arg(year, 4, 10, QChar('0'))
+ .arg(month, 2, 10, QChar('0'))
+ .arg(day, 2, 10, QChar('0'))
+ .arg(hour, 2, 10, QChar('0'))
+ .arg(minute, 2, 10, QChar('0'))
+ .arg(second, 2, 10, QChar('0'))
+ .arg(utcOffset > 0 ? "+" : "-") // Add a plus sign for positive offsets
+ .arg(qAbs(utcOffset), 2, 10, QChar('0'))
+ .arg(utcOffsetMinute, 2, 10, QChar('0'));
+ return dateTimeString;
+}
+
+CalDevice::CalDevice(QString serial) :
+ usb(new USBDevice(serial))
+{
+ loadThread = nullptr;
+ transferActive = false;
+
+ // Check device identification
+ auto id = usb->Query("*IDN?");
+ if(!id.startsWith("LibreCAL,")) {
+ delete usb;
+ throw std::runtime_error("Invalid response to *IDN?: "+id.toStdString());
+ }
+
+ firmware = usb->Query(":FIRMWARE?");
+ QList fw_version = firmware.split(".");
+ if (fw_version.size() == 3) {
+ int firmware_major = fw_version[0].toInt();
+ int firmware_minor = fw_version[1].toInt();
+ this->firmware_major_minor = firmware_major + ((float)firmware_minor/10.0f);
+ if(this->firmware_major_minor >= 0.2)
+ {
+ /* Set Date Time UTC */
+ QString LocalDateTimeWithUtcOffset = getLocalDateTimeWithUtcOffset();
+ QString ret = usb->Query(":DATE_TIME "+LocalDateTimeWithUtcOffset);
+ }
+ } else {
+ // fw_version invalid
+ this->firmware_major_minor = 0.0;
+ }
+ QString ports = usb->Query(":PORTS?");
+ bool okay;
+ numPorts = ports.toInt(&okay);
+ if(!okay) {
+ numPorts = 0;
+ }
+ connect(usb, &USBDevice::communicationFailure, this, &CalDevice::disconnected);
+ connect(this, &CalDevice::updateCoefficientsDone, this, [=]() {
+ transferActive = false;
+ });
+
+ // Check if this device was affected by the factory calibration problem
+ if(factoryProblemSerials.contains(usb->serial())) {
+ // it was, check if it still has bad factory coefficients
+
+ struct point {
+ uint16_t pointNum;
+ double freq;
+ };
+ std::array pointsToCheck = {{
+ {.pointNum = 451, .freq = 1.0},
+ {.pointNum = 551, .freq = 2.0},
+ {.pointNum = 651, .freq = 3.0},
+ }};
+
+ bool hasBadData = false;
+ for(auto point : pointsToCheck) {
+ // grab the point (just checking P12_THROUGH is enough
+ QString ret = usb->Query(":COEFF:GET? FACTORY P12_THROUGH "+QString::number(point.pointNum));
+ auto parts = ret.split(",");
+ if (parts.size() == 9 && parts[0].toDouble() == point.freq) {
+ // got the correct data, check S12 phase
+ auto S12 = std::complex(parts[3].toDouble(), parts[4].toDouble());
+ auto constexpr expectedS12Delay = 498e-12;
+ auto expectedS12Phase = expectedS12Delay * (point.freq * 1e9) * 2*M_PI;
+ auto phase = -arg(S12);
+ // unwrap to expected phase
+ while(phase < expectedS12Phase - M_PI) {
+ phase += 2*M_PI;
+ }
+ double S12Delay = phase / (2*M_PI) / (point.freq * 1e9);
+ qDebug() << "expected delay:" << expectedS12Delay << "factory calibration delay:" << S12Delay;
+ auto error = S12Delay - expectedS12Delay;
+ double tolerance = 17e-12;
+ if(abs(error) > tolerance) {
+ hasBadData = true;
+ break;
+ }
+// QList possibleErrors({0, -94.7e-12, 34.8e-12});
+// for(auto e : possibleErrors) {
+// if(abs(error-e) <= tolerance) {
+// // this is the error of the LibreCAL
+// if(e != 0) {
+// // still has the wrong coefficients
+// hasBadData = true;
+// }
+// break;
+// }
+// }
+ } else {
+ qWarning() << "Unexpected point frequency, factory calibration data is dubious";
+ }
+ if(hasBadData) {
+ break;
+ }
+ }
+ if(hasBadData) {
+ if(InformationBox::AskQuestion("Update Factory Coefficients?", "Your LibreCAL with serial number "+usb->serial()+" is affected by "
+ "a mistake in the factory calibration and its factory coefficients (specifically the phase of all "
+ "THRU standard definitions) are slightly wrong. The mistake has been corrected and updated factory "
+ "coefficients are available. Do you want to update the factory coefficients now?", false)) {
+ factoryUpdateDialog();
+ }
+ }
+ }
+}
+
+CalDevice::~CalDevice()
+{
+ delete usb;
+}
+
+QString CalDevice::StandardToString(CalDevice::Standard s)
+{
+ switch(s.type) {
+ case Standard::Type::Open: return "OPEN";
+ case Standard::Type::Short: return "SHORT";
+ case Standard::Type::Load: return "LOAD";
+ case Standard::Type::Through: return "THROUGH "+QString::number(s.throughDest);
+ case Standard::Type::None: return "NONE";
+ }
+ return "Invalid";
+}
+
+CalDevice::Standard CalDevice::StandardFromString(QString s)
+{
+ for(auto standard : availableStandards()) {
+ if(s == StandardToString(standard)) {
+ return standard;
+ }
+ }
+ return Standard(Standard::Type::None);
+}
+
+CalDevice::Standard CalDevice::getStandard(int port)
+{
+ auto query = ":PORT? "+QString::number(port);
+ auto response = usb->Query(query);
+ return StandardFromString(response);
+}
+
+bool CalDevice::setStandard(int port, CalDevice::Standard s)
+{
+ auto cmd = ":PORT "+QString::number(port)+" "+StandardToString(s);
+ return usb->Cmd(cmd);
+}
+
+std::vector CalDevice::availableStandards()
+{
+ return {Standard(Standard::Type::None), Standard(Standard::Type::Open), Standard(Standard::Type::Short), Standard(Standard::Type::Load), Standard(1), Standard(2), Standard(3), Standard(4)};
+}
+
+double CalDevice::getTemperature()
+{
+ QString tempString = usb->Query(":TEMP?");
+ bool okay;
+ double temp = tempString.toDouble(&okay);
+ if(!okay) {
+ temp = 0.0;
+ }
+ return temp;
+}
+
+bool CalDevice::stabilized()
+{
+ auto stable = usb->Query(":TEMPerature:STABLE?");
+ return stable == "TRUE";
+}
+
+double CalDevice::getHeaterPower()
+{
+ QString tempString = usb->Query(":HEATER:POWER?");
+ bool okay;
+ double power = tempString.toDouble(&okay);
+ if(!okay) {
+ power = 0.0;
+ }
+ return power;
+}
+
+QString CalDevice::serial()
+{
+ return usb->serial();
+}
+
+QString CalDevice::getFirmware() const
+{
+ return firmware;
+}
+
+unsigned int CalDevice::getNumPorts() const
+{
+ return numPorts;
+}
+
+bool CalDevice::enterBootloader()
+{
+ return usb->Cmd(":BOOTloader");
+}
+
+QString CalDevice::getDateTimeUTC()
+{
+ if(this->firmware_major_minor >= 0.2)
+ {
+ return usb->Query(":DATE_TIME?");
+ }else
+ {
+ return ""; // Not available
+ }
+}
+
+void CalDevice::loadCoefficientSets(QStringList names, QList ports, bool fast)
+{
+ coeffSets.clear();
+
+ if(ports.isEmpty()) {
+ for(unsigned int i=1;i<=getNumPorts();i++) {
+ ports.append(i);
+ }
+ } else {
+ // make sure we are sorted, otherwise the through coefficient naming is wrong
+ std::sort(ports.begin(), ports.end());
+ }
+
+ abortLoading = false;
+ transferActive = true;
+ if(fast && Util::firmwareEqualOrHigher(firmware, "0.2.1")) {
+ loadThread = new std::thread(&CalDevice::loadCoefficientSetsThreadFast, this, names, ports);
+ } else {
+ loadThread = new std::thread(&CalDevice::loadCoefficientSetsThreadSlow, this, names, ports);
+ }
+}
+
+void CalDevice::abortCoefficientLoading()
+{
+ if(loadThread) {
+ abortLoading = true;
+ loadThread->join();
+ loadThread = nullptr;
+ transferActive = false;
+ }
+}
+
+void CalDevice::saveCoefficientSets()
+{
+ if(!hasModifiedCoefficients()) {
+ // nothing to do, already done
+ emit updateCoefficientsDone(true);
+ } else {
+ transferActive = true;
+ new std::thread(&CalDevice::saveCoefficientSetsThread, this);
+ }
+}
+
+void CalDevice::loadCoefficientSetsThreadSlow(QStringList names, QList ports)
+{
+ QStringList coeffList = getCoefficientSetNames();
+ if(coeffList.empty()) {
+ // something went wrong
+ emit updateCoefficientsDone(false);
+ return;
+ }
+ if(names.size() > 0) {
+ // check if all the requested names are actually available
+ for(auto n : names) {
+ if(!coeffList.contains(n)) {
+ // this coefficient does not exist
+ emit updateCoefficientsDone(false);
+ return;
+ }
+ }
+ coeffList = names;
+ }
+ // get total number of coefficient points for accurate percentage calculation
+ unsigned long totalPoints = 0;
+ for(auto name : coeffList) {
+ for(int idx=0;idxQuery(":COEFF:NUM? "+name+" P"+QString::number(i)+"_OPEN").toInt();
+ totalPoints += usb->Query(":COEFF:NUM? "+name+" P"+QString::number(i)+"_SHORT").toInt();
+ totalPoints += usb->Query(":COEFF:NUM? "+name+" P"+QString::number(i)+"_LOAD").toInt();
+ for(int jdx=idx+1;jdxQuery(":COEFF:NUM? "+name+" P"+QString::number(i)+QString::number(j)+"_THROUGH").toInt();
+ }
+ }
+ }
+ unsigned long readPoints = 0;
+ int lastPercentage = 0;
+ for(auto name : coeffList) {
+ // create the coefficient set
+ CoefficientSet set;
+ set.name = name;
+ set.ports = numPorts;
+ // Read this coefficient set
+ for(int idx=0;idx CoefficientSet::Coefficient* {
+ int points = usb->Query(":COEFF:NUM? "+setName+" "+paramName).toInt();
+ CoefficientSet::Coefficient *c = new CoefficientSet::Coefficient();
+ if(paramName.endsWith("THROUGH")) {
+ c->t = Touchstone(2);
+ } else {
+ c->t = Touchstone(1);
+ }
+ for(int i=0;iQuery(":COEFF:GET? "+setName+" "+paramName+" "+QString::number(i));
+ QStringList values = pString.split(",");
+ Touchstone::Datapoint p;
+ p.frequency = values[0].toDouble() * 1e9;
+ for(int j = 0;j<(values.size()-1)/2;j++) {
+ double real = values[1+j*2].toDouble();
+ double imag = values[2+j*2].toDouble();
+ p.S.push_back(complex(real, imag));
+ }
+ if(p.S.size() == 4) {
+ // S21 and S12 are swapped in the touchstone file order (S21 goes first)
+ // but Touchstone::AddDatapoint expects S11 S12 S21 S22 order. Swap to match that
+ swap(p.S[1], p.S[2]);
+ }
+ c->t.AddDatapoint(p);
+ readPoints++;
+ int newPercentage = readPoints * 100 / totalPoints;
+ if(newPercentage != lastPercentage) {
+ lastPercentage = newPercentage;
+ emit updateCoefficientsPercent(newPercentage);
+ }
+ }
+ c->t.setFilename("LibreCAL/"+paramName);
+ return c;
+ };
+ set.opens[i] = (createCoefficient(name, "P"+QString::number(i)+"_OPEN"));
+ set.shorts[i] = (createCoefficient(name, "P"+QString::number(i)+"_SHORT"));
+ set.loads[i] = (createCoefficient(name, "P"+QString::number(i)+"_LOAD"));
+ for(int jdx=idx+1;jdx ports)
+{
+ QStringList coeffList = getCoefficientSetNames();
+ if(coeffList.empty()) {
+ // something went wrong
+ emit updateCoefficientsDone(false);
+ return;
+ }
+ if(names.size() > 0) {
+ // check if all the requested names are actually available
+ for(auto n : names) {
+ if(!coeffList.contains(n)) {
+ // this coefficient does not exist
+ emit updateCoefficientsDone(false);
+ return;
+ }
+ }
+ coeffList = names;
+ }
+
+ int total_coeffs = (ports.size() * 3 + ports.size() * (ports.size() - 1) / 2) * coeffList.size();
+ int read_coeffs = 0;
+
+ for(auto name : coeffList) {
+ // create the coefficient set
+ CoefficientSet set;
+ set.name = name;
+ set.ports = numPorts;
+
+ auto createCoefficient = [&](QString setName, QString paramName) -> CoefficientSet::Coefficient* {
+ CoefficientSet::Coefficient *c = new CoefficientSet::Coefficient();
+ // ask for the whole set at once
+ usb->flushReceived();
+ usb->send(":COEFF:GET? "+setName+" "+paramName);
+ // handle incoming lines
+ if(paramName.endsWith("THROUGH")) {
+ c->t = Touchstone(2);
+ } else {
+ c->t = Touchstone(1);
+ }
+ c->t.setFilename("LibreCAL/"+paramName);
+ while(true) {
+ QString line;
+ if(!usb->receive(&line)) {
+ // failed to receive something, abort
+ return nullptr;
+ }
+ if(line.startsWith("ERROR")) {
+ // something went wront
+ return nullptr;
+ }
+ // ignore start, comments and option line
+ if(line.startsWith("START") || line.startsWith("!") || line.startsWith("#")) {
+ // ignore
+ continue;
+ }
+ if(line.startsWith("END")) {
+ // got all data
+ return c;
+ }
+ // parse the values
+ try {
+ QStringList values = line.split(" ");
+ Touchstone::Datapoint p;
+ p.frequency = values[0].toDouble() * 1e9;
+ for(int j = 0;j<(values.size()-1)/2;j++) {
+ double real = values[1+j*2].toDouble();
+ double imag = values[2+j*2].toDouble();
+ p.S.push_back(complex(real, imag));
+ }
+ if(p.S.size() == 4) {
+ // S21 and S12 are swapped in the touchstone file order (S21 goes first)
+ // but Touchstone::AddDatapoint expects S11 S12 S21 S22 order. Swap to match that
+ swap(p.S[1], p.S[2]);
+ }
+ c->t.AddDatapoint(p);
+ } catch (...) {
+ return nullptr;
+ }
+ }
+ };
+
+ for(int idx=0;idxmodified) {
+ totalPoints += c.second->t.points();
+ }
+ }
+ for(auto c : set.shorts) {
+ if(c.second->modified) {
+ totalPoints += c.second->t.points();
+ }
+ }
+ for(auto c : set.loads) {
+ if(c.second->modified) {
+ totalPoints += c.second->t.points();
+ }
+ }
+ for(auto c : set.throughs) {
+ if(c.second->modified) {
+ totalPoints += c.second->t.points();
+ }
+ }
+ }
+ unsigned long transferredPoints = 0;
+ int lastPercentage = 0;
+ bool success = true;
+ for(auto set : coeffSets) {
+ auto createCoefficient = [&](QString setName, QString paramName, Touchstone &t, bool &modified) -> bool {
+ if(!modified) {
+ // no changes, nothing to do
+ return true;
+ }
+ int points = t.points();
+ if(points > 0) {
+ // create the file
+ if(!usb->Cmd(":COEFF:CREATE "+setName+" "+paramName)) {
+ return false;
+ }
+ for(int i=0;iCmd(cmd)) {
+ return false;
+ }
+ transferredPoints++;
+ int newPercentage = transferredPoints * 100 / totalPoints;
+ if(newPercentage != lastPercentage) {
+ lastPercentage = newPercentage;
+ emit updateCoefficientsPercent(newPercentage);
+ }
+ }
+ if(!usb->Cmd(":COEFF:FIN")) {
+ return false;
+ }
+ } else {
+ // no points, delete coefficient
+ if(!usb->Cmd(":COEFF:DEL "+setName+" "+paramName)) {
+ return false;
+ }
+ }
+ modified = false;
+ return true;
+ };
+ for(int i=1;i<=numPorts;i++) {
+ if(set.opens.count(i)) {
+ success &= createCoefficient(set.name, "P"+QString::number(i)+"_OPEN", set.opens[i]->t, set.opens[i]->modified);
+ if(!success) {
+ break;
+ }
+ }
+ if(set.shorts.count(i)) {
+ success &= createCoefficient(set.name, "P"+QString::number(i)+"_SHORT", set.shorts[i]->t, set.shorts[i]->modified);
+ if(!success) {
+ break;
+ }
+ }
+ if(set.loads.count(i)) {
+ success &= createCoefficient(set.name, "P"+QString::number(i)+"_LOAD", set.loads[i]->t, set.loads[i]->modified);
+ if(!success) {
+ break;
+ }
+ }
+ for(int j=i+1;j<=numPorts;j++) {
+ auto c = set.getThrough(i,j);
+ if(c) {
+ success &= createCoefficient(set.name, "P"+QString::number(i)+QString::number(j)+"_THROUGH", c->t, c->modified);
+ if(!success) {
+ break;
+ }
+ }
+ }
+ if(!success) {
+ break;
+ }
+ }
+ }
+ // prune empty coefficient sets
+ auto i = coeffSets.begin();
+ while(i != coeffSets.end()) {
+ if(i->isEmpty()) {
+ i = coeffSets.erase(i);
+ } else {
+ i++;
+ }
+ }
+ emit updateCoefficientsDone(success);
+}
+
+std::vector CalDevice::getCoefficientSets() const
+{
+ return coeffSets;
+}
+
+void CalDevice::addCoefficientSet(QString name)
+{
+ CoefficientSet set;
+ set.name = name;
+ set.ports = numPorts;
+ set.createEmptyCoefficients();
+ coeffSets.push_back(set);
+}
+
+QStringList CalDevice::getCoefficientSetNames()
+{
+ QString resp = usb->Query(":COEFF:LIST?");
+ if(!resp.startsWith("FACTORY")) {
+ return QStringList();
+ }
+ return resp.split(",");
+}
+
+bool CalDevice::hasModifiedCoefficients()
+{
+ for(auto set : coeffSets) {
+ for(auto c : set.opens) {
+ if(c.second->modified) {
+ return true;
+ }
+ }
+ for(auto c : set.shorts) {
+ if(c.second->modified) {
+ return true;
+ }
+ }
+ for(auto c : set.loads) {
+ if(c.second->modified) {
+ return true;
+ }
+ }
+ for(auto c : set.throughs) {
+ if(c.second->modified) {
+ return true;
+ }
+ }
+ }
+ return false;
+}
+
+void CalDevice::factoryUpdateDialog()
+{
+ auto d = new QDialog();
+ auto ui = new Ui::FactoryUpdateDialog();
+ ui->setupUi(d);
+
+ ui->progress->setValue(0);
+ connect(this, &CalDevice::updateCoefficientsPercent, ui->progress, &QProgressBar::setValue, Qt::QueuedConnection);
+
+ auto updateEnableState = [=]() {
+ ui->updateFile->setEnabled(true);
+ ui->updateServer->setEnabled(true);
+ if(ui->updateServer->isChecked()) {
+ // can start
+ ui->startUpdate->setEnabled(true);
+ // file selection disabled
+ ui->file->setEnabled(false);
+ ui->browse->setEnabled(false);
+ } else {
+ // file selection enabled
+ ui->file->setEnabled(true);
+ ui->browse->setEnabled(true);
+ // start possible if some file is selected
+ ui->startUpdate->setEnabled(!ui->file->text().isEmpty());
+ }
+ };
+
+ connect(ui->updateServer, &QRadioButton::toggled, this, updateEnableState);
+ connect(ui->file, &QLineEdit::textChanged, this, updateEnableState);
+ connect(ui->browse, &QPushButton::clicked, this, [=](){
+ auto filename = QFileDialog::getOpenFileName(nullptr, "Select factory coefficient file", "", "Zip files (*.zip)", nullptr, QFileDialog::DontUseNativeDialog);
+ if(filename.isEmpty()) {
+ // aborted selection
+ return;
+ } else {
+ ui->file->setText(filename);
+ updateEnableState();
+ }
+ });
+
+ auto addStatus = [=](QString status) {
+ ui->msg->appendPlainText(status);
+ };
+ auto abortWithError = [=](QString error) {
+ ui->progress->setValue(0);
+
+ QTextCharFormat tf;
+ tf = ui->msg->currentCharFormat();
+ tf.setForeground(QBrush(Qt::red));
+ ui->msg->setCurrentCharFormat(tf);
+ ui->msg->appendPlainText(error);
+ tf.setForeground(QBrush(Qt::black));
+ ui->msg->setCurrentCharFormat(tf);
+
+ updateEnableState();
+ };
+
+ connect(this, &CalDevice::updateCoefficientsDone, this, [=](bool success) {
+ // transfer complete
+
+ // pass on communication failures again
+ connect(usb, &USBDevice::communicationFailure, this, &CalDevice::disconnected);
+ if(success) {
+ ui->progress->setValue(100);
+ addStatus("...done");
+ updateEnableState();
+ } else {
+ abortWithError("Transferring coefficients to LibreCAL failed");
+ }
+ });
+
+ auto updateFromFile = [=](QString filename) {
+ addStatus("Unzipping file...");
+ if(!QMicroz::extract(filename, ".")) {
+ abortWithError("Extracting zip file failed");
+ return;
+ }
+ // create coefficient set
+ auto set = CoefficientSet();
+ set.name = "FACTORY";
+ set.ports = 4;
+ set.createEmptyCoefficients();
+ struct Coeff {
+ QString description;
+ QString filename;
+ CoefficientSet::Coefficient *coeff;
+ };
+ std::array coeffs = {{
+ {.description = "Port 1 open", .filename = "P1_OPEN.s1p", .coeff = set.opens[1]},
+ {.description = "Port 1 short", .filename = "P1_SHORT.s1p", .coeff = set.shorts[1]},
+ {.description = "Port 1 load", .filename = "P1_LOAD.s1p", .coeff = set.loads[1]},
+ {.description = "Port 2 open", .filename = "P2_OPEN.s1p", .coeff = set.opens[2]},
+ {.description = "Port 2 short", .filename = "P2_SHORT.s1p", .coeff = set.shorts[2]},
+ {.description = "Port 2 load", .filename = "P2_LOAD.s1p", .coeff = set.loads[2]},
+ {.description = "Port 3 open", .filename = "P3_OPEN.s1p", .coeff = set.opens[3]},
+ {.description = "Port 3 short", .filename = "P3_SHORT.s1p", .coeff = set.shorts[3]},
+ {.description = "Port 3 load", .filename = "P3_LOAD.s1p", .coeff = set.loads[3]},
+ {.description = "Port 4 open", .filename = "P4_OPEN.s1p", .coeff = set.opens[4]},
+ {.description = "Port 4 short", .filename = "P4_SHORT.s1p", .coeff = set.shorts[4]},
+ {.description = "Port 4 load", .filename = "P4_LOAD.s1p", .coeff = set.loads[4]},
+ {.description = "Port 1 to 2 through", .filename = "P12_THROUGH.s2p", .coeff = set.throughs[set.portsToThroughIndex(1,2)]},
+ {.description = "Port 1 to 3 through", .filename = "P13_THROUGH.s2p", .coeff = set.throughs[set.portsToThroughIndex(1,3)]},
+ {.description = "Port 1 to 4 through", .filename = "P14_THROUGH.s2p", .coeff = set.throughs[set.portsToThroughIndex(1,4)]},
+ {.description = "Port 2 to 3 through", .filename = "P23_THROUGH.s2p", .coeff = set.throughs[set.portsToThroughIndex(2,3)]},
+ {.description = "Port 2 to 4 through", .filename = "P24_THROUGH.s2p", .coeff = set.throughs[set.portsToThroughIndex(2,4)]},
+ {.description = "Port 3 to 4 through", .filename = "P34_THROUGH.s2p", .coeff = set.throughs[set.portsToThroughIndex(3,4)]},
+ }};
+ for(const Coeff &c : coeffs) {
+ addStatus("Loading coefficient ("+c.description+")...");
+ try {
+ auto t = Touchstone::fromFile(c.filename.toStdString());
+ c.coeff->t = t;
+ c.coeff->modified = true;
+ QFile rmfile(c.filename);
+ rmfile.remove();
+ } catch (const std::exception &e) {
+ abortWithError("Failed: "+QString::fromStdString(e.what()));
+ return;
+ }
+ }
+ // delete previous factory set if available
+ for(unsigned int i=0;iCmd(":FACT:ENABLEWRITE I_AM_SURE");
+ // delete all factory coefficients (this formats the factory partition)
+ success &= usb->Cmd(":FACT:DEL", 5000);
+
+ if(success) {
+ // start the transfer
+ addStatus("Transferring new coefficients to LibreCAL...");
+ // potential communication failures should not be passed on during this
+ disconnect(usb, &USBDevice::communicationFailure, this, &CalDevice::disconnected);
+ saveCoefficientSets();
+ } else {
+ abortWithError("Failed to erase previous factory calibration");
+ }
+ };
+
+ auto netw = new QNetworkAccessManager();
+ connect(netw, &QNetworkAccessManager::finished, this, [=](QNetworkReply *reply) {
+ if(reply->error() == QNetworkReply::NoError) {
+ // success
+ addStatus("Factory coefficients downloaded...");
+ QFile file(serial()+".zip");
+ if(!file.open(QIODevice::WriteOnly)) {
+ abortWithError("Failed to create folder for zipped data");
+ return;
+ }
+ file.write(reply->readAll());
+ file.flush();
+ file.close();
+ updateFromFile(serial()+".zip");
+ // remove zip file
+ file.remove();
+ } else {
+ abortWithError("No factory coefficients found. Check internet access and serial number");
+ }
+ });
+
+ connect(ui->startUpdate, &QPushButton::clicked, this, [=](){
+ ui->msg->clear();
+ ui->startUpdate->setEnabled(false);
+ ui->updateFile->setEnabled(false);
+ ui->updateServer->setEnabled(false);
+ ui->file->setEnabled(false);
+ ui->browse->setEnabled(false);
+ if(ui->updateServer->isChecked()) {
+ addStatus("Looking up factory coefficient data...");
+ QUrl url("https://librecal.kaeberich.com/calibrationdata/"+serial()+".zip");
+ netw->get(QNetworkRequest(url));
+ } else {
+ // update from file
+ updateFromFile(ui->file->text());
+ }
+ });
+
+ updateEnableState();
+
+ d->exec();
+}
+
+CalDevice::CoefficientSet::Coefficient *CalDevice::CoefficientSet::getOpen(int port)
+{
+ if(opens.count(port)) {
+ return opens[port];
+ } else {
+ return nullptr;
+ }
+}
+
+CalDevice::CoefficientSet::Coefficient *CalDevice::CoefficientSet::getShort(int port)
+{
+ if(shorts.count(port)) {
+ return shorts[port];
+ } else {
+ return nullptr;
+ }
+}
+
+CalDevice::CoefficientSet::Coefficient *CalDevice::CoefficientSet::getLoad(int port)
+{
+ if(loads.count(port)) {
+ return loads[port];
+ } else {
+ return nullptr;
+ }
+}
+
+CalDevice::CoefficientSet::Coefficient *CalDevice::CoefficientSet::getThrough(int port1, int port2)
+{
+ auto index = portsToThroughIndex(port1, port2);
+ if(throughs.count(index)) {
+ return throughs[index];
+ } else {
+ return nullptr;
+ }
+}
+
+int CalDevice::CoefficientSet::portsToThroughIndex(int port1, int port2)
+{
+ if(port1 > ports || port2 > ports || port1 >= port2) {
+ return -1;
+ }
+ return port1 * ports + port2;
+}
+
+void CalDevice::CoefficientSet::portsFromThroughIndex(int &port1, int &port2, int index)
+{
+ port1 = index / ports;
+ port2 = index - port1 * ports;
+ if(port1 < 1 || port1 > ports) {
+ port1 = -1;
+ }
+ if(port2 < 1 || port2 > ports) {
+ port2 = -1;
+ }
+}
+
+void CalDevice::CoefficientSet::createEmptyCoefficients()
+{
+ loads.clear();
+ shorts.clear();
+ opens.clear();
+ throughs.clear();
+ for(int i=1;i<=ports;i++) {
+ opens[i] = new Coefficient();
+ shorts[i] = new Coefficient();
+ loads[i] = new Coefficient();
+ for(int j=i+1;j<=ports;j++) {
+ throughs[portsToThroughIndex(i,j)] = new Coefficient();
+ }
+ }
+}
+
+bool CalDevice::CoefficientSet::isEmpty()
+{
+ for(auto o : opens) {
+ if(o.second->t.points() > 0) {
+ return false;
+ }
+ }
+ for(auto s : shorts) {
+ if(s.second->t.points() > 0) {
+ return false;
+ }
+ }
+ for(auto l : loads) {
+ if(l.second->t.points() > 0) {
+ return false;
+ }
+ }
+ for(auto t : throughs) {
+ if(t.second->t.points() > 0) {
+ return false;
+ }
+ }
+ // no coefficients or all coefficients empty
+ return true;
+}
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/caldevice.h b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/caldevice.h
new file mode 100644
index 0000000..1b05614
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/caldevice.h
@@ -0,0 +1,128 @@
+#ifndef CALDEVICE_H
+#define CALDEVICE_H
+
+#include "usbdevice.h"
+#include "touchstone.h"
+
+#include
+#include
+#include
+
+class CalDevice : public QObject
+{
+ Q_OBJECT
+public:
+ CalDevice(QString serial);
+ ~CalDevice();
+
+ class Standard {
+ public:
+ enum class Type {
+ Open,
+ Short,
+ Load,
+ Through,
+ None
+ };
+ Standard(Type type) : type(type), throughDest(0){}
+ Standard(int throughDest) : type(Type::Through), throughDest(throughDest){}
+ Type type;
+ int throughDest;
+ };
+
+ static QString StandardToString(Standard s);
+ static Standard StandardFromString(QString s);
+
+ Standard getStandard(int port);
+ bool setStandard(int port, Standard s);
+ static std::vector availableStandards();
+
+ double getTemperature();
+ bool stabilized();
+ double getHeaterPower();
+
+ QString serial();
+ QString getFirmware() const;
+ unsigned int getNumPorts() const;
+
+ QString getDateTimeUTC();
+
+ bool enterBootloader();
+
+ class CoefficientSet {
+ public:
+ QString name;
+ int ports;
+ class Coefficient {
+ public:
+ Coefficient() : t(Touchstone(1)), modified(false) {}
+ Touchstone t;
+ bool modified;
+ };
+
+ Coefficient *getOpen(int port);
+ Coefficient *getShort(int port);
+ Coefficient *getLoad(int port);
+ Coefficient *getThrough(int port1, int port2);
+
+ std::map opens;
+ std::map shorts;
+ std::map loads;
+ std::map throughs;
+
+ int portsToThroughIndex(int port1, int port2);
+ void portsFromThroughIndex(int &port1, int &port2, int index);
+
+ void createEmptyCoefficients();
+ bool isEmpty();
+ };
+
+ // Extracts the coefficients from the device. This is done with a dedicated thread.
+ // Do not call any other functions until the update is finished. Process can be
+ // monitored through the updateCoefficientsPercent and updateCoefficientsDone signals
+ void loadCoefficientSets(QStringList names = QStringList(), QList ports = {}, bool fast=true);
+
+ void abortCoefficientLoading();
+ // Writes coefficient sets to the device. This will only write modified files to save
+ // time. This is done with a dedicated thread.
+ // Do not call any other functions until the update is finished. Process can be
+ // monitored through the updateCoefficientsPercent and updateCoefficientsDone signals
+ void saveCoefficientSets();
+ std::vector getCoefficientSets() const;
+
+ void addCoefficientSet(QString name);
+
+ QStringList getCoefficientSetNames();
+
+ bool hasModifiedCoefficients();
+
+ bool coefficientTransferActive() { return transferActive; }
+
+public slots:
+ void factoryUpdateDialog();
+
+signals:
+ void updateCoefficientsPercent(int percent);
+ // emitted when all coefficients have been received and it is safe to call all functions again
+ void updateCoefficientsDone(bool success);
+
+ void disconnected();
+
+private:
+ void loadCoefficientSetsThreadSlow(QStringList names, QList ports);
+ void loadCoefficientSetsThreadFast(QStringList names, QList ports);
+ void saveCoefficientSetsThread();
+
+ USBDevice *usb;
+ QString firmware;
+ int numPorts;
+ std::thread *loadThread;
+ bool abortLoading;
+ bool transferActive;
+
+ float firmware_major_minor;
+
+ std::vector coeffSets;
+};
+
+#endif // CALDEVICE_H
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/factoryUpdateDialog.ui b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/factoryUpdateDialog.ui
new file mode 100644
index 0000000..b063441
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/factoryUpdateDialog.ui
@@ -0,0 +1,98 @@
+
+
+ FactoryUpdateDialog
+
+
+ Qt::ApplicationModal
+
+
+
+ 0
+ 0
+ 635
+ 448
+
+
+
+ Factory Coefficient Update
+
+
+ -
+
+
+ Updating the factory coefficients is normally not necessary. But in case they have been lost or modified accidentally, they can be set to the original state again.
+
+
+ true
+
+
+
+ -
+
+
+ Update coefficients from manufacturing server
+
+
+ true
+
+
+ buttonGroup
+
+
+
+ -
+
+
-
+
+
+ Update from file
+
+
+ buttonGroup
+
+
+
+ -
+
+
+ -
+
+
+ Select file
+
+
+ ...
+
+
+
+
+
+ -
+
+
+ Qt::NoFocus
+
+
+
+ -
+
+
+ 24
+
+
+
+ -
+
+
+ Update Factory Coefficients
+
+
+
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/librecaldialog.cpp b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/librecaldialog.cpp
new file mode 100644
index 0000000..3dde1c1
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/librecaldialog.cpp
@@ -0,0 +1,688 @@
+#include "librecaldialog.h"
+#include "ui_librecaldialog.h"
+
+#include "caldevice.h"
+#include "usbdevice.h"
+#include "CustomWidgets/informationbox.h"
+#include "preferences.h"
+
+#include
+
+#include
+
+using namespace std;
+
+LibreCALDialog::LibreCALDialog(Calibration *cal) :
+ QDialog(nullptr),
+ ui(new Ui::LibreCALDialog),
+ cal(cal),
+ device(nullptr),
+ busy(false)
+{
+ ui->setupUi(this);
+ setAttribute(Qt::WA_DeleteOnClose);
+
+ createPortAssignmentUI();
+
+ connect(this, &LibreCALDialog::portAssignmentChanged, this, &LibreCALDialog::updateCalibrationStartStatus);
+
+ connect(ui->cbDevice, &QComboBox::currentTextChanged, [=](QString text) {
+ if(device) {
+ delete device;
+ device = nullptr;
+ }
+ try {
+ device = new CalDevice(text);
+ } catch (exception &e) {
+ device = nullptr;
+ InformationBox::ShowError("Failed to connect", e.what(), this);
+ }
+ if(device) {
+ createPortAssignmentUI();
+ connect(device, &CalDevice::updateCoefficientsPercent, ui->progressCoeff, &QProgressBar::setValue);
+ connect(device, &CalDevice::updateCoefficientsDone, this, [=](bool success){
+ busy = false;
+ updateCalibrationStartStatus();
+ if(success) {
+ ui->progressCoeff->setValue(100);
+ ui->lCalibrationStatus->setText("Coefficients loaded.");
+ coeffSet = device->getCoefficientSets()[0];
+
+ if(validateCoefficients()) {
+ startCalibration();
+ } else {
+ enableUI();
+ }
+ } else {
+ ui->progressCal->setValue(0);
+ ui->lCalibrationStatus->setText("Failed to load coefficients");
+ }
+ }, Qt::QueuedConnection);
+
+ ui->cbCoefficients->clear();
+ ui->cbCoefficients->addItem("Select...");
+ for(auto c : device->getCoefficientSetNames()) {
+ ui->cbCoefficients->addItem(c);
+ }
+ ui->cbCoefficients->setEnabled(true);
+ // select first available coefficient set
+ if(ui->cbCoefficients->count() > 1) {
+ ui->cbCoefficients->setCurrentIndex(1);
+ }
+ } else {
+ ui->cbCoefficients->clear();
+ ui->cbCoefficients->setEnabled(false);
+ ui->start->setEnabled(false);
+ }
+ });
+
+ connect(ui->cbCoefficients, &QComboBox::currentTextChanged, [=](){
+ // no coefficient set selected
+ ui->progressCoeff->setValue(0);
+ coeffSet = CalDevice::CoefficientSet();
+ ui->lCalibrationStatus->setText("No coefficients loaded");
+ updateCalibrationStartStatus();
+ });
+
+ auto deviceList = USBDevice::GetDevices();
+ for(auto device : deviceList) {
+ ui->cbDevice->addItem(device);
+ }
+
+ connect(ui->start, &QPushButton::clicked, this, &LibreCALDialog::determineAutoPorts);
+ connect(this, &LibreCALDialog::autoPortComplete, this, &LibreCALDialog::loadCoefficients);
+
+ updateCalibrationStartStatus();
+ updateDeviceStatus();
+ connect(&updateTimer, &QTimer::timeout, this, &LibreCALDialog::updateDeviceStatus);
+ updateTimer.start(1000);
+}
+
+LibreCALDialog::~LibreCALDialog()
+{
+ if(device) {
+ device->abortCoefficientLoading();
+ }
+ delete device;
+ delete ui;
+}
+
+bool LibreCALDialog::validatePortSelection(bool autoAllowed)
+{
+ set usedCalPorts;
+ QString status;
+ bool canStart = true;
+ // Check port mapping for duplicate entries (and at least one used port)
+ for(auto port : portAssignment) {
+ if(autoAllowed && port == -1) {
+ // auto port, to be determined later
+ usedCalPorts.insert(port);
+ // skip duplicate selection
+ continue;
+ } else if(port < 1) {
+ // skip unused ports
+ continue;
+ }
+ if(usedCalPorts.count(port)) {
+ status = "LibreCAL port "+QString::number(port)+" is assigned to multiple VNA ports.";
+ canStart = false;
+ break;
+ } else {
+ usedCalPorts.insert(port);
+ }
+ }
+ if(canStart) {
+ // at least one port must be used
+ if(usedCalPorts.size() == 0) {
+ status = "At least one port must be assigned.";
+ canStart = false;
+ }
+ }
+ if(!canStart) {
+ ui->lCalibrationStatus->setText(status);
+ ui->lCalibrationStatus->setStyleSheet("QLabel { color : red; }");
+ }
+ return canStart;
+}
+
+bool LibreCALDialog::validateCoefficients()
+{
+ bool canStart = true;
+ QString status;
+
+ double coeffMinFreq = numeric_limits::max();
+ double coeffMaxFreq = numeric_limits::lowest();
+
+ auto checkCoefficient = [&](CalDevice::CoefficientSet::Coefficient *c) -> bool {
+ if(!c) {
+ return false;
+ }
+ if(c->t.points() == 0) {
+ return false;
+ } else {
+ if(c->t.minFreq() < coeffMinFreq) {
+ coeffMinFreq = c->t.minFreq();
+ }
+ if(c->t.maxFreq() > coeffMaxFreq) {
+ coeffMaxFreq = c->t.maxFreq();
+ }
+ return true;
+ }
+ };
+
+ set usedCalPorts;
+ // Check port mapping for duplicate entries (and at least one used port)
+ for(auto port : portAssignment) {
+ if(port > 0) {
+ usedCalPorts.insert(port);
+ }
+ }
+
+ // check if coefficients for all ports are available
+ for(auto i : usedCalPorts) {
+ // Check if OSL coefficients are there
+ if(!checkCoefficient(coeffSet.getOpen(i))) {
+ status = "Open coefficient for LibreCAL port "+QString::number(i)+" is missing.";
+ canStart = false;
+ break;
+ }
+ if(!checkCoefficient(coeffSet.getShort(i))) {
+ status = "Short coefficient for LibreCAL port "+QString::number(i)+" is missing.";
+ canStart = false;
+ break;
+ }
+ if(!checkCoefficient(coeffSet.getLoad(i))) {
+ status = "Load coefficient for LibreCAL port "+QString::number(i)+" is missing.";
+ canStart = false;
+ break;
+ }
+ for(auto j : usedCalPorts) {
+ if(j <= i) {
+ continue;
+ }
+ if(!checkCoefficient(coeffSet.getThrough(i,j))) {
+ status = "Through coefficient for LibreCAL port "+QString::number(i)+" to "+QString::number(j)+" is missing.";
+ canStart = false;
+ break;
+ }
+ }
+ }
+ if(!canStart) {
+ ui->lCalibrationStatus->setText(status);
+ ui->lCalibrationStatus->setStyleSheet("QLabel { color : red; }");
+ }
+ return canStart;
+}
+
+void LibreCALDialog::updateCalibrationStartStatus()
+{
+ bool canStart = true;
+ if(!device) {
+ canStart = false;
+ ui->lCalibrationStatus->setText("Not connected to a LibreCAL device");
+ ui->lCalibrationStatus->setStyleSheet("QLabel { color : red; }");
+ }
+
+ if(canStart) {
+ if(ui->cbCoefficients->currentIndex() == 0) {
+ canStart = false;
+ ui->lCalibrationStatus->setText("No coefficient set selected");
+ ui->lCalibrationStatus->setStyleSheet("QLabel { color : red; }");
+ }
+ }
+
+ if(canStart) {
+ canStart = validatePortSelection(true);
+ }
+
+ if(canStart) {
+ if(!Preferences::getInstance().Acquisition.allowUseOfUnstableLibreCALTemp && !device->stabilized()) {
+ canStart = false;
+ ui->lCalibrationStatus->setText("LibreCAL temperature unstable");
+ ui->lCalibrationStatus->setStyleSheet("QLabel { color : red; }");
+ }
+ }
+
+ ui->start->setEnabled(canStart);
+ if(canStart) {
+ ui->lCalibrationStatus->setText("Ready to start");
+ ui->lCalibrationStatus->setStyleSheet("");
+ }
+}
+
+void LibreCALDialog::updateDeviceStatus()
+{
+ if(!device) {
+ ui->lDeviceStatus->setText("No LibreCAL connected");
+ ui->lDeviceStatus->setStyleSheet("QLabel { color : red; }");
+ return;
+ }
+ if(busy) {
+ // can't update while busy reading coefficients
+ return;
+ }
+ if(device->stabilized()) {
+ ui->lDeviceStatus->setText("LibreCAL ready for calibration");
+ ui->lDeviceStatus->setStyleSheet("");
+ } else {
+ ui->lDeviceStatus->setText("Heating up, please wait with calibration");
+ ui->lDeviceStatus->setStyleSheet("QLabel { color : orange; }");
+ }
+ updateCalibrationStartStatus();
+}
+
+void LibreCALDialog::determineAutoPorts()
+{
+ disableUI();
+ ui->progressCal->setValue(0);
+ ui->lCalibrationStatus->setText("Autodetecting port connections...");
+ ui->lCalibrationStatus->setStyleSheet("QLabel { color : green; }");
+
+ // check if any ports are set to auto
+ bool usesAuto = false;
+ for(auto port : portAssignment) {
+ if(port == -1) {
+ usesAuto = true;
+ break;
+ }
+ }
+ if(usesAuto) {
+ driver = DeviceDriver::getActiveDriver();
+ emit driver->acquireControl();
+ // Determine ports by setting all ports to open and then switching them to short one at a time while observing the change in the VNA measurement
+ for(unsigned int i=1;i<=device->getNumPorts();i++) {
+ device->setStandard(i, CalDevice::Standard::Type::Open);
+ }
+ autoPortMeasurements.clear();
+ startSweep();
+ } else {
+ // no auto ports
+ emit autoPortComplete();
+ }
+}
+
+void LibreCALDialog::loadCoefficients()
+{
+ // validate ports again, at this point no "auto" selection is allowed anymore
+ if(!validatePortSelection(false)) {
+ enableUI();
+ updateCalibrationStartStatus();
+ } else {
+ // can continue with loading coefficients
+ // they might already be loaded from a previous calibration run, check first
+ if(!validateCoefficients()) {
+ // only load required coefficients
+ ui->progressCal->setValue(0);
+ ui->lCalibrationStatus->setText("Loading coefficients...");
+ ui->lCalibrationStatus->setStyleSheet("QLabel { color : green; }");
+
+ // determine the used ports of the LibreCAL
+ QList usedPorts;
+ for(auto port : portAssignment) {
+ if(port > 0) {
+ usedPorts.append(port);
+ }
+ }
+
+ busy = true;
+ device->loadCoefficientSets({ui->cbCoefficients->currentText()}, usedPorts);
+ } else {
+ // can proceed with calibration directly
+ startCalibration();
+ }
+ }
+}
+
+void LibreCALDialog::handleIncomingMeasurement(DeviceDriver::VNAMeasurement m)
+{
+ stopSweep();
+ autoPortMeasurements.push_back(m);
+ auto nextPort = autoPortMeasurements.size();
+ // switch LibreCAL to next port
+ if(nextPort <= device->getNumPorts()) {
+ device->setStandard(nextPort, CalDevice::Standard::Type::Short);
+ }
+ if(nextPort > 1) {
+ device->setStandard(nextPort-1, CalDevice::Standard::Type::Open);
+ }
+ if(nextPort > device->getNumPorts()) {
+ // auto port measurements complete
+
+ // reset LibreCAL ports
+ for(unsigned int i=1;i<=device->getNumPorts();i++) {
+ device->setStandard(i, CalDevice::Standard::Type::None);
+ }
+ // evaluate results
+ for(unsigned int p=0;p> measurements;
+ for(auto m : autoPortMeasurements) {
+ if(m.measurements.count(param)) {
+ measurements.push_back(m.measurements[param]);
+ }
+ }
+ if(measurements.size() != device->getNumPorts()+1) {
+ // not all measurements available (maybe the port has no stimulus?), set to unused
+ portAssignmentComboBoxes[p]->setCurrentIndex(0);
+ continue;
+ }
+ // got all required measurements, determine which one deviates the most from the baseline
+ double maxDeviation = 0.0;
+ int maxDevIndex = 0;
+ for(unsigned int i=1;i<=device->getNumPorts();i++) {
+ auto diff = abs(measurements[i] - measurements[0]);
+ if (diff > maxDeviation) {
+ maxDeviation = diff;
+ maxDevIndex = i;
+ }
+ }
+ constexpr double minRequiredDeviation = 0.25;
+ if(maxDeviation > minRequiredDeviation) {
+ portAssignmentComboBoxes[p]->setCurrentIndex(maxDevIndex+1);
+ } else {
+ // not enough deviation, probably unused
+ portAssignmentComboBoxes[p]->setCurrentIndex(0);
+ }
+ }
+ emit driver->releaseControl();
+ emit autoPortComplete();
+ } else {
+ // trigger the next measurement
+ startSweep();
+ }
+}
+
+void LibreCALDialog::startSweep()
+{
+ // set up a sweep with a single measurement point at the start frequency
+ auto info = driver->getInfo();
+ DeviceDriver::VNASettings s = {};
+ s.dBmStart = info.Limits.VNA.maxdBm;
+ s.dBmStop = info.Limits.VNA.maxdBm;
+
+ auto freq = info.Limits.VNA.minFreq == 0 ? 100000 : info.Limits.VNA.minFreq;
+
+ s.freqStart = freq;
+ s.freqStop = freq;
+ s.IFBW = 100;
+ s.logSweep = false;
+ s.points = 1;
+
+ for(unsigned int i=1;i<=info.Limits.VNA.ports;i++) {
+ s.excitedPorts.push_back(i);
+ }
+ driver->setVNA(s, [=](bool){
+ connect(driver, &DeviceDriver::VNAmeasurementReceived, this, &LibreCALDialog::handleIncomingMeasurement, Qt::DirectConnection);
+ });
+}
+
+void LibreCALDialog::stopSweep()
+{
+ disconnect(driver, &DeviceDriver::VNAmeasurementReceived, this, &LibreCALDialog::handleIncomingMeasurement);
+ driver->setIdle();
+}
+
+void LibreCALDialog::startCalibration()
+{
+ disableUI();
+ busy = true;
+
+ ui->progressCal->setValue(0);
+ ui->lCalibrationStatus->setText("Creating calibration kit from coefficients...");
+ ui->lCalibrationStatus->setStyleSheet("");
+ auto& kit = cal->getKit();
+ kit.clearStandards();
+ kit.manufacturer = "LibreCAL ("+coeffSet.name+")";
+ kit.serialnumber = device->serial();
+ kit.description = "Automatically created from LibreCAL module";
+
+ // determine the used ports of the LibreCAL
+ QList usedPorts;
+ for(auto port : portAssignment) {
+ if(port > 0) {
+ usedPorts.append(port);
+ }
+ }
+ std::sort(usedPorts.begin(), usedPorts.end());
+
+ std::map openStandards;
+ std::map shortStandards;
+ std::map loadStandards;
+ std::map throughStandards;
+ for(unsigned int idx=0;idxt.points() > 0) {
+ auto o = new CalStandard::Open();
+ o->setName("Port "+QString::number(i));
+ o->setMeasurement(coeffSet.getOpen(i)->t);
+ openStandards[i] = o;
+ kit.addStandard(o);
+ }
+ if(coeffSet.getShort(i)->t.points() > 0) {
+ auto o = new CalStandard::Short();
+ o->setName("Port "+QString::number(i));
+ o->setMeasurement(coeffSet.getShort(i)->t);
+ shortStandards[i] = o;
+ kit.addStandard(o);
+ }
+ if(coeffSet.getLoad(i)->t.points() > 0) {
+ auto o = new CalStandard::Load();
+ o->setName("Port "+QString::number(i));
+ o->setMeasurement(coeffSet.getLoad(i)->t);
+ loadStandards[i] = o;
+ kit.addStandard(o);
+ }
+ for(unsigned int jdx=idx+1;jdxt.points() > 0) {
+ auto o = new CalStandard::Through();
+ o->setName("Port "+QString::number(i)+" to "+QString::number(j));
+ o->setMeasurement(c->t);
+ throughStandards[coeffSet.portsToThroughIndex(i, j)] = o;
+ kit.addStandard(o);
+ }
+ }
+ }
+ ui->lCalibrationStatus->setText("Creating calibration measurements...");
+ cal->reset();
+ auto vnaPorts = DeviceDriver::getInfo(DeviceDriver::getActiveDriver()).Limits.VNA.ports;
+ set openMeasurements;
+ set shortMeasurements;
+ set loadMeasurements;
+ vector throughMeasurements;
+ for(unsigned int p=0;psetPort(p+1);
+ open->setStandard(openStandards[portAssignment[p]]);
+ openMeasurements.insert(open);
+ cal->measurements.push_back(open);
+
+ auto _short = new CalibrationMeasurement::Short(cal);
+ _short->setPort(p+1);
+ _short->setStandard(shortStandards[portAssignment[p]]);
+ shortMeasurements.insert(_short);
+ cal->measurements.push_back(_short);
+
+ auto load = new CalibrationMeasurement::Load(cal);
+ load->setPort(p+1);
+ load->setStandard(loadStandards[portAssignment[p]]);
+ loadMeasurements.insert(load);
+ cal->measurements.push_back(load);
+ for(unsigned int p2=p+1;p2setPort1(p+1);
+ through->setPort2(p2+1);
+ // find correct through standard
+ int libreCALp1 = portAssignment[p];
+ int libreCALp2 = portAssignment[p2];
+ QString forwardName = "Port "+QString::number(libreCALp1)+" to "+QString::number(libreCALp2);
+ QString reverseName = "Port "+QString::number(libreCALp2)+" to "+QString::number(libreCALp1);
+ for(auto ts : throughStandards) {
+ if(ts.second->getName() == forwardName) {
+ through->setStandard(ts.second);
+ through->setReverseStandard(false);
+ } else if(ts.second->getName() == reverseName) {
+ through->setStandard(ts.second);
+ through->setReverseStandard(true);
+ }
+ }
+ throughMeasurements.push_back(through);
+ cal->measurements.push_back(through);
+ }
+ }
+
+ ui->lCalibrationStatus->setText("Taking calibration measurements...");
+
+ measurementsTaken = 0;
+
+ auto setTerminationOnAllUsedPorts = [=](CalDevice::Standard s) {
+ for(auto p : portAssignment) {
+ if(p > 0) {
+ device->setStandard(p, s);
+ }
+ }
+ };
+
+ auto startNextCalibrationStep = [=]() {
+ // indicate calibration percentage
+ auto totalMeasurements = 3 + throughMeasurements.size();
+ ui->progressCal->setValue(measurementsTaken * 100 / totalMeasurements);
+ switch(measurementsTaken) {
+ case 0:
+ setTerminationOnAllUsedPorts(CalDevice::Standard(CalDevice::Standard::Type::Open));
+ emit cal->startMeasurements(openMeasurements);
+ break;
+ case 1:
+ setTerminationOnAllUsedPorts(CalDevice::Standard(CalDevice::Standard::Type::Short));
+ emit cal->startMeasurements(shortMeasurements);
+ break;
+ case 2:
+ setTerminationOnAllUsedPorts(CalDevice::Standard(CalDevice::Standard::Type::Load));
+ emit cal->startMeasurements(loadMeasurements);
+ break;
+ default: {
+ // into through measurements now
+ unsigned int throughIndex = measurementsTaken - 3;
+ if(throughIndex >= throughMeasurements.size()) {
+ // this was the last measurement
+ // Try to apply the calibration
+ Calibration::CalType type;
+ type.type = Calibration::Type::SOLT;
+ for(unsigned int i=0;i 0) {
+ // this VNA port was used in the calibration
+ type.usedPorts.push_back(i+1);
+ }
+ }
+ auto res = cal->compute(type);
+ if(res) {
+ ui->progressCal->setValue(100);
+ ui->lCalibrationStatus->setText("Calibration activated.");
+ } else {
+ ui->progressCal->setValue(0);
+ ui->lCalibrationStatus->setText("Failed to activate calibration.");
+ ui->lCalibrationStatus->setStyleSheet("QLabel { color : red; }");
+ }
+ // sever connection to this function
+ disconnect(cal, &Calibration::measurementsUpdated, this, nullptr);
+ setTerminationOnAllUsedPorts(CalDevice::Standard(CalDevice::Standard::Type::None));
+ enableUI();
+ busy = false;
+ break;
+ }
+ setTerminationOnAllUsedPorts(CalDevice::Standard(CalDevice::Standard::Type::None));
+ auto m = throughMeasurements[throughIndex];
+ device->setStandard(portAssignment[m->getPort1()-1], CalDevice::Standard(portAssignment[m->getPort2()-1]));
+ emit cal->startMeasurements({m});
+ }
+ break;
+ }
+ measurementsTaken++;
+ };
+
+ disconnect(cal, &Calibration::measurementsUpdated, this, nullptr);
+ connect(cal, &Calibration::measurementsUpdated, this, startNextCalibrationStep, Qt::QueuedConnection);
+ connect(cal, &Calibration::measurementsAborted, this, [=](){
+ setTerminationOnAllUsedPorts(CalDevice::Standard(CalDevice::Standard::Type::None));
+ enableUI();
+ busy = false;
+ ui->lCalibrationStatus->setText("Ready to start");
+ });
+
+ startNextCalibrationStep();
+}
+
+void LibreCALDialog::disableUI()
+{
+ ui->cbDevice->setEnabled(false);
+ ui->cbCoefficients->setEnabled(false);
+ ui->start->setEnabled(false);
+ for(auto cb : portAssignmentComboBoxes) {
+ cb->setEnabled(false);
+ }
+}
+
+void LibreCALDialog::enableUI()
+{
+ ui->cbDevice->setEnabled(true);
+ ui->cbCoefficients->setEnabled(true);
+ ui->start->setEnabled(true);
+ for(auto cb : portAssignmentComboBoxes) {
+ cb->setEnabled(true);
+ }
+}
+
+void LibreCALDialog::createPortAssignmentUI()
+{
+ auto layout = static_cast(ui->assignmentBox->layout());
+ // Clear any possible previous elements
+ portAssignment.clear();
+ portAssignmentComboBoxes.clear();
+ while(layout->rowCount() > 1) {
+ layout->removeRow(1);
+ }
+ auto vnaPorts = DeviceDriver::getInfo(DeviceDriver::getActiveDriver()).Limits.VNA.ports;
+ portAssignment.resize(vnaPorts, 0);
+ auto calPorts = 0;
+ if(device) {
+ calPorts = device->getNumPorts();
+ }
+ QStringList choices = {"Unused", "Auto"};
+ for(int i=1;i<=calPorts;i++) {
+ choices.push_back("Port "+QString::number(i));
+ }
+ for(unsigned int p = 1;p<=vnaPorts;p++) {
+ auto label = new QLabel("Port "+QString::number(p)+":");
+ auto comboBox = new QComboBox();
+ comboBox->addItems(choices);
+ connect(comboBox, qOverload(&QComboBox::currentIndexChanged), [=](){
+ if(comboBox->currentText().startsWith("Unused")) {
+ portAssignment[p-1] = 0;
+ } else if(comboBox->currentText().startsWith("Auto")) {
+ portAssignment[p-1] = -1;
+ } else if(comboBox->currentText().startsWith("Port")) {
+ portAssignment[p-1] = comboBox->currentText().back().digitValue();
+ }
+ emit portAssignmentChanged();
+ });
+ comboBox->setCurrentIndex(1);
+ layout->addRow(label, comboBox);
+ portAssignmentComboBoxes.push_back(comboBox);
+ }
+}
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/librecaldialog.h b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/librecaldialog.h
new file mode 100644
index 0000000..ca36b64
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/librecaldialog.h
@@ -0,0 +1,60 @@
+#ifndef LIBRECALDIALOG_H
+#define LIBRECALDIALOG_H
+
+#include "Calibration/calibration.h"
+#include "caldevice.h"
+#include "Device/devicedriver.h"
+
+#include
+#include
+#include
+
+namespace Ui {
+class LibreCALDialog;
+}
+
+class LibreCALDialog : public QDialog
+{
+ Q_OBJECT
+
+public:
+ explicit LibreCALDialog(Calibration *cal);
+ ~LibreCALDialog();
+
+private:
+signals:
+ void portAssignmentChanged();
+ void autoPortComplete();
+private slots:
+ bool validatePortSelection(bool autoAllowed);
+ bool validateCoefficients();
+ void updateCalibrationStartStatus();
+ void updateDeviceStatus();
+ void determineAutoPorts();
+ void loadCoefficients();
+ void startCalibration();
+
+ // auto port slots
+ void handleIncomingMeasurement(DeviceDriver::VNAMeasurement m);
+ void startSweep();
+ void stopSweep();
+private:
+ void disableUI();
+ void enableUI();
+ void createPortAssignmentUI();
+ Ui::LibreCALDialog *ui;
+ Calibration *cal;
+ CalDevice *device;
+ CalDevice::CoefficientSet coeffSet;
+ QTimer updateTimer;
+ bool busy;
+ // 0 for unused port, -1 for auto port, otherwise the port number
+ std::vector portAssignment;
+ std::vector portAssignmentComboBoxes;
+ std::vector autoPortMeasurements;
+ DeviceDriver *driver;
+
+ int measurementsTaken;
+};
+
+#endif // LIBRECALDIALOG_H
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/librecaldialog.ui b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/librecaldialog.ui
new file mode 100644
index 0000000..7b3867c
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/librecaldialog.ui
@@ -0,0 +1,160 @@
+
+
+ LibreCALDialog
+
+
+
+ 0
+ 0
+ 399
+ 405
+
+
+
+ Electronic Calibration Dialog
+
+
+ true
+
+
+ -
+
+
+ Device Selection
+
+
+
-
+
+
-
+
+
+ Device:
+
+
+
+ -
+
+
+
+
+ -
+
+
+ DEVICE_STATUS_PLACEHOLDER
+
+
+
+ -
+
+
-
+
+
+ Coefficients:
+
+
+
+ -
+
+
+
+
+
+
+
+ -
+
+
+ Port Assignments
+
+
+
-
+
+
+ LibreVNA
+
+
+ Qt::AlignCenter
+
+
+
+ -
+
+
+ LibreCAL
+
+
+ Qt::AlignCenter
+
+
+
+
+
+
+ -
+
+
+ Calibration
+
+
+
-
+
+
+ Start
+
+
+
+ ..
+
+
+
+ -
+
+
-
+
+
+ Coefficients:
+
+
+
+ -
+
+
+ 0
+
+
+
+
+
+ -
+
+
-
+
+
+ Calibration:
+
+
+
+ -
+
+
+ 0
+
+
+
+
+
+ -
+
+
+ CALIBRATION_STATUS_PLACEHOLDER
+
+
+
+
+
+
+
+
+
+
+
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/usbdevice.cpp b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/usbdevice.cpp
new file mode 100644
index 0000000..fe8e1c5
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/usbdevice.cpp
@@ -0,0 +1,290 @@
+#include "usbdevice.h"
+
+#include "CustomWidgets/informationbox.h"
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+using namespace std;
+
+using USBID = struct {
+ int VID;
+ int PID;
+};
+static constexpr USBID IDs[] = {
+ {0x0483, 0x4122},
+ {0x1209, 0x4122},
+};
+
+USBDevice::USBDevice(QString serial)
+{
+ m_handle = nullptr;
+ libusb_init(&m_context);
+#if LIBUSB_API_VERSION >= 0x01000106
+ libusb_set_option(m_context, LIBUSB_OPTION_LOG_LEVEL, LIBUSB_LOG_LEVEL_INFO);
+#endif
+
+ SearchDevices([=](libusb_device_handle *handle, QString found_serial) -> bool {
+ if(serial.isEmpty() || serial == found_serial) {
+ // accept connection to this device
+ m_serial = found_serial;
+ m_handle = handle;
+ // abort device search
+ return false;
+ } else {
+ // not the requested device, continue search
+ return true;
+ }
+ }, m_context, false);
+
+ if(!m_handle) {
+ QString message = "No device found";
+ if(!serial.isEmpty()) {
+ // only show error message if specific device was requested
+ InformationBox::ShowError("Error opening device", message);
+ }
+ libusb_exit(m_context);
+ throw std::runtime_error(message.toStdString());
+ return;
+ }
+
+ // Found the correct device, now connect
+ /* claim the interface */
+ int ret = libusb_claim_interface(m_handle, 2);
+ if (ret < 0) {
+ libusb_close(m_handle);
+ /* Failed to open */
+ QString message = "Failed to claim interface: \"";
+ message.append(libusb_strerror((libusb_error) ret));
+ message.append("\" Maybe you are already connected to this device?");
+ qWarning() << message;
+ InformationBox::ShowError("Error opening device", message);
+ libusb_exit(m_context);
+ throw std::runtime_error(message.toStdString());
+ }
+ qInfo() << "USB connection established" << Qt::flush;
+
+ connected = true;
+ m_receiveThread = new std::thread(&USBDevice::USBHandleThread, this);
+ usbBuffer = new USBInBuffer(m_handle, LIBUSB_ENDPOINT_IN | 0x03, 65536);
+ connect(usbBuffer, &USBInBuffer::DataReceived, this, &USBDevice::ReceivedData, Qt::DirectConnection);
+
+ // clear any possible queued data in USB device
+ QString dummy;
+ while(receive(&dummy, 10));
+}
+
+USBDevice::~USBDevice()
+{
+ delete usbBuffer;
+ connected = false;
+ libusb_release_interface(m_handle, 2);
+ libusb_close(m_handle);
+ m_receiveThread->join();
+ libusb_exit(m_context);
+ delete m_receiveThread;
+}
+
+bool USBDevice::Cmd(QString cmd, unsigned int timeout)
+{
+ QString rcv;
+ flushReceived();
+ bool success = send(cmd) && receive(&rcv, timeout);
+ if(success && rcv == "") {
+ // empty response expected by commad
+ return true;
+ } else {
+ // failed to send/receive
+ emit communicationFailure();
+ return false;
+ }
+}
+
+QString USBDevice::Query(QString query, unsigned int timeout)
+{
+ flushReceived();
+ if(send(query)) {
+ QString rcv;
+ if(receive(&rcv, timeout)) {
+ return rcv;
+ } else {
+ emit communicationFailure();
+ }
+ } else {
+ emit communicationFailure();
+ }
+ return QString();
+}
+
+
+std::set USBDevice::GetDevices()
+{
+ std::set serials;
+
+ libusb_context *ctx;
+ libusb_init(&ctx);
+#if LIBUSB_API_VERSION >= 0x01000106
+ libusb_set_option(ctx, LIBUSB_OPTION_LOG_LEVEL, LIBUSB_LOG_LEVEL_INFO);
+#endif
+
+ SearchDevices([&serials](libusb_device_handle *, QString serial) -> bool {
+ serials.insert(serial);
+ return true;
+ }, ctx, true);
+
+ libusb_exit(ctx);
+
+ return serials;
+}
+
+void USBDevice::SearchDevices(std::function foundCallback, libusb_context *context, bool ignoreOpenError)
+{
+ libusb_device **devList;
+ auto ndevices = libusb_get_device_list(context, &devList);
+
+ for (ssize_t idx = 0; idx < ndevices; idx++) {
+ int ret;
+ libusb_device *device = devList[idx];
+ libusb_device_descriptor desc = {};
+
+ ret = libusb_get_device_descriptor(device, &desc);
+ if (ret) {
+ /* some error occured */
+ qCritical() << "Failed to get device descriptor: "
+ << libusb_strerror((libusb_error) ret);
+ continue;
+ }
+
+ bool correctID = false;
+ int numIDs = sizeof(IDs)/sizeof(IDs[0]);
+ for(int i=0;i 0) {
+ /* managed to read the product string */
+ QString product(c_product);
+ if (product == "LibreCAL") {
+ // this is a match
+ if(!foundCallback(handle, QString(c_serial))) {
+ // abort search
+ break;
+ }
+ }
+ } else {
+ qWarning() << "Failed to get product descriptor: "
+ << libusb_strerror((libusb_error) ret);
+ }
+ libusb_close(handle);
+ }
+ libusb_free_device_list(devList, 1);
+}
+
+bool USBDevice::send(const QString &s)
+{
+ lineBuffer.clear();
+ qDebug() << "USB send:" << s;
+ unsigned char data[s.size()+2];
+ memcpy(data, s.toLatin1().data(), s.size());
+ memcpy(&data[s.size()], "\r\n", 2);
+ int actual;
+ auto r = libusb_bulk_transfer(m_handle, LIBUSB_ENDPOINT_OUT | 0x03, data, s.size() + 2, &actual, 0);
+ if(r == 0 && actual == s.size() + 2) {
+ return true;
+ } else {
+ return false;
+ }
+}
+
+bool USBDevice::receive(QString *s, unsigned int timeout)
+{
+ // check if we already have a line queued
+ unique_lock lck(mtx);
+ while(lineBuffer.size() == 0) {
+ // needs to wait for an incoming line
+ using namespace std::chrono_literals;
+ if(cv.wait_for(lck, std::chrono::milliseconds(timeout)) == cv_status::timeout) {
+ qWarning() << "Timed out while waiting for received line";
+ return false;
+ }
+ }
+ *s = lineBuffer.takeFirst();
+ qDebug() << "USB recv:" << *s;
+ return true;
+}
+
+void USBDevice::ReceivedData()
+{
+ uint16_t handled_len;
+ unique_lock lck(mtx);
+ do {
+ handled_len = 0;
+ auto firstLinebreak = (uint8_t*) memchr(usbBuffer->getBuffer(), '\n', usbBuffer->getReceived());
+ if(firstLinebreak) {
+ handled_len = firstLinebreak - usbBuffer->getBuffer();
+ auto line = QString::fromLatin1((const char*) usbBuffer->getBuffer(), handled_len - 1);
+
+ // add received line to buffer
+ lineBuffer.append(line);
+
+ usbBuffer->removeBytes(handled_len + 1);
+ }
+ } while(handled_len > 0);
+ if(lineBuffer.size() > 0) {
+ cv.notify_one();
+ }
+}
+
+void USBDevice::flushReceived()
+{
+ unique_lock lck(mtx);
+ lineBuffer.clear();
+}
+
+void USBDevice::USBHandleThread()
+{
+ qDebug() << "Receive thread started";
+ while (connected) {
+ libusb_handle_events(m_context);
+ }
+ qDebug() << "Disconnected, receive thread exiting";
+}
+
+QString USBDevice::serial() const
+{
+ return m_serial;
+}
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/usbdevice.h b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/usbdevice.h
new file mode 100644
index 0000000..2df5458
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/LibreCAL/usbdevice.h
@@ -0,0 +1,61 @@
+#ifndef USBDEVICE_H
+#define USBDEVICE_H
+
+#include "Util/usbinbuffer.h"
+
+#include
+#ifdef Q_OS_MACOS
+#include
+#else
+#include
+#endif
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+class USBDevice : public QObject
+{
+ Q_OBJECT
+public:
+ // connect to a CAL device. If serial is specified only connecting to this device, otherwise to the first one found
+ USBDevice(QString serial = QString());
+ ~USBDevice();
+
+ bool Cmd(QString cmd, unsigned int timeout = 2000);
+ QString Query(QString query, unsigned int timeout = 2000);
+ QString serial() const;
+
+ // Returns serial numbers of all connected devices
+ static std::set GetDevices();
+
+ bool send(const QString &s);
+ bool receive(QString *s, unsigned int timeout = 2000);
+ void flushReceived();
+signals:
+ void communicationFailure();
+
+private slots:
+ void ReceivedData();
+private:
+ void USBHandleThread();
+ bool connected;
+ std::thread *m_receiveThread;
+
+ static void SearchDevices(std::function foundCallback, libusb_context *context, bool ignoreOpenError);
+ libusb_device_handle *m_handle;
+ libusb_context *m_context;
+
+ USBInBuffer *usbBuffer;
+ std::mutex mtx;
+ std::condition_variable cv;
+ QStringList lineBuffer;
+
+ QString m_serial;
+};
+
+#endif // DEVICE_H
diff --git a/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/calibration.cpp b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/calibration.cpp
new file mode 100644
index 0000000..8f63534
--- /dev/null
+++ b/device_firmware/multi_libreVNA_firmware/reproduce/LibreVNA/Software/PC_Application/LibreVNA-GUI/Calibration/calibration.cpp
@@ -0,0 +1,2229 @@
+#include "calibration.h"
+#include "ui_calibrationdialogui.h"
+#include "CustomWidgets/informationbox.h"
+#include "Util/app_common.h"
+#include "unit.h"
+#include "Util/util.h"
+#include "LibreCAL/librecaldialog.h"
+#include "preferences.h"
+#include "Traces/sparamtraceselectordialog.h"
+
+#include "Tools/Eigen/Dense"
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+using namespace std;
+using Eigen::MatrixXcd;
+
+bool operator==(const Calibration::CalType &lhs, const Calibration::CalType &rhs) {
+ if(lhs.type != rhs.type) {
+ return false;
+ }
+ if(lhs.usedPorts.size() != rhs.usedPorts.size()) {
+ return false;
+ }
+ for(unsigned int i=0;i QString {
+ if(params.size() != 1) {
+ return SCPI::getResultName(SCPI::Result::Error);
+ } else {
+ auto availableCals = getAvailableCalibrations();
+ for(auto caltype : availableCals) {
+ if(caltype.getShortString().compare(params[0], Qt::CaseInsensitive) == 0) {
+ // found a match
+ // check if calibration can be activated
+ if(canCompute(caltype)) {
+ compute(caltype);
+ return SCPI::getResultName(SCPI::Result::Empty);
+ } else {
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ }
+ }
+ // if we get here, the supplied parameter did not match any of the available calibrations
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ return SCPI::getResultName(SCPI::Result::Empty);
+ }, [=](QStringList) -> QString {
+ auto availableCals = getAvailableCalibrations();
+ if(availableCals.size() == 0) {
+ return SCPI::getResultName(SCPI::Result::Empty);
+ }
+ auto ret = availableCals[0].getShortString();
+ for(unsigned int i=1;i QString {
+ return caltype.getShortString();
+ }));
+ add(new SCPICommand("NUMber", nullptr, [=](QStringList) -> QString {
+ return QString::number(measurements.size());
+ }));
+ add(new SCPICommand("RESET", [=](QStringList) -> QString {
+ reset();
+ return SCPI::getResultName(SCPI::Result::Empty);
+ }, nullptr));
+ add(new SCPICommand("ADD", [=](QStringList params) -> QString {
+ if(params.size() < 1) {
+ // no measurement type specified
+ return SCPI::getResultName(SCPI::Result::Error);
+ } else {
+ // parse measurement type
+ auto type = CalibrationMeasurement::Base::TypeFromString(params[0]);
+ auto newMeas = newMeasurement(type);
+ if(!newMeas) {
+ // failed to create this type of measurement
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ if(params.size() == 2) {
+ // standard name given
+ CalStandard::Virtual *standard = nullptr;
+ for(auto s : newMeas->supportedStandards()) {
+ if(s->getName().compare(params[1], Qt::CaseInsensitive) == 0) {
+ // use this standard
+ standard = s;
+ }
+ }
+ if(!standard) {
+ // specified standard not available
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ newMeas->setStandard(standard);
+ }
+ measurements.push_back(newMeas);
+ return SCPI::getResultName(SCPI::Result::Empty);
+ }
+ }, nullptr));
+ add(new SCPICommand("TYPE", nullptr, [=](QStringList params) -> QString {
+ if(params.size() < 1) {
+ // no measurement number specified
+ return SCPI::getResultName(SCPI::Result::Error);
+ } else {
+ bool okay;
+ unsigned int number = params[0].toUInt(&okay);
+ if(!okay || number >= measurements.size()) {
+ // invalid measurement specified
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ return CalibrationMeasurement::Base::TypeToString(measurements[number]->getType());
+ }
+ }));
+ add(new SCPICommand("PORT", [=](QStringList params) -> QString {
+ if(params.size() < 1) {
+ // invalid number of parameters
+ return SCPI::getResultName(SCPI::Result::Error);
+ } else {
+ bool okay;
+ unsigned int number = params[0].toUInt(&okay);
+ if(!okay || number >= measurements.size()) {
+ // invalid measurement specified
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ auto meas = measurements[number];
+ auto onePort = dynamic_cast(meas);
+ if(onePort) {
+ if(params.size() != 2) {
+ // invalid number of parameters
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ bool okay;
+ unsigned int number = params[1].toInt(&okay);
+ if(!okay || number < 1 || number > DeviceDriver::getInfo(DeviceDriver::getActiveDriver()).Limits.VNA.ports) {
+ // invalid port specified
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ onePort->setPort(number);
+ return SCPI::getResultName(SCPI::Result::Empty);
+ }
+ auto twoPort = dynamic_cast(meas);
+ if(twoPort) {
+ if(params.size() != 3) {
+ // invalid number of parameters
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ bool okay1;
+ unsigned int port1 = params[1].toInt(&okay1);
+ bool okay2;
+ unsigned int port2 = params[2].toInt(&okay2);
+ if(!okay1 || !okay2 || port1 < 1 || port2 > DeviceDriver::getInfo(DeviceDriver::getActiveDriver()).Limits.VNA.ports
+ || port2 < 1 || port2 > DeviceDriver::getInfo(DeviceDriver::getActiveDriver()).Limits.VNA.ports) {
+ // invalid port specified
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ twoPort->setPort1(port1);
+ twoPort->setPort2(port2);
+ return SCPI::getResultName(SCPI::Result::Empty);
+ }
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ }, [=](QStringList params) -> QString {
+ if(params.size() != 1) {
+ // invalid number of parameters
+ return SCPI::getResultName(SCPI::Result::Error);
+ } else {
+ bool okay;
+ unsigned int number = params[0].toUInt(&okay);
+ if(!okay || number >= measurements.size()) {
+ // invalid measurement specified
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ auto meas = measurements[number];
+ auto onePort = dynamic_cast(meas);
+ if(onePort) {
+ return QString::number(onePort->getPort());
+ }
+ auto twoPort = dynamic_cast(meas);
+ if(twoPort) {
+ return QString::number(twoPort->getPort1()) + " " + QString::number(twoPort->getPort2());
+ }
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ }));
+ add(new SCPICommand("STANDARD", [=](QStringList params) -> QString {
+ if(params.size() != 2) {
+ // invalid number of parameters
+ return SCPI::getResultName(SCPI::Result::Error);
+ } else {
+ bool okay;
+ unsigned int number = params[0].toUInt(&okay);
+ if(!okay || number >= measurements.size()) {
+ // invalid measurement specified
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ auto meas = measurements[number];
+ for(auto s : meas->supportedStandards()) {
+ if(s->getName().compare(params[1], Qt::CaseInsensitive) == 0) {
+ // use this standard
+ meas->setStandard(s);
+ return SCPI::getResultName(SCPI::Result::Empty);
+ }
+ }
+ // specified standard not available
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ }, [=](QStringList params) -> QString {
+ if(params.size() != 1) {
+ // invalid number of parameters
+ return SCPI::getResultName(SCPI::Result::Error);
+ } else {
+ bool okay;
+ unsigned int number = params[0].toUInt(&okay);
+ if(!okay || number >= measurements.size()) {
+ // invalid measurement specified
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ auto s = measurements[number]->getStandard();
+ if(s) {
+ return s->getName();
+ } else {
+ // no standard set
+ return "None";
+ }
+ }
+ }));
+ add(new SCPICommand("MEASure", [=](QStringList params) -> QString {
+ if(params.size() < 1 ) {
+ // no measurement specified
+ // TODO check if measurement is already running
+ return SCPI::getResultName(SCPI::Result::Error);
+ } else {
+ // assemble list of measurements to take
+ std::set m;
+ for(QString p : params) {
+ bool okay = false;
+ unsigned int number = p.toUInt(&okay);
+ if(!okay || number >= measurements.size()) {
+ // invalid measurement specified
+ return SCPI::getResultName(SCPI::Result::Error);
+ } else {
+ m.insert(measurements[number]);
+ }
+ }
+ if(CalibrationMeasurement::Base::canMeasureSimultaneously(m)) {
+ emit startMeasurements(m);
+ return SCPI::getResultName(SCPI::Result::Empty);
+ } else {
+ // can't start these measurements simultaneously
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ }
+ }, nullptr));
+ add(new SCPICommand("SAVE", [=](QStringList params) -> QString {
+ if(params.size() != 1 || getCaltype().type == Calibration::Type::None) {
+ // no filename given or no calibration active
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ if(!toFile(params[0])) {
+ // some error when writing the calibration file
+ return SCPI::getResultName(SCPI::Result::Error);
+ }
+ return SCPI::getResultName(SCPI::Result::Empty);
+ }, nullptr, false));
+ add(new SCPICommand("LOAD", nullptr, [=](QStringList params) -> QString {
+ if(params.size() != 1) {
+ // no filename given or no calibration active
+ return SCPI::getResultName(SCPI::Result::False);
+ }
+ if(!fromFile(params[0])) {
+ // some error when loading the calibration file
+ return SCPI::getResultName(SCPI::Result::False);
+ }
+ return SCPI::getResultName(SCPI::Result::True);
+ }, false));
+ add(&kit);
+}
+
+QString Calibration::TypeToString(Calibration::Type type)
+{
+ switch(type) {
+ case Type::None: return "None";
+ case Type::OSL: return "OSL";
+ case Type::SOLT: return "SOLT";
+ case Type::SOLTwithoutRxMatch: return "SOLTwithoutRxMatch";
+ case Type::ThroughNormalization: return "ThroughNormalization";
+ case Type::TRL: return "TRL";
+ case Type::Last: return "Invalid";
+ }
+ return "";
+}
+
+Calibration::Type Calibration::TypeFromString(QString s)
+{
+ for(int i=0;i<(int) Type::Last;i++) {
+ if(TypeToString((Type) i) == s) {
+ return (Type) i;
+ }
+ }
+ return Type::None;
+}
+
+void Calibration::correctMeasurement(DeviceDriver::VNAMeasurement &d)
+{
+ lock_guard guard(access);
+ if(caltype.type == Type::None) {
+ // no calibration active, nothing to do
+ return;
+ }
+ // formulas from "Multi-Port Calibration Techniques for Differential Parameter Measurements with Network Analyzers", variable names also losely follow this document
+ MatrixXcd S(caltype.usedPorts.size(), caltype.usedPorts.size());
+ MatrixXcd a(caltype.usedPorts.size(), caltype.usedPorts.size());
+ MatrixXcd b(caltype.usedPorts.size(), caltype.usedPorts.size());
+
+ // gab point and interpolate
+ Point p;
+ if(d.frequency <= points.front().frequency) {
+ p = points.front();
+ } else if(d.frequency >= points.back().frequency) {
+ p = points.back();
+ } else {
+ // needs to interpolate
+ auto lower = lower_bound(points.begin(), points.end(), d.frequency, [](const Point &lhs, double rhs) -> bool {
+ return lhs.frequency < rhs;
+ });
+ auto highPoint = *lower;
+ auto lowPoint = *prev(lower);
+ double alpha = (d.frequency - lowPoint.frequency) / (highPoint.frequency - lowPoint.frequency);
+
+ p = lowPoint.interpolate(highPoint, alpha);
+ }
+
+ // Grab measurements (easier to access by index later)
+ for(unsigned int i=0;i traceSet)
+{
+ auto points = Trace::assembleDatapoints(traceSet);
+ if(points.size()) {
+ // succeeded in assembling datapoints
+ for(auto &p : points) {
+ correctMeasurement(p);
+ }
+ Trace::fillFromDatapoints(traceSet, points);
+ }
+}
+
+void Calibration::edit(TraceModel *traceModel)
+{
+ auto d = new QDialog();
+ d->setAttribute(Qt::WA_DeleteOnClose);
+ auto ui = new Ui::CalibrationDialog;
+ ui->setupUi(d);
+
+ ui->calMinFreq->setUnit("Hz");
+ ui->calMinFreq->setPrecision(4);
+ ui->calMinFreq->setPrefixes(" kMG");
+ ui->calMaxFreq->setUnit("Hz");
+ ui->calMaxFreq->setPrecision(4);
+ ui->calMaxFreq->setPrefixes(" kMG");
+
+ // generate all possible calibration with the connected device
+ vector availableCals = getAvailableCalibrations();
+
+ for(auto c : availableCals) {
+ ui->calibrationList->addItem(c.getReadableDescription());
+ }
+
+ auto updateCalStatistics = [=](){
+ lock_guard guard(access);
+ ui->activeCalibration->setText(caltype.getReadableDescription());
+ ui->calPoints->setValue(points.size());
+ if(points.size() > 0) {
+ ui->calMinFreq->setValue(points.front().frequency);
+ ui->calMaxFreq->setValue(points.back().frequency);
+ } else {
+ ui->calMinFreq->setValue(0);
+ ui->calMaxFreq->setValue(0);
+ }
+ };
+
+ auto updateCalButtons = [=](){
+ lock_guard guard(access);
+ auto row = ui->calibrationList->currentRow();
+ if(row < 0) {
+ ui->activate->setEnabled(false);
+ ui->deactivate->setEnabled(false);
+ } else {
+ if(caltype == availableCals[row]) {
+ ui->deactivate->setEnabled(true);
+ ui->activate->setEnabled(false);
+ } else {
+ ui->deactivate->setEnabled(false);
+ ui->activate->setEnabled(canCompute(availableCals[row]));
+ }
+ }
+ };
+
+ auto updateCalibrationList = [=](){
+ auto style = QApplication::style();
+ for(unsigned int i=0;istandardIcon(QStyle::SP_DialogApplyButton);
+ } else {
+ icon = style->standardIcon(QStyle::SP_MessageBoxCritical);
+ }
+ ui->calibrationList->item(i)->setIcon(icon);
+ }
+ updateCalButtons();
+ };
+
+ updateCalibrationList();
+ updateCalStatistics();
+ updateCalButtons();
+
+ connect(ui->calibrationList, &QListWidget::doubleClicked, [=](const QModelIndex&) {
+ ui->activate->clicked();
+ });
+
+ connect(ui->calibrationList, &QListWidget::currentRowChanged, [=](){
+ updateCalButtons();
+ });
+
+ connect(this, &Calibration::activated, d, [=](){
+ updateCalibrationList();
+ updateCalStatistics();
+ updateCalButtons();
+ });
+
+ connect(this, &Calibration::deactivated, d, [=](){
+ updateCalibrationList();
+ updateCalStatistics();
+ updateCalButtons();
+ });
+
+ connect(ui->activate, &QPushButton::clicked, [=](){
+ auto cal = availableCals[ui->calibrationList->currentRow()];
+ compute(cal);
+ });
+
+ connect(ui->deactivate, &QPushButton::clicked, this, &Calibration::deactivate);
+
+ ui->table->horizontalHeader()->setSectionResizeMode(QHeaderView::ResizeToContents);
+
+ auto updateTableEditButtons = [=](){
+ ui->bDelete->setEnabled(ui->table->currentRow() >= 0);
+ ui->bMoveUp->setEnabled(ui->table->currentRow() >= 1);
+ ui->bMoveDown->setEnabled(ui->table->currentRow() >= 0 && ui->table->currentRow() < ui->table->rowCount() - 1);
+ auto selected = ui->table->selectionModel()->selectedRows();
+ ui->measure->setEnabled(selected.size() > 0);
+ ui->selectMeasurement->setEnabled(traceModel && selected.size() == 1);
+ ui->clearMeasurement->setEnabled(selected.size() > 0);
+ };
+
+ auto updateMeasurementTable = [=](){
+ int row = ui->table->currentRow();
+ ui->table->clear();
+ ui->table->setColumnCount(5);
+ ui->table->setHorizontalHeaderItem(0, new QTableWidgetItem("Type"));
+ ui->table->setHorizontalHeaderItem(1, new QTableWidgetItem("Calkit Standard"));
+ ui->table->setHorizontalHeaderItem(2, new QTableWidgetItem("Settings"));
+ ui->table->setHorizontalHeaderItem(3, new QTableWidgetItem("Statistics"));
+ ui->table->setHorizontalHeaderItem(4, new QTableWidgetItem("Timestamp"));
+ ui->table->setRowCount(measurements.size());
+ for(unsigned int i=0;itable->setItem(i, 0, new QTableWidgetItem(CalibrationMeasurement::Base::TypeToString(measurements[i]->getType())));
+ ui->table->setCellWidget(i, 1, measurements[i]->createStandardWidget());
+ ui->table->setCellWidget(i, 2, measurements[i]->createSettingsWidget());
+ ui->table->setItem(i, 3, measurements[i]->getStatisticsItem());
+ ui->table->setItem(i, 4, new QTableWidgetItem(measurements[i]->getTimestamp().toLocalTime().toString()));
+ }
+ ui->table->setEditTriggers(QAbstractItemView::NoEditTriggers);
+ ui->table->selectRow(row);
+ updateTableEditButtons();
+ };
+
+ ui->createDefault->addItem(" ");
+ for(unsigned int i=0;i<(int) DefaultMeasurements::Last;i++) {
+ ui->createDefault->addItem(DefaultMeasurementsToString((DefaultMeasurements) i));
+ }
+
+ QObject::connect(ui->createDefault, qOverload(&QComboBox::currentIndexChanged), [=](){
+ if(measurements.size() > 0) {
+ if(!InformationBox::AskQuestion("Create default entries?", "Do you want to remove all existing entries and create default calibration measurements instead?", true)) {
+ // user aborted
+ ui->createDefault->blockSignals(true);
+ ui->createDefault->setCurrentIndex(0);
+ ui->createDefault->blockSignals(false);
+ return;
+ }
+ deleteMeasurements();
+ }
+ createDefaultMeasurements((DefaultMeasurements) (ui->createDefault->currentIndex() - 1));
+ updateMeasurementTable();
+ updateCalibrationList();
+ ui->createDefault->blockSignals(true);
+ ui->createDefault->setCurrentIndex(0);
+ ui->createDefault->blockSignals(false);
+ });
+
+ QObject::connect(ui->bDelete, &QPushButton::clicked, [=](){
+ auto selected = ui->table->selectionModel()->selectedRows();
+ set toDelete;
+ for(auto s : selected) {
+ toDelete.insert(measurements[s.row()]);
+ }
+ while(toDelete.size() > 0) {
+ for(unsigned int i=0;ibMoveUp, &QPushButton::clicked, [=](){
+ auto row = ui->table->currentRow();
+ if(row >= 1) {
+ swap(measurements[row], measurements[row-1]);
+ ui->table->selectRow(row-1);
+ updateMeasurementTable();
+ }
+ });
+
+ QObject::connect(ui->bMoveDown, &QPushButton::clicked, [=](){
+ auto row = ui->table->currentRow();
+ if(row >= 0) {
+ swap(measurements[row], measurements[row+1]);
+ ui->table->selectRow(row+1);
+ updateMeasurementTable();
+ }
+ });
+
+ connect(ui->measure, &QPushButton::clicked, [=](){
+ std::set m;
+ auto selected = ui->table->selectionModel()->selectedRows();
+ for(auto s : selected) {
+ auto meas = measurements[s.row()];
+ if(!meas->readyForMeasurement()) {
+ InformationBox::ShowError("Unable to measure", CalibrationMeasurement::Base::TypeToString(meas->getType())+" measurement is not ready, please check that a valid calibration standard is selected");
+ return;
+ }
+ m.insert(measurements[s.row()]);
+ }
+ if(!CalibrationMeasurement::Base::canMeasureSimultaneously(m)) {
+ InformationBox::ShowError("Unable to measure", "Different selected measurements require the same port, unable to perform measurement");
+ return;
+ }
+ emit startMeasurements(m);
+ });
+
+ // double clicking on a row also starts the measurement
+ connect(ui->table, &QTableWidget::doubleClicked, this, [=](){
+ emit ui->measure->clicked();
+ });
+
+ connect(ui->selectMeasurement, &QPushButton::clicked, [=](){
+ auto selected = ui->table->selectionModel()->selectedRows();
+ if(selected.size() != 1) {
+ InformationBox::ShowError("Unable to select measurement", "Exactly one measurement must be selected");
+ return;
+ }
+ // figure out which S parameters we need
+ auto meas = measurements[selected[0].row()];
+ auto ports = meas->getPorts();
+ if(ports.size() == 0) {
+ InformationBox::ShowError("Unable to select measurement", "Selecting measurements for this type of calibration measurement is not supported");
+ return;
+ }
+ auto selector = new SParamTraceSelectorDialog(*traceModel, ports);
+ connect(selector, &SParamTraceSelectorDialog::tracesSelected, d, [=](std::vector traceMeasurements){
+ clearMeasurements({meas});
+ for(const auto &tm : traceMeasurements) {
+ addMeasurements({meas}, tm);
+ }
+ updateMeasurementTable();
+ updateCalibrationList();
+ });
+ selector->show();
+ });
+ if(!traceModel) {
+ // can not select a measurement if no trace model is supplied
+ ui->selectMeasurement->setEnabled(false);
+ }
+
+ connect(this, &Calibration::measurementsUpdated, d, [=](){
+ updateMeasurementTable();
+ updateCalibrationList();
+ if(caltype.type != Type::None) {
+ // update the calibration with the new measurement
+ if(canCompute(caltype)) {
+ compute(caltype);
+ } else {
+ // can not keep the calibration, disabled
+ deactivate();
+ }
+ }
+ });
+
+ connect(ui->clearMeasurement, &QPushButton::clicked, [=](){
+ auto selected = ui->table->selectionModel()->selectedRows();
+ for(auto s : selected) {
+ measurements[s.row()]->clearPoints();
+ }
+ // update calibration (may have changed due to deleted measurement)
+ if(canCompute(caltype)) {
+ compute(caltype);
+ } else {
+ deactivate();
+ }
+ updateMeasurementTable();
+ updateCalibrationList();
+ });
+
+ connect(ui->eCal, &QPushButton::clicked, [=](){
+ auto d = new LibreCALDialog(this);
+ d->show();
+ });
+
+ connect(ui->editCalkit, &QPushButton::clicked, [=](){
+ kit.edit([=](){
+ updateMeasurementTable();
+ // update calibration (may have changed due to edited calibration standard)
+ if(canCompute(caltype)) {
+ compute(caltype);
+ } else {
+ deactivate();
+ }
+ });
+ });
+
+ QObject::connect(ui->table, &QTableWidget::itemSelectionChanged, updateTableEditButtons);
+
+ auto addMenu = new QMenu();
+ for(auto t : CalibrationMeasurement::Base::availableTypes()) {
+ auto action = new QAction(CalibrationMeasurement::Base::TypeToString(t));
+ QObject::connect(action, &QAction::triggered, [=](){
+ auto newMeas = newMeasurement(t);
+ if(newMeas) {
+ measurements.push_back(newMeas);
+ updateMeasurementTable();
+ }
+ });
+ addMenu->addAction(action);
+ }
+
+ ui->bAdd->setMenu(addMenu);
+
+ updateMeasurementTable();
+
+ d->show();
+}
+
+CalibrationMeasurement::Base *Calibration::newMeasurement(CalibrationMeasurement::Base::Type type)
+{
+ CalibrationMeasurement::Base *m = nullptr;
+ switch(type) {
+ case CalibrationMeasurement::Base::Type::Open: m = new CalibrationMeasurement::Open(this); break;
+ case CalibrationMeasurement::Base::Type::Short: m = new CalibrationMeasurement::Short(this); break;
+ case CalibrationMeasurement::Base::Type::Load: m = new CalibrationMeasurement::Load(this); break;
+ case CalibrationMeasurement::Base::Type::SlidingLoad: m = new CalibrationMeasurement::SlidingLoad(this); break;
+ case CalibrationMeasurement::Base::Type::Reflect: m = new CalibrationMeasurement::Reflect(this); break;
+ case CalibrationMeasurement::Base::Type::Through: m = new CalibrationMeasurement::Through(this); break;
+ case CalibrationMeasurement::Base::Type::Isolation: m = new CalibrationMeasurement::Isolation(this); break;
+ case CalibrationMeasurement::Base::Type::Line: m = new CalibrationMeasurement::Line(this); break;
+ case CalibrationMeasurement::Base::Type::Last: break;
+ }
+ return m;
+}
+
+Calibration::Point Calibration::createInitializedPoint(double f) {
+ Point point;
+ point.frequency = f;
+ // resize vectors
+ point.D.resize(caltype.usedPorts.size(), 0.0);
+ point.R.resize(caltype.usedPorts.size(), 1.0);
+ point.S.resize(caltype.usedPorts.size(), 0.0);
+
+ point.L.resize(caltype.usedPorts.size());
+ point.T.resize(caltype.usedPorts.size());
+ point.I.resize(caltype.usedPorts.size());
+ fill(point.L.begin(), point.L.end(), vector>(caltype.usedPorts.size(), 0.0));
+ fill(point.T.begin(), point.T.end(), vector>(caltype.usedPorts.size(), 1.0));
+ fill(point.I.begin(), point.I.end(), vector>(caltype.usedPorts.size(), 0.0));
+ return point;
+}
+
+Calibration::Point Calibration::computeOSL(double f)
+{
+ Point point = createInitializedPoint(f);
+
+ // Calculate SOL coefficients
+ for(unsigned int i=0;i(findMeasurement(CalibrationMeasurement::Base::Type::Short, p));
+ auto open = static_cast(findMeasurement(CalibrationMeasurement::Base::Type::Open, p));
+ auto s_m = _short->getMeasured(f);
+ auto o_m = open->getMeasured(f);
+ auto s_c = _short->getActual(f);
+ auto o_c = open->getActual(f);
+ complex l_c, l_m;
+ auto slidingMeasurements = findMeasurements(CalibrationMeasurement::Base::Type::SlidingLoad, p);
+ if(slidingMeasurements.size() >= 3) {
+ // use sliding load
+ vector> slidingMeasured;
+ for(auto m : slidingMeasurements) {
+ auto slidingLoad = static_cast(m);
+ auto value = slidingLoad->getMeasured(f);
+ if(isnan(abs(value))) {
+ throw runtime_error("missing sliding load measurement");
+ }
+ slidingMeasured.push_back(value);
+ }
+ // use center of measurement for ideal load measurement
+ l_m = Util::findCenterOfCircle(slidingMeasured);
+ // assume perfect sliding load
+ l_c = 0.0;
+ } else {
+ // use normal load standard
+ auto load = static_cast(findMeasurement(CalibrationMeasurement::Base::Type::Load, p));
+ l_c = load->getActual(f);
+ l_m = load->getMeasured(f);
+ }
+ auto denom = l_c * o_c * (o_m - l_m) + l_c * s_c * (l_m - s_m) + o_c * s_c * (s_m - o_m);
+ point.D[i] = (l_c * o_m * (s_m * (o_c - s_c) + l_m * s_c) - l_c * o_c * l_m * s_m + o_c * l_m * s_c * (s_m - o_m)) / denom;
+ point.S[i] = (l_c * (o_m - s_m) + o_c * (s_m - l_m) + s_c * (l_m - o_m)) / denom;
+ auto delta = (l_c * l_m * (o_m - s_m) + o_c * o_m * (s_m - l_m) + s_c * s_m * (l_m - o_m)) / denom;
+ point.R[i] = point.D[i] * point.S[i] - delta;
+ }
+ return point;
+}
+
+Calibration::Point Calibration::computeSOLT(double f)
+{
+ Point point = computeOSL(f);
+
+ // calculate forward match and transmission
+ for(unsigned int i=0;i(findMeasurement(CalibrationMeasurement::Base::Type::Through, p1, p2));
+ auto throughReverse = static_cast(findMeasurement(CalibrationMeasurement::Base::Type::Through, p2, p1));
+ complex S11, S21;
+ Sparam Sideal;
+ if(throughForward) {
+ S11 = throughForward->getMeasured(f).get(1,1);
+ S21 = throughForward->getMeasured(f).get(2,1);
+ Sideal = throughForward->getActual(f);
+ } else if(throughReverse) {
+ S11 = throughReverse->getMeasured(f).get(2,2);
+ S21 = throughReverse->getMeasured(f).get(1,2);
+ Sideal = throughReverse->getActual(f);
+ Sideal.swapPorts(1,2);
+ }
+ auto isoMeas = static_cast(findMeasurement(CalibrationMeasurement::Base::Type::Isolation));
+ auto isolation = complex(0.0,0.0);
+ if(isoMeas) {
+ isolation = isoMeas->getMeasured(f, p2, p1);
+ }
+ auto deltaS = Sideal.get(1,1)*Sideal.get(2,2) - Sideal.get(2,1) * Sideal.get(1,2);
+ point.L[i][j] = ((S11 - point.D[i])*(1.0 - point.S[i] * Sideal.get(1,1))-Sideal.get(1,1)*point.R[i])
+ / ((S11 - point.D[i])*(Sideal.get(2,2)-point.S[i]*deltaS)-deltaS*point.R[i]);
+ point.T[i][j] = (S21 - isolation)*(1.0 - point.S[i]*Sideal.get(1,1) - point.L[i][j]*Sideal.get(2,2) + point.S[i]*point.L[i][j]*deltaS) / Sideal.get(2,1);
+ point.I[i][j] = isolation;
+ }
+ }
+ return point;
+}
+
+Calibration::Point Calibration::computeSOLTwithoutRxMatch(double f) {
+ // This is very similar to SOLT but it assumes that receiver matching at the VNA is perfect.
+ // It can be used if the through calibration standard is very lossy which would result in
+ // very noisy values for the receiver match
+ auto p = computeSOLT(f);
+ for(auto &l : p.L) {
+ fill(l.begin(), l.end(), 0.0);
+ }
+ return p;
+}
+
+Calibration::Point Calibration::computeThroughNormalization(double f)
+{
+ Point point = createInitializedPoint(f);
+
+ // Calculate SOL coefficients
+ for(unsigned int i=0;i(findMeasurement(CalibrationMeasurement::Base::Type::Through, p1, p2));
+ auto throughReverse = static_cast(findMeasurement(CalibrationMeasurement::Base::Type::Through, p2, p1));
+ complex S21 = 0.0;
+ Sparam Sideal;
+ if(throughForward) {
+ S21 = throughForward->getMeasured(f).get(2,1);
+ Sideal = throughForward->getActual(f);
+ } else if(throughReverse) {
+ S21 = throughReverse->getMeasured(f).get(1,2);
+ Sideal = throughReverse->getActual(f);
+ Sideal.swapPorts(1,2);
+ }
+ point.L[i][j] = 0.0;
+ point.T[i][j] = S21 / Sideal.get(2,1);
+ point.I[i][j] = 0.0;
+ }
+ }
+ return point;
+}
+
+Calibration::Point Calibration::computeTRL(double freq)
+{
+ Point point = createInitializedPoint(freq);
+
+ // calculate forward match and transmission
+ for(unsigned int i=0;i(findMeasurement(CalibrationMeasurement::Base::Type::Reflect, p1));
+ auto S22_reflection = static_cast(findMeasurement(CalibrationMeasurement::Base::Type::Reflect, p2));
+ bool S11_short, S22_short;
+ {
+ auto S11_short_standard = dynamic_cast(S11_reflection->getStandard());
+ auto S11_open_standard = dynamic_cast(S11_reflection->getStandard());
+ auto S11_reflect_standard = dynamic_cast(S11_reflection->getStandard());
+ if(S11_short_standard) {
+ S11_short = true;
+ } else if(S11_open_standard) {
+ S11_short = false;
+ } else if(S11_reflect_standard) {
+ S11_short = S11_reflect_standard->getIsShort();
+ } else {
+ // invalid standard
+ throw runtime_error("Invalid standard defined for reflection measurement");
+ }
+ auto S22_short_standard = dynamic_cast(S22_reflection->getStandard());
+ auto S22_open_standard = dynamic_cast(S22_reflection->getStandard());
+ auto S22_reflect_standard = dynamic_cast(S22_reflection->getStandard());
+ if(S22_short_standard) {
+ S22_short = true;
+ } else if(S22_open_standard) {
+ S22_short = false;
+ } else if(S22_reflect_standard) {
+ S22_short = S22_reflect_standard->getIsShort();
+ } else {
+ // invalid standard
+ throw runtime_error("Invalid standard defined for reflection measurement");
+ }
+ }
+ bool reflectionIsNegative;
+ if(S11_short && S22_short) {
+ reflectionIsNegative = true;
+ } else if(!S11_short && !S22_short) {
+ reflectionIsNegative = false;
+ } else {
+ throw runtime_error("Reflection measurements must all use the same standard (either open or short)");
+ }
+ // grab through measurement
+ auto throughForward = static_cast(findMeasurement(CalibrationMeasurement::Base::Type::Through, p1, p2));
+ auto throughReverse = static_cast(findMeasurement(CalibrationMeasurement::Base::Type::Through, p2, p1));
+ Sparam Sthrough;
+ if(throughForward) {
+ Sthrough = throughForward->getMeasured(freq);
+ } else if(throughReverse) {
+ Sthrough = throughReverse->getMeasured(freq);
+ Sthrough.swapPorts(1,2);
+ }
+ // grab line measurement
+ auto forwardLines = findMeasurements(CalibrationMeasurement::Base::Type::Line, p1, p2);
+ auto reverseLines = findMeasurements(CalibrationMeasurement::Base::Type::Line, p2, p1);
+ // find the closest (geometric) match for the current frequency
+ double closestIdealFreqRatio = numeric_limits::max();
+ bool closestLineIsReversed = false;
+ CalibrationMeasurement::Line* closestLine = nullptr;
+ CalStandard::Line* closestStandard = nullptr;
+ for(int i=0;i<2;i++) {
+ auto list = i ? reverseLines : forwardLines;
+ for(auto l : list) {
+ auto line = static_cast(l);
+ auto standard = static_cast(line->getStandard());
+ double idealFreq = (standard->minFrequency() + standard->maxFrequency()) / 2;
+ double mismatch = idealFreq / freq;
+ if(mismatch < 0) {
+ mismatch = 1.0 / mismatch;
+ }
+ if(mismatch < closestIdealFreqRatio) {
+ closestIdealFreqRatio = mismatch;
+ closestLineIsReversed = i > 0;
+ closestLine = line;
+ closestStandard = standard;
+ }
+ }
+ }
+ if(!closestLine) {
+ throw runtime_error("Unable to find required line measurement");
+ }
+ if(freq < closestStandard->minFrequency() || freq > closestStandard->maxFrequency()) {
+ throw runtime_error("No line standard supports the required frequency ("+QString::number(freq).toStdString()+")");
+ }
+
+ Sparam Sline = closestLine->getMeasured(freq);
+ if(closestLineIsReversed) {
+ Sline.swapPorts(1,2);
+ }
+
+ // got all required measurements
+ // calculate TRL calibration
+ // variable names and formulas according to http://emlab.uiuc.edu/ece451/notes/new_TRL.pdf
+ // page 19
+ auto R_T = Tparam(Sthrough);
+ auto R_D = Tparam(Sline);
+ auto T = R_D*R_T.inverse();
+ complex a_over_c, b;
+ // page 21-22
+ Util::solveQuadratic(T.get(2,1), T.get(2,2) - T.get(1,1), -T.get(1,2), b, a_over_c);
+ // ensure correct root selection
+ // page 23
+ if(abs(b) >= abs(a_over_c)) {
+ swap(b, a_over_c);
+ }
+ // page 24
+ auto g = R_T.get(2,2);
+ auto d = R_T.get(1,1) / g;
+ auto e = R_T.get(1,2) / g;
+ auto f = R_T.get(2,1) / g;
+
+ // page 25
+ auto r22_rho22 = g * (1.0 - e / a_over_c) / (1.0 - b / a_over_c);
+ auto gamma = (f - d / a_over_c) / (1.0 - e / a_over_c);
+ auto beta_over_alpha = (e - b) / (d - b * f);
+ // page 26
+ auto alpha_a = (d - b * f) / (1.0 - e / a_over_c);
+ auto w1 = S11_reflection->getMeasured(freq);
+ auto w2 = S22_reflection->getMeasured(freq);
+ // page 28
+ auto a = sqrt((w1 - b) / (w2 + gamma) * (1.0 + w2 * beta_over_alpha) / (1.0 - w1 / a_over_c) * alpha_a);
+ // page 29, check sign of a
+ auto reflection = (w1 - b) / (a * (1.0 - w1 / a_over_c));
+ if((reflection.real() > 0 && reflectionIsNegative) || (reflection.real() < 0 && !reflectionIsNegative)) {
+ // wrong sign for a
+ a = -a;
+ }
+ // Revert back from error boxes with T parameters to S paramaters,
+ // page 17 + formulas for calculating S parameters from T parameters.
+ // Forward coefficients, normalize for S21 = 1.0 -> r22 = 1.0
+ auto r22 = complex(1.0);
+ auto rho22 = r22_rho22 / r22;
+ auto alpha = alpha_a / a;
+ auto beta = beta_over_alpha * alpha;
+ auto c = a / a_over_c;
+ auto Box_A = Tparam(r22 * a, r22 * b, r22 * c, r22);
+ auto Box_B = Tparam(rho22 * alpha, rho22 * beta, rho22 * gamma, rho22);
+ auto S_A = Sparam(Box_A);
+ point.D[i] = S_A.get(1,1);
+ point.R[i] = S_A.get(1,2);
+ point.S[i] = S_A.get(2,2);
+ auto S_B = Sparam(Box_B);
+ point.L[i][j] = S_B.get(1,1);
+ point.T[i][j] = S_B.get(2,1);
+ // no isolation measurement available
+ point.I[i][j] = 0.0;
+
+ // Reverse coefficients, will be handled in loop iteration where i=j and j=i
+ }
+ }
+ return point;
+}
+
+Calibration::CalType Calibration::getCaltype() const
+{
+ return caltype;
+}
+
+Calibration::InterpolationType Calibration::getInterpolation(double f_start, double f_stop, int npoints)
+{
+ lock_guard guard(access);
+ if(!points.size()) {
+ return InterpolationType::NoCalibration;
+ }
+ if(f_start < points.front().frequency || f_stop > points.back().frequency) {
+ return InterpolationType::Extrapolate;
+ }
+ // Either exact or interpolation, check individual frequencies
+ uint32_t f_step;
+ if(npoints > 1) {
+ f_step = (f_stop - f_start) / (npoints - 1);
+ } else {
+ f_step = f_stop - f_start;
+ }
+ uint64_t f = f_start;
+ do {
+ if(find_if(points.begin(), points.end(), [&f](const Point& p){
+ return abs(f - p.frequency) < 100;
+ }) == points.end()) {
+ return InterpolationType::Interpolate;
+ }
+ f += f_step;
+ } while(f <= f_stop && f_step > std::numeric_limits::epsilon());
+
+ // if we get here all frequency points were matched
+ if(points.front().frequency == f_start && points.back().frequency == f_stop) {
+ return InterpolationType::Unchanged;
+ } else {
+ return InterpolationType::Exact;
+ }
+}
+
+std::vector Calibration::getErrorTermTraces()
+{
+ lock_guard guard(access);
+ vector ret;
+ if(points.size() == 0) {
+ return ret;
+ }
+ for(unsigned int i=0;isetReflection(true);
+ tDir->setCalibration();
+ auto tSM = new Trace("SourceMatch_Port"+QString::number(p));
+ tSM->setReflection(true);
+ tSM->setCalibration();
+ auto tRT = new Trace("ReflectionTracking_Port"+QString::number(p));
+ tRT->setReflection(false);
+ tRT->setCalibration();
+ for(auto p : points) {
+ Trace::Data td;
+ td.x = p.frequency;
+ td.y = p.D[i];
+ tDir->addData(td, Trace::DataType::Frequency);
+ td.y = p.S[i];
+ tSM->addData(td, Trace::DataType::Frequency);
+ td.y = p.R[i];
+ tRT->addData(td, Trace::DataType::Frequency);
+ }
+ ret.push_back(tDir);
+ ret.push_back(tSM);
+ ret.push_back(tRT);
+ for(unsigned int j=0;jsetReflection(true);
+ tRM->setCalibration();
+ auto tTT = new Trace("TransmissionTracking_"+QString::number(p)+QString::number(p2));
+ tTT->setReflection(false);
+ tTT->setCalibration();
+ auto tTI = new Trace("TransmissionIsolation_"+QString::number(p)+QString::number(p2));
+ tTI->setReflection(false);
+ tTI->setCalibration();
+ for(auto p : points) {
+ Trace::Data td;
+ td.x = p.frequency;
+ td.y = p.L[i][j];
+ tRM->addData(td, Trace::DataType::Frequency);
+ td.y = p.T[i][j];
+ tTT->addData(td, Trace::DataType::Frequency);
+ td.y = p.I[i][j];
+ tTI->addData(td, Trace::DataType::Frequency);
+ }
+ ret.push_back(tRM);
+ ret.push_back(tTT);
+ ret.push_back(tTI);
+ }
+ }
+ return ret;
+}
+
+std::vector Calibration::getMeasurementTraces()
+{
+ lock_guard guard(access);
+ vector ret;
+ for(auto m : measurements) {
+ switch(m->getType()) {
+ case CalibrationMeasurement::Base::Type::Open:
+ case CalibrationMeasurement::Base::Type::Short:
+ case CalibrationMeasurement::Base::Type::Load:
+ case CalibrationMeasurement::Base::Type::SlidingLoad:
+ case CalibrationMeasurement::Base::Type::Reflect: {
+ auto onePort = static_cast(m);
+ auto t = new Trace(CalibrationMeasurement::Base::TypeToString(onePort->getType())+"_Port"+QString::number(onePort->getPort()));
+ t->setCalibration();
+ t->setReflection(true);
+ for(auto d : onePort->getPoints()) {
+ Trace::Data td;
+ td.x = d.frequency;
+ td.y = d.S;
+ t->addData(td, Trace::DataType::Frequency);
+ }
+ ret.push_back(t);
+ }
+ break;
+ case CalibrationMeasurement::Base::Type::Through:
+ case CalibrationMeasurement::Base::Type::Line: {
+ auto twoPort = static_cast(m);
+ auto ts11 = new Trace(CalibrationMeasurement::Base::TypeToString(twoPort->getType())+"_Port"+QString::number(twoPort->getPort1())+QString::number(twoPort->getPort2())+"_S11");
+ auto ts12 = new Trace(CalibrationMeasurement::Base::TypeToString(twoPort->getType())+"_Port"+QString::number(twoPort->getPort1())+QString::number(twoPort->getPort2())+"_S12");
+ auto ts21 = new Trace(CalibrationMeasurement::Base::TypeToString(twoPort->getType())+"_Port"+QString::number(twoPort->getPort1())+QString::number(twoPort->getPort2())+"_S21");
+ auto ts22 = new Trace(CalibrationMeasurement::Base::TypeToString(twoPort->getType())+"_Port"+QString::number(twoPort->getPort1())+QString::number(twoPort->getPort2())+"_S22");
+ ts11->setCalibration();
+ ts11->setReflection(true);
+ ts12->setCalibration();
+ ts12->setReflection(false);
+ ts21->setCalibration();
+ ts21->setReflection(false);
+ ts22->setCalibration();
+ ts22->setReflection(true);
+ for(auto d : twoPort->getPoints()) {
+ Trace::Data td;
+ td.x = d.frequency;
+ td.y = d.S.get(1,1);
+ ts11->addData(td, Trace::DataType::Frequency);
+ td.y = d.S.get(1,2);
+ ts12->addData(td, Trace::DataType::Frequency);
+ td.y = d.S.get(2,1);
+ ts21->addData(td, Trace::DataType::Frequency);
+ td.y = d.S.get(2,2);
+ ts22->addData(td, Trace::DataType::Frequency);
+ }
+ ret.push_back(ts11);
+ ret.push_back(ts12);
+ ret.push_back(ts21);
+ ret.push_back(ts22);
+ }
+ break;
+ case CalibrationMeasurement::Base::Type::Isolation: {
+ auto iso = static_cast(m);
+ int ports = iso->getPoints()[0].S.size();
+ // Create the traces
+ vector> traces;
+ traces.resize(ports);
+ for(int i=0;igetType())+"_S"+QString::number(i+1)+QString::number(j+1));
+ t->setCalibration();
+ t->setReflection(i==j);
+ traces[i].push_back(t);
+ // also add to main return vector
+ ret.push_back(t);
+ }
+ }
+ // Fill the traces
+ for(auto p : iso->getPoints()) {
+ Trace::Data td;
+ td.x = p.frequency;
+ for(unsigned int i=0;iaddData(td, Trace::DataType::Frequency);
+ }
+ }
+ }
+ }
+ break;
+ case CalibrationMeasurement::Base::Type::Last:
+ break;
+ }
+ }
+ return ret;
+}
+
+QString Calibration::getCurrentCalibrationFile()
+{
+ return currentCalFile;
+}
+
+double Calibration::getMinFreq()
+{
+ if(points.size() > 0) {
+ return points.front().frequency;
+ } else {
+ return numeric_limits::quiet_NaN();
+ }
+}
+
+double Calibration::getMaxFreq()
+{
+ if(points.size() > 0) {
+ return points.back().frequency;
+ } else {
+ return numeric_limits::quiet_NaN();
+ }
+}
+
+int Calibration::getNumPoints()
+{
+ return points.size();
+}
+
+QString Calibration::descriptiveCalName()
+{
+ if(points.size() == 0) {
+ return QString();
+ }
+ int precision = 3;
+ QString lo = Unit::ToString(points.front().frequency, "", " kMG", precision);
+ QString hi = Unit::ToString(points.back().frequency, "", " kMG", precision);
+ // due to rounding up 123.66M and 123.99M -> we get lo="124M" and hi="124M"
+ // so let's add some precision
+ if (lo == hi) {
+ // Only in case of 123.66M and 123.69M we would need 5 digits, but that kind of narrow cal. is very unlikely.
+ precision = 4;
+ lo = Unit::ToString(points.front().frequency, "", " kMG", precision);
+ hi = Unit::ToString(points.back().frequency, "", " kMG", precision);
+ }
+
+ QString tmp =
+ caltype.getShortString()
+ + "_"
+ + lo + "-" + hi
+ + "_"
+ + QString::number(this->points.size()) + "pt";
+ tmp = tmp.replace(" ", "_");
+ tmp = tmp.replace("[", "");
+ tmp = tmp.replace("]", "");
+ tmp = tmp.replace(".", "_");
+ tmp = tmp.replace(",", "_");
+ return tmp;
+}
+
+QString Calibration::getValidDevice() const
+{
+ return validDevice;
+}
+
+bool Calibration::validForDevice(QString serial) const
+{
+ if(validDevice.isEmpty()) {
+ // no device indicated, always assume that the calibration is valid
+ return true;
+ }
+ if(validDevice == serial) {
+ return true;
+ } else {
+ return false;
+ }
+}
+
+bool Calibration::hasDirectivity(unsigned int port)
+{
+ unsigned int index = std::find(caltype.usedPorts.begin(), caltype.usedPorts.end(), port) - caltype.usedPorts.begin();
+ if(points.size() == 0 || index >= caltype.usedPorts.size()) {
+ // no calibration or it does not contain this port
+ return false;
+ }
+ auto def = std::complex(0.0, 0.0);
+ for(const auto &p : points) {
+ if(p.D[index] != def) {
+ // at least one point does not match the default value -> we have a valid calibration for this
+ return true;
+ }
+ }
+ // all points still at default value
+ return false;
+}
+
+bool Calibration::hasReflectionTracking(unsigned int port)
+{
+ unsigned int index = std::find(caltype.usedPorts.begin(), caltype.usedPorts.end(), port) - caltype.usedPorts.begin();
+ if(points.size() == 0 || index >= caltype.usedPorts.size()) {
+ // no calibration or it does not contain this port
+ return false;
+ }
+ auto def = std::complex(1.0, 0.0);
+ for(const auto &p : points) {
+ if(p.R[index] != def) {
+ // at least one point does not match the default value -> we have a valid calibration for this
+ return true;
+ }
+ }
+ // all points still at default value
+ return false;
+}
+
+bool Calibration::hasSourceMatch(unsigned int port)
+{
+ unsigned int index = std::find(caltype.usedPorts.begin(), caltype.usedPorts.end(), port) - caltype.usedPorts.begin();
+ if(points.size() == 0 || index >= caltype.usedPorts.size()) {
+ // no calibration or it does not contain this port
+ return false;
+ }
+ auto def = std::complex(0.0, 0.0);
+ for(const auto &p : points) {
+ if(p.S[index] != def) {
+ // at least one point does not match the default value -> we have a valid calibration for this
+ return true;
+ }
+ }
+ // all points still at default value
+ return false;
+}
+
+bool Calibration::hasReceiverMatch(unsigned int sourcePort, unsigned int receivePort)
+{
+ unsigned int indexSrc = std::find(caltype.usedPorts.begin(), caltype.usedPorts.end(), sourcePort) - caltype.usedPorts.begin();
+ unsigned int indexRcv = std::find(caltype.usedPorts.begin(), caltype.usedPorts.end(), receivePort) - caltype.usedPorts.begin();
+ if(points.size() == 0 || indexSrc >= caltype.usedPorts.size() || indexRcv >= caltype.usedPorts.size()) {
+ // no calibration or it does not contain this port
+ return false;
+ }
+ auto def = std::complex(0.0, 0.0);
+ for(const auto &p : points) {
+ if(p.L[indexSrc][indexRcv] != def) {
+ // at least one point does not match the default value -> we have a valid calibration for this
+ return true;
+ }
+ }
+ // all points still at default value
+ return false;
+}
+
+bool Calibration::hasTransmissionTracking(unsigned int sourcePort, unsigned int receivePort)
+{
+ unsigned int indexSrc = std::find(caltype.usedPorts.begin(), caltype.usedPorts.end(), sourcePort) - caltype.usedPorts.begin();
+ unsigned int indexRcv = std::find(caltype.usedPorts.begin(), caltype.usedPorts.end(), receivePort) - caltype.usedPorts.begin();
+ if(points.size() == 0 || indexSrc >= caltype.usedPorts.size() || indexRcv >= caltype.usedPorts.size()) {
+ // no calibration or it does not contain this port
+ return false;
+ }
+ auto def = std::complex(1.0, 0.0);
+ for(const auto &p : points) {
+ if(p.T[indexSrc][indexRcv] != def) {
+ // at least one point does not match the default value -> we have a valid calibration for this
+ return true;
+ }
+ }
+ // all points still at default value
+ return false;
+}
+
+bool Calibration::hasIsolation(unsigned int sourcePort, unsigned int receivePort)
+{
+ unsigned int indexSrc = std::find(caltype.usedPorts.begin(), caltype.usedPorts.end(), sourcePort) - caltype.usedPorts.begin();
+ unsigned int indexRcv = std::find(caltype.usedPorts.begin(), caltype.usedPorts.end(), receivePort) - caltype.usedPorts.begin();
+ if(points.size() == 0 || indexSrc >= caltype.usedPorts.size() || indexRcv >= caltype.usedPorts.size()) {
+ // no calibration or it does not contain this port
+ return false;
+ }
+ auto def = std::complex(0.0, 0.0);
+ for(const auto &p : points) {
+ if(p.I[indexSrc][indexRcv] != def) {
+ // at least one point does not match the default value -> we have a valid calibration for this
+ return true;
+ }
+ }
+ // all points still at default value
+ return false;
+}
+
+bool Calibration::hasUnsavedChanges() const
+{
+ return unsavedChanges;
+}
+
+Calkit &Calibration::getKit()
+{
+ return kit;
+}
+
+nlohmann::json Calibration::toJSON()
+{
+ lock_guard guard(access);
+ nlohmann::json j;
+ j["format"] = 3;
+ nlohmann::json jmeasurements;
+ for(auto m : measurements) {
+ nlohmann::json jmeas;
+ jmeas["type"] = CalibrationMeasurement::Base::TypeToString(m->getType()).toStdString();
+ jmeas["data"] = m->toJSON();
+ jmeasurements.push_back(jmeas);
+ }
+ j["measurements"] = jmeasurements;
+ j["calkit"] = kit.toJSON();
+ j["type"] = TypeToString(caltype.type).toStdString();
+ nlohmann::json jports;
+ for(auto p : caltype.usedPorts) {
+ jports.push_back(p);
+ }
+ j["ports"] = jports;
+ j["version"] = qlibrevnaApp->applicationVersion().toStdString();
+ j["device"] = validDevice.toStdString();
+ return j;
+}
+
+void Calibration::fromJSON(nlohmann::json j)
+{
+ reset();
+ lock_guard guard(access);
+ if(j.contains("calkit")) {
+ kit.fromJSON(j["calkit"]);
+ }
+ unsigned int format = 0;
+ if(j.contains("format")) {
+ format = j["format"];
+ } else {
+ // no clear format indicated, attempt to guess from json content
+ if(j.contains("port1StandardMale")) {
+ format = 2;
+ } else if(j.contains("version")){
+ format = 3;
+ }
+ }
+ switch(format) {
+ case 3: {
+ if(j.contains("measurements")) {
+ for(auto jm : j["measurements"]) {
+ auto type = CalibrationMeasurement::Base::TypeFromString(QString::fromStdString(jm.value("type", "")));
+ auto m = newMeasurement(type);
+ if(m && jm.contains("data")) {
+ m->fromJSON(jm["data"]);
+ measurements.push_back(m);
+ }
+ }
+ }
+
+ CalType ct;
+ ct.type = TypeFromString(QString::fromStdString(j.value("type", "")));
+ if(j.contains("ports")) {
+ for(auto jp : j["ports"]) {
+ ct.usedPorts.push_back(jp);
+ }
+ }
+ if(ct.type != Type::None) {
+ compute(ct);
+ }
+ validDevice = QString::fromStdString(j.value("device", ""));
+ }
+ break;
+ case 2: {
+ // associated calkit should already be loaded
+ if(j.contains("measurements")) {
+ // grab measurements
+ for(auto j_m : j["measurements"]) {
+ if(!j_m.contains("name")) {
+ throw runtime_error("Measurement without name given");
+ }
+ CalibrationMeasurement::Base *m = nullptr;
+ auto name = QString::fromStdString(j_m["name"]);
+ if(name == "Port 1 Open") {
+ m = newMeasurement(CalibrationMeasurement::Base::Type::Open);
+ static_cast(m)->setPort(1);
+ } else if(name == "Port 1 Short") {
+ m = newMeasurement(CalibrationMeasurement::Base::Type::Short);
+ static_cast(m)->setPort(1);
+ } else if(name == "Port 1 Load") {
+ m = newMeasurement(CalibrationMeasurement::Base::Type::Load);
+ static_cast(m)->setPort(1);
+ } else if(name == "Port 2 Open") {
+ m = newMeasurement(CalibrationMeasurement::Base::Type::Open);
+ static_cast(m)->setPort(2);
+ } else if(name == "Port 2 Short") {
+ m = newMeasurement(CalibrationMeasurement::Base::Type::Short);
+ static_cast(m)->setPort(2);
+ } else if(name == "Port 2 Load") {
+ m = newMeasurement(CalibrationMeasurement::Base::Type::Load);
+ static_cast(m)->setPort(2);
+ } else if(name == "Through") {
+ m = newMeasurement(CalibrationMeasurement::Base::Type::Through);
+ static_cast(m)->setPort1(1);
+ static_cast(m)->setPort2(2);
+ } else if(name == "Isolation") {
+ m = newMeasurement(CalibrationMeasurement::Base::Type::Isolation);
+ } else if(name == "Line") {
+ m = newMeasurement(CalibrationMeasurement::Base::Type::Line);
+ static_cast(m)->setPort1(1);
+ static_cast(m)->setPort2(2);
+ }
+ if(!m) {
+ // unknown measurement name
+ throw runtime_error("Measurement name unknown: "+std::string(j_m["name"]));
+ }
+ // attempt to select the correct standard
+ bool p1male = j.value("port1StandardMale", true);
+ bool p2male = j.value("port2StandardMale", true);
+ bool throughZeroLength = j.value("throughZeroLength", true);
+
+ auto onePort = dynamic_cast(m);
+ if(onePort) {
+ bool male = onePort->getPort() == 1 ? p1male : p2male;
+ QString name = male ? "Default male standard" : "Default female standard";
+ for(auto s : m->supportedStandards()) {
+ if(s->getName() == name) {
+ m->setStandard(s);
+ break;
+ }
+ }
+ }
+ auto through = dynamic_cast(m);
+ if(through) {
+ if(throughZeroLength) {
+ // needs to create a zero length through standard in the calkit in addition to the already existing through standard
+ auto zerolength = new CalStandard::Through();
+ zerolength->setName("Zero length");
+ kit.addStandard(zerolength);
+ // use this standard
+ m->setStandard(zerolength);
+ }
+ }
+ if(!m->getStandard()) {
+ // failed to find specific standard, use the first available
+ m->setFirstSupportedStandard();
+ }
+ // extract points
+ if(!j_m.contains("points")) {
+ throw runtime_error("Measurement "+name.toStdString()+" does not contain any points");
+ }
+ for(auto j_p : j_m["points"]) {
+ DeviceDriver::VNAMeasurement p;
+ p.frequency = j_p.value("frequency", 0.0);
+ p.Z0 = 50.0;
+ p.measurements["S11"] = complex(j_p.value("S11_real", 0.0), j_p.value("S11_imag", 0.0));
+ p.measurements["S12"] = complex(j_p.value("S12_real", 0.0), j_p.value("S12_imag", 0.0));
+ p.measurements["S21"] = complex(j_p.value("S21_real", 0.0), j_p.value("S21_imag", 0.0));
+ p.measurements["S22"] = complex(j_p.value("S22_real", 0.0), j_p.value("S22_imag", 0.0));
+ m->addPoint(p);
+ }
+ measurements.push_back(m);
+ }
+ }
+ // got all measurements, construct calibration according to type
+ if(j.contains("type")) {
+ auto type = QString::fromStdString(j["type"]);
+ CalType ct;
+ ct.type = Calibration::Type::None;
+ if(type == "Port 1") {
+ ct.type = Calibration::Type::SOLT;
+ ct.usedPorts = {1};
+ } else if(type == "Port 2") {
+ ct.type = Calibration::Type::SOLT;
+ ct.usedPorts = {2};
+ } else if(type == "SOLT") {
+ ct.type = Calibration::Type::SOLT;
+ ct.usedPorts = {1,2};
+ } else if(type == "Normalize") {
+ ct.type = Calibration::Type::ThroughNormalization;
+ ct.usedPorts = {1,2};
+ } else if(type == "TRL") {
+ ct.type = Calibration::Type::TRL;
+ ct.usedPorts = {1,2};
+ }
+ if(ct.type != Type::None) {
+ compute(ct);
+ }
+ }
+ InformationBox::ShowMessage("Old calibration format", "The selected calibration file was saved in an old format. Please check the imported result "
+ "carefully and save the calibration to migrate to the new format");
+ }
+ break;
+ default:
+ InformationBox::ShowError("Failed to load calibration", "Unable to load calibration, unknown json format: "+QString::number(format));
+ break;
+ }
+}
+
+bool Calibration::toFile(QString filename)
+{
+ if(filename.isEmpty()) {
+ QString fn = descriptiveCalName();
+ filename = QFileDialog::getSaveFileName(nullptr, "Save calibration data", Preferences::getInstance().UISettings.Paths.cal + "/" + fn, "Calibration files (*.cal)", nullptr, Preferences::QFileDialogOptions());
+ if(filename.isEmpty()) {
+ // aborted selection
+ return false;
+ }
+ Preferences::getInstance().UISettings.Paths.cal = QFileInfo(filename).path();
+ }
+
+ if(filename.toLower().endsWith(".cal")) {
+ filename.chop(4);
+ }
+ auto calibration_file = filename + ".cal";
+ ofstream file;
+ file.open(calibration_file.toStdString());
+ file << setw(1) << toJSON();
+
+ this->currentCalFile = calibration_file; // if all ok, remember this
+
+ unsavedChanges = false;
+ return true;
+}
+
+bool Calibration::fromFile(QString filename)
+{
+ if(filename.isEmpty()) {
+ filename = QFileDialog::getOpenFileName(nullptr, "Load calibration data", Preferences::getInstance().UISettings.Paths.cal, "Calibration files (*.cal)", nullptr, Preferences::QFileDialogOptions());
+ if(filename.isEmpty()) {
+ // aborted selection
+ return false;
+ }
+ Preferences::getInstance().UISettings.Paths.cal = QFileInfo(filename).path();
+ }
+
+ // force correct file ending
+ if(filename.toLower().endsWith(".cal")) {
+ filename.chop(4);
+ filename += ".cal";
+ }
+
+ qDebug() << "Attempting to open calibration from file" << filename;
+
+ // attempt to load associated calibration kit first. It needs to be available when using the old calibration format. If the
+ // newer calibration format is used, the calibration kit is overwritten by the calibration file anyway
+ auto calkit_file = filename;
+ auto dotPos = calkit_file.lastIndexOf('.');
+ if(dotPos >= 0) {
+ calkit_file.truncate(dotPos);
+ }
+ calkit_file.append(".calkit");
+ qDebug() << "Associated calibration kit expected in" << calkit_file;
+ if(!kit.fromFile(calkit_file)) {
+ qDebug() << "Parsing of calibration kit failed while opening calibration file (ignore for calibration format >= 3)";
+ }
+
+ ifstream file;
+
+ file.open(filename.toStdString());
+ if(!file.good()) {
+ QString msg = "Unable to open file: "+filename;
+ InformationBox::ShowError("Error", msg);
+ qWarning() << msg;
+ return false;
+ }
+
+ try {
+ nlohmann::json j;
+ file >> j;
+ currentCalFile = filename; // if all ok, remember this
+ fromJSON(j);
+ } catch(exception &e) {
+ currentCalFile.clear();
+ InformationBox::ShowError("File parsing error", e.what());
+ qWarning() << "Calibration file parsing failed: " << e.what();
+ return false;
+ }
+
+ unsavedChanges = false;
+ return true;
+}
+
+std::vector Calibration::getAvailableCalibrations()
+{
+ unsigned int ports = DeviceDriver::getInfo(DeviceDriver::getActiveDriver()).Limits.VNA.ports;
+ vector ret;
+ for(auto t : getTypes()) {
+ CalType cal;
+ cal.type = t;
+ auto minPorts = minimumPorts(t);
+ for(unsigned int pnum = minPorts;pnum <= ports;pnum++) {
+ std::string bitmask(pnum, 1);
+ bitmask.resize(ports, 0);
+ // assemble selected ports and permute bitmask
+ do {
+ vector usedPorts;
+ for (unsigned int i = 0; i < ports; ++i) {
+ if (bitmask[i]) {
+ usedPorts.push_back(i+1);
+ }
+ }
+ cal.usedPorts = usedPorts;
+ ret.push_back(cal);
+ } while (std::prev_permutation(bitmask.begin(), bitmask.end()));
+ }
+ }
+ return ret;
+}
+
+std::vector Calibration::getTypes()
+{
+ // do not include SOLTwithoutRxMatch for now as it is not fully working
+ return {Type::OSL, Type::SOLT, Type::ThroughNormalization, Type::TRL};
+ // vector types;
+ // // Start at index 1, skip Type::None
+ // for(int i=1;i<(int) Type::Last;i++) {
+ // types.push_back((Type) i);
+ // }
+ // return types;
+}
+
+bool Calibration::canCompute(Calibration::CalType type, double *startFreq, double *stopFreq, int *points, bool *isLog)
+{
+ using RequiredMeasurements = struct {
+ CalibrationMeasurement::Base::Type type;
+ unsigned int port1, port2;
+ };
+ vector required;
+ switch(type.type) {
+ case Type::None:
+ return true; // Always possible to reset the calibration
+ case Type::SOLT:
+ case Type::SOLTwithoutRxMatch:
+ // through measurements between all ports
+ for(unsigned int i=1;i<=type.usedPorts.size();i++) {
+ for(unsigned int j=i+1;j<=type.usedPorts.size();j++) {
+ required.push_back({.type = CalibrationMeasurement::Base::Type::Through, .port1 = i, .port2 = j});
+ }
+ }
+ [[fallthrough]];
+ case Type::OSL:
+ // SOL measurements for every port
+ for(auto p : type.usedPorts) {
+ required.push_back({.type = CalibrationMeasurement::Base::Type::Short, .port1 = p, .port2 = 0});
+ required.push_back({.type = CalibrationMeasurement::Base::Type::Open, .port1 = p, .port2 = 0});
+ if(findMeasurements(CalibrationMeasurement::Base::Type::SlidingLoad, p).size() >= 3) {
+ // got enough sliding load measurements, use these
+ required.push_back({.type = CalibrationMeasurement::Base::Type::SlidingLoad, .port1 = p, .port2 = 0});
+ } else {
+ // not enough sliding load measurement, use normal load
+ required.push_back({.type = CalibrationMeasurement::Base::Type::Load, .port1 = p, .port2 = 0});
+ }
+ }
+ break;
+ case Type::ThroughNormalization:
+ // through measurements between all ports
+ for(unsigned int i=1;i<=type.usedPorts.size();i++) {
+ for(unsigned int j=i+1;j<=type.usedPorts.size();j++) {
+ required.push_back({.type = CalibrationMeasurement::Base::Type::Through, .port1 = i, .port2 = j});
+ }
+ }
+ break;
+ case Type::TRL:
+ // Reflect measurement for every port
+ for(auto p : type.usedPorts) {
+ required.push_back({.type = CalibrationMeasurement::Base::Type::Reflect, .port1 = p, .port2 = 0});
+ }
+ // through and line measurements between all ports
+ for(unsigned int i=1;i<=type.usedPorts.size();i++) {
+ for(unsigned int j=i+1;j<=type.usedPorts.size();j++) {
+ required.push_back({.type = CalibrationMeasurement::Base::Type::Through, .port1 = i, .port2 = j});
+ required.push_back({.type = CalibrationMeasurement::Base::Type::Line, .port1 = i, .port2 = j});
+ }
+ }
+ break;
+ case Type::Last:
+ // Invalid selection
+ return false;
+
+ }
+ if(required.size() > 0) {
+ vector foundMeasurements;
+ for(auto m : required) {
+ auto meas = findMeasurement(m.type, m.port1, m.port2);
+ if(!meas) {
+ // missing measurement
+ return false;
+ } else if (!meas->readyForCalculation()){
+ // measurement not ready (either not calkit standard definded or no measurements)
+ return false;
+ } else {
+ foundMeasurements.push_back(meas);
+ }
+ }
+ return hasFrequencyOverlap(foundMeasurements, startFreq, stopFreq, points, isLog);
+ }
+ return false;
+}
+
+bool Calibration::compute(Calibration::CalType type)
+{
+ lock_guard guard(access);
+ if(type.type == Type::None) {
+ deactivate();
+ return true;
+ }
+ double start, stop;
+ int numPoints;
+ bool isLog;
+ if(!canCompute(type, &start, &stop, &numPoints, &isLog)) {
+ return false;
+ }
+ caltype = type;
+ try {
+ points.clear();
+ for(int i=0;i m, const DeviceDriver::VNAMeasurement &data)
+{
+ for(auto meas : m) {
+ meas->addPoint(data);
+ }
+ unsavedChanges = true;
+ if(DeviceDriver::getActiveDriver()) {
+ validDevice = DeviceDriver::getActiveDriver()->getSerial();
+ }
+}
+
+void Calibration::clearMeasurements(std::set m)
+{
+ for(auto meas : m) {
+ meas->clearPoints();
+ }
+ unsavedChanges = true;
+}
+
+void Calibration::measurementsComplete()
+{
+ emit measurementsUpdated();
+}
+
+void Calibration::measurementsAbort()
+{
+ emit measurementsAborted();
+}
+
+void Calibration::deactivate()
+{
+ lock_guard guard(access);
+ points.clear();
+ caltype.type = Type::None;
+ caltype.usedPorts.clear();
+ unsavedChanges = true;
+ emit deactivated();
+}
+
+QString Calibration::DefaultMeasurementsToString(Calibration::DefaultMeasurements dm)
+{
+ switch(dm) {
+ case DefaultMeasurements::SOL1Port: return "1 Port SOL";
+ case DefaultMeasurements::SOLT2Port: return "2 Port SOLT";
+ case DefaultMeasurements::SOLT3Port: return "3 Port SOLT";
+ case DefaultMeasurements::SOLT4Port: return "4 Port SOLT";
+ case DefaultMeasurements::Last: return "Invalid";
+ }
+ return "";
+}
+
+void Calibration::createDefaultMeasurements(Calibration::DefaultMeasurements dm)
+{
+ lock_guard guard(access);
+ auto createSOL = [=](int port) {
+ auto open = new CalibrationMeasurement::Open(this);
+ open->setPort(port);
+ measurements.push_back(open);
+ auto _short = new CalibrationMeasurement::Short(this);
+ _short->setPort(port);
+ measurements.push_back(_short);
+ auto load = new CalibrationMeasurement::Load(this);
+ load->setPort(port);
+ measurements.push_back(load);
+ };
+ auto createThrough = [=](int port1, int port2) {
+ auto through = new CalibrationMeasurement::Through(this);
+ through->setPort1(port1);
+ through->setPort2(port2);
+ measurements.push_back(through);
+ };
+ switch(dm) {
+ case DefaultMeasurements::SOL1Port:
+ createSOL(1);
+ break;
+ case DefaultMeasurements::SOLT2Port:
+ createSOL(1);
+ createSOL(2);
+ createThrough(1, 2);
+ break;
+ case DefaultMeasurements::SOLT3Port:
+ createSOL(1);
+ createSOL(2);
+ createSOL(3);
+ createThrough(1, 2);
+ createThrough(1, 3);
+ createThrough(2, 3);
+ break;
+ case DefaultMeasurements::SOLT4Port:
+ createSOL(1);
+ createSOL(2);
+ createSOL(3);
+ createSOL(4);
+ createThrough(1, 2);
+ createThrough(1, 3);
+ createThrough(1, 4);
+ createThrough(2, 3);
+ createThrough(2, 4);
+ createThrough(3, 4);
+ break;
+ case DefaultMeasurements::Last:
+ break;
+ }
+}
+
+void Calibration::deleteMeasurements()
+{
+ lock_guard guard(access);
+ for(auto m : measurements) {
+ delete m;
+ }
+ measurements.clear();
+}
+
+bool Calibration::hasFrequencyOverlap(std::vector m, double *startFreq, double *stopFreq, int *points, bool *isLog)
+{
+ double minResolution = std::numeric_limits::max();
+ double minFreq = 0;
+ double maxFreq = std::numeric_limits::max();
+ unsigned int logCount = 0;
+ unsigned int linCount = 0;
+ for(auto meas : m) {
+ if(meas->numPoints() < 2) {
+ return false;
+ }
+ auto resolution = (meas->maxUsableFreq() - meas->minUsableFreq()) / (meas->numPoints() - 1);
+ if(meas->maxUsableFreq() < maxFreq) {
+ maxFreq = meas->maxUsableFreq();
+ }
+ if(meas->minUsableFreq() > minFreq) {
+ minFreq = meas->minUsableFreq();
+ }
+ if(resolution < minResolution) {
+ minResolution = resolution;
+ }
+ // check whether the frequency points are more linear or more logarithmic
+ double minDiff = std::numeric_limits::max();
+ double maxDiff = 0;
+ double minRatio = std::numeric_limits::max();
+ double maxRatio = 0;
+ for(unsigned int i=1;inumPoints();i++) {
+ double f_prev = meas->getPointFreq(i-1);
+ double f_next = meas->getPointFreq(i);
+ double diff = f_next - f_prev;
+ double ratio = f_next / f_prev;
+ if(diff < minDiff) {
+ minDiff = diff;
+ }
+ if(diff > maxDiff) {
+ maxDiff = diff;
+ }
+ if(ratio < minRatio) {
+ minRatio = ratio;
+ }
+ if(ratio > maxRatio) {
+ maxRatio = ratio;
+ }
+ }
+ double diffVariationNormalized = (maxDiff - minDiff) / maxDiff;
+ double ratioVariationNormalized = (maxRatio - minRatio) / maxRatio;
+ if(abs(diffVariationNormalized) < abs(ratioVariationNormalized)) {
+ // more linear
+ linCount++;
+ } else {
+ // more logarithmic
+ logCount++;
+ }
+ }
+ if(startFreq) {
+ *startFreq = minFreq;
+ }
+ if(stopFreq) {
+ *stopFreq = maxFreq;
+ }
+ if(points) {
+ *points = (maxFreq - minFreq) / minResolution + 1;
+ }
+ if(isLog) {
+ *isLog = logCount > linCount;
+ }
+ if(maxFreq > minFreq) {
+ return true;
+ } else {
+ return false;
+ }
+}
+
+std::vector Calibration::findMeasurements(CalibrationMeasurement::Base::Type type, int port1, int port2)
+{
+ vector ret;
+ for(auto m : measurements) {
+ if(m->getType() != type) {
+ continue;
+ }
+ auto onePort = dynamic_cast(m);
+ if(onePort) {
+ if(onePort->getPort() != port1) {
+ continue;
+ }
+ }
+ auto twoPort = dynamic_cast(m);
+ if(twoPort) {
+ if(twoPort->getPort1() != port1 || twoPort->getPort2() != port2) {
+ continue;
+ }
+ }
+ // if we get here, we have a match
+ ret.push_back(m);
+ }
+ return ret;
+}
+
+CalibrationMeasurement::Base *Calibration::findMeasurement(CalibrationMeasurement::Base::Type type, int port1, int port2)
+{
+ auto meas = findMeasurements(type, port1, port2);
+ if(meas.size() > 0) {
+ return meas[0];
+ } else {
+ return nullptr;
+ }
+}
+
+QString Calibration::CalType::getReadableDescription()
+{
+ QString ret = TypeToString(this->type);
+ if(usedPorts.size() == 1) {
+ ret += ", Port: "+QString::number(usedPorts[0]);
+ } else if(usedPorts.size() > 0) {
+ ret += ", Ports: [";
+ for(auto p : usedPorts) {
+ ret += QString::number(p)+",";
+ }
+ // remove the last trailing comma
+ ret.chop(1);
+ ret += "]";
+ }
+ return ret;
+}
+
+QString Calibration::CalType::getShortString()
+{
+ QString ret = TypeToString(this->type);
+ if(usedPorts.size() > 0) {
+ ret += "_";
+ }
+ for(auto p : usedPorts) {
+ ret += QString::number(p);
+ }
+ return ret;
+}
+
+Calibration::CalType Calibration::CalType::fromShortString(QString s)
+{
+ CalType ret;
+ auto list = s.split("_");
+ if(list.size() != 2) {
+ ret.type = Type::None;
+ } else {
+ ret.type = TypeFromString(list[0]);
+ for(auto c : list[1]) {
+ ret.usedPorts.push_back(QString(c).toInt());
+ }
+ }
+ return ret;
+}
+
+Calibration::Point Calibration::Point::interpolate(const Calibration::Point &to, double alpha)
+{
+ Point ret;
+ ret.frequency = frequency * (1.0-alpha) + to.frequency * alpha;
+ ret.D.resize(D.size(), 0.0);
+ for(unsigned int i=0;i
+
+class Calibration : public QObject, public Savable, public SCPINode
+{
+ Q_OBJECT
+
+ friend class LibreCALDialog;
+ friend class CalibrationTests;
+public:
+ Calibration();
+
+ enum class Type {
+ None,
+ OSL,
+ SOLT,
+ SOLTwithoutRxMatch,
+ ThroughNormalization,
+ TRL,
+ Last,
+ };
+ class CalType {
+ public:
+ Type type;
+ std::vector usedPorts; // port count starts at 1
+ QString getReadableDescription();
+ QString getShortString();
+
+ static CalType fromShortString(QString s);
+
+ friend bool operator==(const CalType &lhs, const CalType &rhs);
+ };
+
+ static QString TypeToString(Type type);
+ static Type TypeFromString(QString s);
+
+ // Applies calculated calibration coefficients to measurement data
+ void correctMeasurement(DeviceDriver::VNAMeasurement &d);
+ void correctTraces(std::map traceSet);
+
+ // Starts the calibration edit dialog, allowing the user to make/delete measurements
+ void edit(TraceModel *traceModel = nullptr);
+
+ Calkit& getKit();
+
+ virtual nlohmann::json toJSON() override;
+ virtual void fromJSON(nlohmann::json j) override;
+
+ bool toFile(QString filename = QString());
+ bool fromFile(QString filename = QString());
+
+ // Returns all possible calibration types/port permutations for the currently connected device.
+ // If no device is connected, a two-port device is assumed
+ static std::vector getAvailableCalibrations();
+
+ // Returns vector of all calibration types (without 'Last')
+ static std::vector getTypes();
+ // Checks whether all measurements for a specific calibration are available.
+ // If pointer to the frequency/points variables are given, the start/stop frequency and number of points the calibration will have after the calculation is stored there
+ bool canCompute(CalType type, double *startFreq = nullptr, double *stopFreq = nullptr, int *points = nullptr, bool *isLog = nullptr);
+ // Resets the calibration (deletes all measurements and calculated coefficients)
+ void reset();
+ // Returns the minimum number of ports for a given calibration type.
+ // E.g. the SOL(T) calibration can work with only one port, a through normalization requires at least two
+ static int minimumPorts(Type type);
+
+ // Adds a new measurement point (data) to all calibration measurements (m)
+ void addMeasurements(std::set m, const DeviceDriver::VNAMeasurement &data);
+ // Deletes all datapoints in the calibration measurements (m)
+ void clearMeasurements(std::set m);
+ CalType getCaltype() const;
+
+ enum class InterpolationType {
+ Unchanged, // Nothing has changed, settings and calibration points match
+ Exact, // Every frequency point in settings has an exact calibration point (but there are more calibration points outside of the sweep)
+ Interpolate, // Every point in the sweep can be interpolated between two calibration points
+ Extrapolate, // At least one point in sweep is outside of the calibration and has to be extrapolated
+ NoCalibration, // No calibration available
+ };
+
+ InterpolationType getInterpolation(double f_start, double f_stop, int npoints);
+
+ std::vector getErrorTermTraces();
+ std::vector