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f20ad2301b
fixed relative phases in Mach-Zander and ADC clocks. ADC clock delayed to move ADC sampling time far from the start of modulated period. Now there is 400 ns time reserve.
9974606734
partially solved issue with random modulator and ADC clock stopping at the end of ЛЧМ. Done: when we want to stop clocks -- enable IRQ on sloewr clock (TIM11). In IRQ switches TIM4, TIM11 to one-pulse mode, disables IRQ. When we starting these timers th next time -- we resets their counters, one-pulse mode disables.
0829fd0983
fixed modulation and ADC clocks initial phase to 0. (by TIM->CNT=0)
5756dfe749
configured ADC sync signals at fastest possible frequency: 1.75 MHz
61bb0c41db
configured external ADC sync and Mach-Zander modulation clocks at 2 and 1 MHz respectively