ChTheo/RadioPhotonic_PCB_software
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This commit is contained in:
Ayzen
2026-03-13 17:49:58 +03:00
parent db80907a0b
commit eafc328caa
89 changed files with 36315 additions and 34500 deletions
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334
build/stm32f7xx_hal_cortex.lst
View File

@ -1,4 +1,4 @@
ARM GAS /tmp/ccB9Q52u.s page 1
ARM GAS /tmp/ccjFay11.s page 1
1 .cpu cortex-m7
@ -58,7 +58,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
28:Drivers/CMSIS/Include/core_cm7.h **** #pragma clang system_header /* treat file as system include file */
29:Drivers/CMSIS/Include/core_cm7.h **** #endif
30:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 2
ARM GAS /tmp/ccjFay11.s page 2
31:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_GENERIC
@ -118,7 +118,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
85:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
86:Drivers/CMSIS/Include/core_cm7.h **** #endif
87:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 3
ARM GAS /tmp/ccjFay11.s page 3
88:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@ -178,7 +178,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
142:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
143:Drivers/CMSIS/Include/core_cm7.h **** #endif
144:Drivers/CMSIS/Include/core_cm7.h **** #else
ARM GAS /tmp/ccB9Q52u.s page 4
ARM GAS /tmp/ccjFay11.s page 4
145:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U
@ -238,7 +238,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
199:Drivers/CMSIS/Include/core_cm7.h **** #warning "__ICACHE_PRESENT not defined in device header file; using default!"
200:Drivers/CMSIS/Include/core_cm7.h **** #endif
201:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 5
ARM GAS /tmp/ccjFay11.s page 5
202:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DCACHE_PRESENT
@ -298,7 +298,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
256:Drivers/CMSIS/Include/core_cm7.h **** - Core MPU Register
257:Drivers/CMSIS/Include/core_cm7.h **** - Core FPU Register
258:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/
ARM GAS /tmp/ccB9Q52u.s page 6
ARM GAS /tmp/ccjFay11.s page 6
259:Drivers/CMSIS/Include/core_cm7.h **** /**
@ -358,7 +358,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
313:Drivers/CMSIS/Include/core_cm7.h **** typedef union
314:Drivers/CMSIS/Include/core_cm7.h **** {
315:Drivers/CMSIS/Include/core_cm7.h **** struct
ARM GAS /tmp/ccB9Q52u.s page 7
ARM GAS /tmp/ccjFay11.s page 7
316:Drivers/CMSIS/Include/core_cm7.h **** {
@ -418,7 +418,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
370:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Pos 24U /*!< xPSR
371:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR
372:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 8
ARM GAS /tmp/ccjFay11.s page 8
373:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Pos 16U /*!< xPSR
@ -478,7 +478,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
427:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register *
428:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[24U];
429:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register
ARM GAS /tmp/ccB9Q52u.s page 9
ARM GAS /tmp/ccjFay11.s page 9
430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[24U];
@ -538,7 +538,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
484:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[15U];
485:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0
486:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1
ARM GAS /tmp/ccB9Q52u.s page 10
ARM GAS /tmp/ccjFay11.s page 10
487:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2
@ -598,7 +598,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
541:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB
542:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB
543:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 11
ARM GAS /tmp/ccjFay11.s page 11
544:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB
@ -658,7 +658,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
598:Drivers/CMSIS/Include/core_cm7.h ****
599:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Pos 16U /*!< SCB
600:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB
ARM GAS /tmp/ccB9Q52u.s page 12
ARM GAS /tmp/ccjFay11.s page 12
601:Drivers/CMSIS/Include/core_cm7.h ****
@ -718,7 +718,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
655:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB
656:Drivers/CMSIS/Include/core_cm7.h ****
657:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB
ARM GAS /tmp/ccB9Q52u.s page 13
ARM GAS /tmp/ccjFay11.s page 13
658:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB
@ -778,7 +778,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
712:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB
713:Drivers/CMSIS/Include/core_cm7.h ****
714:Drivers/CMSIS/Include/core_cm7.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
ARM GAS /tmp/ccB9Q52u.s page 14
ARM GAS /tmp/ccjFay11.s page 14
715:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB
@ -838,7 +838,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
769:Drivers/CMSIS/Include/core_cm7.h ****
770:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Pos 24U /*!< SCB
771:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB
ARM GAS /tmp/ccB9Q52u.s page 15
ARM GAS /tmp/ccjFay11.s page 15
772:Drivers/CMSIS/Include/core_cm7.h ****
@ -898,7 +898,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
826:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Pos 5U /*!< SCB
827:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB
828:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 16
ARM GAS /tmp/ccjFay11.s page 16
829:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
@ -958,7 +958,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
883:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB
884:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB
885:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 17
ARM GAS /tmp/ccjFay11.s page 17
886:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB
@ -1018,7 +1018,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
940:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR:
941:Drivers/CMSIS/Include/core_cm7.h ****
942:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR:
ARM GAS /tmp/ccB9Q52u.s page 18
ARM GAS /tmp/ccjFay11.s page 18
943:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR:
@ -1078,7 +1078,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
997:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT
998:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT
999:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 19
ARM GAS /tmp/ccjFay11.s page 19
1000:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SysTick */
@ -1138,7 +1138,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1054:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM
1055:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM
1056:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 20
ARM GAS /tmp/ccjFay11.s page 20
1057:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM
@ -1198,7 +1198,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1111:Drivers/CMSIS/Include/core_cm7.h **** */
1112:Drivers/CMSIS/Include/core_cm7.h ****
1113:Drivers/CMSIS/Include/core_cm7.h **** /**
ARM GAS /tmp/ccB9Q52u.s page 21
ARM GAS /tmp/ccjFay11.s page 21
1114:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
@ -1258,7 +1258,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1168:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR
1169:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR
1170:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 22
ARM GAS /tmp/ccjFay11.s page 22
1171:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR
@ -1318,7 +1318,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1225:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Function Register Definitions */
1226:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN
1227:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN
ARM GAS /tmp/ccB9Q52u.s page 23
ARM GAS /tmp/ccjFay11.s page 23
1228:Drivers/CMSIS/Include/core_cm7.h ****
@ -1378,7 +1378,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[1U];
1283:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1284:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
ARM GAS /tmp/ccB9Q52u.s page 24
ARM GAS /tmp/ccjFay11.s page 24
1285:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
@ -1438,7 +1438,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1339:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF
1340:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF
1341:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 25
ARM GAS /tmp/ccjFay11.s page 25
1342:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF
@ -1498,7 +1498,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1396:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV
1397:Drivers/CMSIS/Include/core_cm7.h ****
1398:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV
ARM GAS /tmp/ccB9Q52u.s page 26
ARM GAS /tmp/ccjFay11.s page 26
1399:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV
@ -1558,7 +1558,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1453:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU
1454:Drivers/CMSIS/Include/core_cm7.h ****
1455:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Control Register Definitions */
ARM GAS /tmp/ccB9Q52u.s page 27
ARM GAS /tmp/ccjFay11.s page 27
1456:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU
@ -1618,7 +1618,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1510:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_MPU */
1511:Drivers/CMSIS/Include/core_cm7.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1512:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 28
ARM GAS /tmp/ccjFay11.s page 28
1513:Drivers/CMSIS/Include/core_cm7.h ****
@ -1678,7 +1678,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1567:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Default Status Control Register Definitions */
1568:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS
1569:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS
ARM GAS /tmp/ccB9Q52u.s page 29
ARM GAS /tmp/ccjFay11.s page 29
1570:Drivers/CMSIS/Include/core_cm7.h ****
@ -1738,7 +1738,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1624:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register
1625:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1626:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Core Debug Registers
ARM GAS /tmp/ccB9Q52u.s page 30
ARM GAS /tmp/ccjFay11.s page 30
1627:Drivers/CMSIS/Include/core_cm7.h **** @{
@ -1798,7 +1798,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1681:Drivers/CMSIS/Include/core_cm7.h ****
1682:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core
1683:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core
ARM GAS /tmp/ccB9Q52u.s page 31
ARM GAS /tmp/ccjFay11.s page 31
1684:Drivers/CMSIS/Include/core_cm7.h ****
@ -1858,7 +1858,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1738:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1739:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted value.
1740:Drivers/CMSIS/Include/core_cm7.h **** */
ARM GAS /tmp/ccB9Q52u.s page 32
ARM GAS /tmp/ccjFay11.s page 32
1741:Drivers/CMSIS/Include/core_cm7.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
@ -1918,7 +1918,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1795:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Functions
1796:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Functions
1797:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Functions
ARM GAS /tmp/ccB9Q52u.s page 33
ARM GAS /tmp/ccjFay11.s page 33
1798:Drivers/CMSIS/Include/core_cm7.h **** - Core Register Access Functions
@ -1978,7 +1978,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1852:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu
1853:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu
1854:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 34
ARM GAS /tmp/ccjFay11.s page 34
1855:Drivers/CMSIS/Include/core_cm7.h ****
@ -2038,7 +2038,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1909:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt is not enabled.
1910:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt is enabled.
1911:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative.
ARM GAS /tmp/ccB9Q52u.s page 35
ARM GAS /tmp/ccjFay11.s page 35
1912:Drivers/CMSIS/Include/core_cm7.h **** */
@ -2098,7 +2098,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4
ARM GAS /tmp/ccB9Q52u.s page 36
ARM GAS /tmp/ccjFay11.s page 36
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018
@ -2158,7 +2158,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
ARM GAS /tmp/ccB9Q52u.s page 37
ARM GAS /tmp/ccjFay11.s page 37
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
@ -2218,7 +2218,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
116:Drivers/CMSIS/Include/cmsis_gcc.h ****
117:Drivers/CMSIS/Include/cmsis_gcc.h ****
118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
ARM GAS /tmp/ccB9Q52u.s page 38
ARM GAS /tmp/ccjFay11.s page 38
119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
@ -2278,7 +2278,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
174:Drivers/CMSIS/Include/cmsis_gcc.h ****
175:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccB9Q52u.s page 39
ARM GAS /tmp/ccjFay11.s page 39
176:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
@ -2338,7 +2338,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register.
231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value
232:Drivers/CMSIS/Include/cmsis_gcc.h **** */
ARM GAS /tmp/ccB9Q52u.s page 40
ARM GAS /tmp/ccjFay11.s page 40
233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
@ -2398,7 +2398,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
288:Drivers/CMSIS/Include/cmsis_gcc.h **** */
289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
ARM GAS /tmp/ccB9Q52u.s page 41
ARM GAS /tmp/ccjFay11.s page 41
290:Drivers/CMSIS/Include/cmsis_gcc.h **** {
@ -2458,7 +2458,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
344:Drivers/CMSIS/Include/cmsis_gcc.h **** {
345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
346:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS /tmp/ccB9Q52u.s page 42
ARM GAS /tmp/ccjFay11.s page 42
347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
@ -2518,7 +2518,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result);
403:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS /tmp/ccB9Q52u.s page 43
ARM GAS /tmp/ccjFay11.s page 43
404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
@ -2578,7 +2578,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register.
459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value
460:Drivers/CMSIS/Include/cmsis_gcc.h **** */
ARM GAS /tmp/ccB9Q52u.s page 44
ARM GAS /tmp/ccjFay11.s page 44
461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
@ -2638,7 +2638,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
515:Drivers/CMSIS/Include/cmsis_gcc.h **** */
516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
517:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS /tmp/ccB9Q52u.s page 45
ARM GAS /tmp/ccjFay11.s page 45
518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
@ -2698,7 +2698,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
572:Drivers/CMSIS/Include/cmsis_gcc.h **** }
573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
574:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccB9Q52u.s page 46
ARM GAS /tmp/ccjFay11.s page 46
575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
@ -2758,7 +2758,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit
630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure
ARM GAS /tmp/ccB9Q52u.s page 47
ARM GAS /tmp/ccjFay11.s page 47
632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode.
@ -2818,7 +2818,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result;
687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) );
688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result;
ARM GAS /tmp/ccB9Q52u.s page 48
ARM GAS /tmp/ccjFay11.s page 48
689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
@ -2878,7 +2878,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set
745:Drivers/CMSIS/Include/cmsis_gcc.h **** */
ARM GAS /tmp/ccB9Q52u.s page 49
ARM GAS /tmp/ccjFay11.s page 49
746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
@ -2938,7 +2938,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr);
801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
ARM GAS /tmp/ccB9Q52u.s page 50
ARM GAS /tmp/ccjFay11.s page 50
803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
@ -2998,7 +2998,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev")
858:Drivers/CMSIS/Include/cmsis_gcc.h ****
859:Drivers/CMSIS/Include/cmsis_gcc.h ****
ARM GAS /tmp/ccB9Q52u.s page 51
ARM GAS /tmp/ccjFay11.s page 51
860:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
@ -3058,7 +3058,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
85 .align 2
86 .L3:
87 0020 00E100E0 .word -536813312
ARM GAS /tmp/ccB9Q52u.s page 52
ARM GAS /tmp/ccjFay11.s page 52
88 .cfi_endproc
@ -3118,7 +3118,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1985:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1986:Drivers/CMSIS/Include/core_cm7.h **** {
1987:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0)
ARM GAS /tmp/ccB9Q52u.s page 53
ARM GAS /tmp/ccjFay11.s page 53
1988:Drivers/CMSIS/Include/core_cm7.h **** {
@ -3178,7 +3178,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
113 .LVL3:
114 .loc 2 2028 49 view .LVU22
115 0006 C9B2 uxtb r1, r1
ARM GAS /tmp/ccB9Q52u.s page 54
ARM GAS /tmp/ccjFay11.s page 54
116 .loc 2 2028 47 view .LVU23
@ -3238,7 +3238,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
153 .loc 2 2047 1 is_stmt 1 view -0
154 .cfi_startproc
155 @ args = 0, pretend = 0, frame = 0
ARM GAS /tmp/ccB9Q52u.s page 55
ARM GAS /tmp/ccjFay11.s page 55
156 @ frame_needed = 0, uses_anonymous_args = 0
@ -3298,7 +3298,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
2061:Drivers/CMSIS/Include/core_cm7.h **** \brief Encode Priority
2062:Drivers/CMSIS/Include/core_cm7.h **** \details Encodes the priority for an interrupt with the given priority group,
2063:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value, and subpriority value.
ARM GAS /tmp/ccB9Q52u.s page 56
ARM GAS /tmp/ccjFay11.s page 56
2064:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available
@ -3358,7 +3358,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
235 0020 0EFA0CF0 lsl r0, lr, ip
236 .LVL13:
237 .loc 2 2081 30 view .LVU57
ARM GAS /tmp/ccB9Q52u.s page 57
ARM GAS /tmp/ccjFay11.s page 57
238 0024 21EA0001 bic r1, r1, r0
@ -3418,7 +3418,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
275 .cfi_offset 14, -4
2100:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used
276 .loc 2 2100 3 is_stmt 1 view .LVU64
ARM GAS /tmp/ccB9Q52u.s page 58
ARM GAS /tmp/ccjFay11.s page 58
277 .loc 2 2100 12 is_stmt 0 view .LVU65
@ -3478,7 +3478,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
322 .L21:
2105:Drivers/CMSIS/Include/core_cm7.h ****
323 .loc 2 2105 109 discriminator 2 view .LVU84
ARM GAS /tmp/ccB9Q52u.s page 59
ARM GAS /tmp/ccjFay11.s page 59
324 003a 0021 movs r1, #0
@ -3538,7 +3538,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
340 .cfi_startproc
341 @ Volatile: function does not return.
342 @ args = 0, pretend = 0, frame = 0
ARM GAS /tmp/ccB9Q52u.s page 60
ARM GAS /tmp/ccjFay11.s page 60
343 @ frame_needed = 0, uses_anonymous_args = 0
@ -3598,7 +3598,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
385 .loc 2 2156 3 view .LVU98
2157:Drivers/CMSIS/Include/core_cm7.h **** {
2158:Drivers/CMSIS/Include/core_cm7.h **** __NOP();
ARM GAS /tmp/ccB9Q52u.s page 61
ARM GAS /tmp/ccjFay11.s page 61
386 .loc 2 2158 5 discriminator 1 view .LVU99
@ -3658,7 +3658,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** The pending IRQ priority will be managed only by the sub priority.
31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
ARM GAS /tmp/ccB9Q52u.s page 62
ARM GAS /tmp/ccjFay11.s page 62
32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** -@- IRQ priority order (sorted by highest to lowest priority):
@ -3718,7 +3718,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */
87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX
ARM GAS /tmp/ccB9Q52u.s page 63
ARM GAS /tmp/ccjFay11.s page 63
89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief CORTEX HAL module driver
@ -3778,7 +3778,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
413 .loc 1 143 1 view -0
414 .cfi_startproc
ARM GAS /tmp/ccB9Q52u.s page 64
ARM GAS /tmp/ccjFay11.s page 64
415 @ args = 0, pretend = 0, frame = 0
@ -3838,7 +3838,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
451 .LVL32:
1875:Drivers/CMSIS/Include/core_cm7.h **** }
452 .loc 2 1875 3 is_stmt 1 view .LVU117
ARM GAS /tmp/ccB9Q52u.s page 65
ARM GAS /tmp/ccjFay11.s page 65
1875:Drivers/CMSIS/Include/core_cm7.h **** }
@ -3898,7 +3898,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** uint32_t prioritygroup = 0x00;
490 .loc 1 166 3 is_stmt 1 view .LVU123
491 .LVL35:
ARM GAS /tmp/ccB9Q52u.s page 66
ARM GAS /tmp/ccjFay11.s page 66
167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
@ -3958,7 +3958,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
534 .thumb
535 .thumb_func
537 HAL_NVIC_EnableIRQ:
ARM GAS /tmp/ccB9Q52u.s page 67
ARM GAS /tmp/ccjFay11.s page 67
538 .LVL41:
@ -4018,7 +4018,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
566 000e 024A ldr r2, .L36
567 0010 42F82030 str r3, [r2, r0, lsl #2]
568 .LVL43:
ARM GAS /tmp/ccB9Q52u.s page 68
ARM GAS /tmp/ccjFay11.s page 68
569 .L34:
@ -4078,7 +4078,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
607 0006 08BD pop {r3, pc}
608 .cfi_endproc
609 .LFE144:
ARM GAS /tmp/ccB9Q52u.s page 69
ARM GAS /tmp/ccjFay11.s page 69
611 .section .text.HAL_NVIC_SystemReset,"ax",%progbits
@ -4138,7 +4138,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
648 @ args = 0, pretend = 0, frame = 0
649 @ frame_needed = 0, uses_anonymous_args = 0
650 @ link register save eliminated.
ARM GAS /tmp/ccB9Q52u.s page 70
ARM GAS /tmp/ccjFay11.s page 70
230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** return SysTick_Config(TicksNumb);
@ -4198,7 +4198,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
2209:Drivers/CMSIS/Include/core_cm7.h ****
2210:Drivers/CMSIS/Include/core_cm7.h ****
2211:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 71
ARM GAS /tmp/ccjFay11.s page 71
2212:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## Cache functions #################################### */
@ -4258,7 +4258,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
2266:Drivers/CMSIS/Include/core_cm7.h **** {
2267:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
2268:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
ARM GAS /tmp/ccB9Q52u.s page 72
ARM GAS /tmp/ccjFay11.s page 72
2269:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
@ -4318,7 +4318,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
2323:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets;
2324:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways;
2325:Drivers/CMSIS/Include/core_cm7.h ****
ARM GAS /tmp/ccB9Q52u.s page 73
ARM GAS /tmp/ccjFay11.s page 73
2326:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
@ -4378,7 +4378,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
2380:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U);
2381:Drivers/CMSIS/Include/core_cm7.h ****
2382:Drivers/CMSIS/Include/core_cm7.h **** __DSB();
ARM GAS /tmp/ccB9Q52u.s page 74
ARM GAS /tmp/ccjFay11.s page 74
2383:Drivers/CMSIS/Include/core_cm7.h **** __ISB();
@ -4438,7 +4438,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
2437:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR;
2438:Drivers/CMSIS/Include/core_cm7.h ****
2439:Drivers/CMSIS/Include/core_cm7.h **** /* clean & invalidate D-Cache */
ARM GAS /tmp/ccB9Q52u.s page 75
ARM GAS /tmp/ccjFay11.s page 75
2440:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr));
@ -4498,7 +4498,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
2494:Drivers/CMSIS/Include/core_cm7.h **** int32_t op_size = dsize;
2495:Drivers/CMSIS/Include/core_cm7.h **** uint32_t op_addr = (uint32_t) addr;
2496:Drivers/CMSIS/Include/core_cm7.h **** int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (
ARM GAS /tmp/ccB9Q52u.s page 76
ARM GAS /tmp/ccjFay11.s page 76
2497:Drivers/CMSIS/Include/core_cm7.h ****
@ -4558,7 +4558,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
2551:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2552:Drivers/CMSIS/Include/core_cm7.h ****
2553:Drivers/CMSIS/Include/core_cm7.h **** /**
ARM GAS /tmp/ccB9Q52u.s page 77
ARM GAS /tmp/ccjFay11.s page 77
2554:Drivers/CMSIS/Include/core_cm7.h **** \brief System Tick Configuration
@ -4618,7 +4618,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
683 .loc 2 2573 3 is_stmt 1 view .LVU172
684 .loc 2 2573 18 is_stmt 0 view .LVU173
685 0016 0020 movs r0, #0
ARM GAS /tmp/ccB9Q52u.s page 78
ARM GAS /tmp/ccjFay11.s page 78
686 .LVL51:
@ -4678,7 +4678,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** @endverbatim
ARM GAS /tmp/ccB9Q52u.s page 79
ARM GAS /tmp/ccjFay11.s page 79
249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @{
@ -4738,7 +4738,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** MPU->CTRL = 0;
747 .loc 1 266 3 is_stmt 1 view .LVU189
748 .loc 1 266 13 is_stmt 0 view .LVU190
ARM GAS /tmp/ccB9Q52u.s page 80
ARM GAS /tmp/ccjFay11.s page 80
749 000e 0022 movs r2, #0
@ -4798,7 +4798,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
785 .loc 1 286 14 view .LVU198
786 000c 42F48032 orr r2, r2, #65536
787 0010 5A62 str r2, [r3, #36]
ARM GAS /tmp/ccB9Q52u.s page 81
ARM GAS /tmp/ccjFay11.s page 81
287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
@ -4858,7 +4858,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Enables the MPU Region.
ARM GAS /tmp/ccB9Q52u.s page 82
ARM GAS /tmp/ccjFay11.s page 82
295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None
@ -4918,7 +4918,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
871 @ frame_needed = 0, uses_anonymous_args = 0
872 @ link register save eliminated.
315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */
ARM GAS /tmp/ccB9Q52u.s page 83
ARM GAS /tmp/ccjFay11.s page 83
316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
@ -4978,7 +4978,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
908 .loc 1 336 3 view .LVU221
337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
909 .loc 1 337 3 view .LVU222
ARM GAS /tmp/ccB9Q52u.s page 84
ARM GAS /tmp/ccjFay11.s page 84
338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
@ -5038,7 +5038,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
944 .loc 1 356 34 view .LVU243
945 002a 417B ldrb r1, [r0, #13] @ zero_extendqisi2
ARM GAS /tmp/ccB9Q52u.s page 85
ARM GAS /tmp/ccjFay11.s page 85
355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
@ -5098,7 +5098,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
ARM GAS /tmp/ccB9Q52u.s page 86
ARM GAS /tmp/ccjFay11.s page 86
367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
@ -5158,7 +5158,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * 3 bits for subpriority
386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
ARM GAS /tmp/ccB9Q52u.s page 87
ARM GAS /tmp/ccjFay11.s page 87
387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * 2 bits for subpriority
@ -5218,7 +5218,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1064 .LFB154:
403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c ****
404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /**
ARM GAS /tmp/ccB9Q52u.s page 88
ARM GAS /tmp/ccjFay11.s page 88
405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt.
@ -5278,7 +5278,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1096 .loc 2 1974 43 view .LVU282
1097 .LBE65:
1098 .LBE64:
ARM GAS /tmp/ccB9Q52u.s page 89
ARM GAS /tmp/ccjFay11.s page 89
418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** }
@ -5338,7 +5338,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1133 0002 0BDB blt .L73
1955:Drivers/CMSIS/Include/core_cm7.h **** }
1134 .loc 2 1955 5 is_stmt 1 view .LVU291
ARM GAS /tmp/ccB9Q52u.s page 90
ARM GAS /tmp/ccjFay11.s page 90
1955:Drivers/CMSIS/Include/core_cm7.h **** }
@ -5398,7 +5398,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
1175 .loc 1 446 1 is_stmt 1 view -0
ARM GAS /tmp/ccB9Q52u.s page 91
ARM GAS /tmp/ccjFay11.s page 91
1176 .cfi_startproc
@ -5458,7 +5458,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1214 0018 00E100E0 .word -536813312
1215 .cfi_endproc
1216 .LFE156:
ARM GAS /tmp/ccB9Q52u.s page 92
ARM GAS /tmp/ccjFay11.s page 92
1218 .section .text.HAL_NVIC_GetActive,"ax",%progbits
@ -5518,7 +5518,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1250 000a 52F82330 ldr r3, [r2, r3, lsl #2]
2006:Drivers/CMSIS/Include/core_cm7.h **** }
1251 .loc 2 2006 91 view .LVU324
ARM GAS /tmp/ccB9Q52u.s page 93
ARM GAS /tmp/ccjFay11.s page 93
1252 000e 00F01F00 and r0, r0, #31
@ -5578,7 +5578,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1290 .loc 1 482 3 view .LVU331
483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
1291 .loc 1 483 3 view .LVU332
ARM GAS /tmp/ccB9Q52u.s page 94
ARM GAS /tmp/ccjFay11.s page 94
1292 .loc 1 483 6 is_stmt 0 view .LVU333
@ -5638,7 +5638,7 @@ ARM GAS /tmp/ccB9Q52u.s page 1
504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None
505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */
506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void)
ARM GAS /tmp/ccB9Q52u.s page 95
ARM GAS /tmp/ccjFay11.s page 95
507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** {
@ -5687,83 +5687,83 @@ ARM GAS /tmp/ccB9Q52u.s page 1
1363 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h"
1364 .file 5 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h"
1365 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h"
ARM GAS /tmp/ccB9Q52u.s page 96
ARM GAS /tmp/ccjFay11.s page 96
DEFINED SYMBOLS
*ABS*:00000000 stm32f7xx_hal_cortex.c
/tmp/ccB9Q52u.s:20 .text.__NVIC_DisableIRQ:00000000 $t
/tmp/ccB9Q52u.s:25 .text.__NVIC_DisableIRQ:00000000 __NVIC_DisableIRQ
/tmp/ccB9Q52u.s:87 .text.__NVIC_DisableIRQ:00000020 $d
/tmp/ccB9Q52u.s:92 .text.__NVIC_SetPriority:00000000 $t
/tmp/ccB9Q52u.s:97 .text.__NVIC_SetPriority:00000000 __NVIC_SetPriority
/tmp/ccB9Q52u.s:139 .text.__NVIC_SetPriority:0000001c $d
/tmp/ccB9Q52u.s:145 .text.__NVIC_GetPriority:00000000 $t
/tmp/ccB9Q52u.s:150 .text.__NVIC_GetPriority:00000000 __NVIC_GetPriority
/tmp/ccB9Q52u.s:185 .text.__NVIC_GetPriority:00000018 $d
/tmp/ccB9Q52u.s:191 .text.NVIC_EncodePriority:00000000 $t
/tmp/ccB9Q52u.s:196 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority
/tmp/ccB9Q52u.s:258 .text.NVIC_DecodePriority:00000000 $t
/tmp/ccB9Q52u.s:263 .text.NVIC_DecodePriority:00000000 NVIC_DecodePriority
/tmp/ccB9Q52u.s:332 .text.__NVIC_SystemReset:00000000 $t
/tmp/ccB9Q52u.s:337 .text.__NVIC_SystemReset:00000000 __NVIC_SystemReset
/tmp/ccB9Q52u.s:398 .text.__NVIC_SystemReset:0000001c $d
/tmp/ccB9Q52u.s:404 .text.HAL_NVIC_SetPriorityGrouping:00000000 $t
/tmp/ccB9Q52u.s:410 .text.HAL_NVIC_SetPriorityGrouping:00000000 HAL_NVIC_SetPriorityGrouping
/tmp/ccB9Q52u.s:464 .text.HAL_NVIC_SetPriorityGrouping:0000001c $d
/tmp/ccB9Q52u.s:470 .text.HAL_NVIC_SetPriority:00000000 $t
/tmp/ccB9Q52u.s:476 .text.HAL_NVIC_SetPriority:00000000 HAL_NVIC_SetPriority
/tmp/ccB9Q52u.s:526 .text.HAL_NVIC_SetPriority:0000001c $d
/tmp/ccB9Q52u.s:531 .text.HAL_NVIC_EnableIRQ:00000000 $t
/tmp/ccB9Q52u.s:537 .text.HAL_NVIC_EnableIRQ:00000000 HAL_NVIC_EnableIRQ
/tmp/ccB9Q52u.s:578 .text.HAL_NVIC_EnableIRQ:00000018 $d
/tmp/ccB9Q52u.s:583 .text.HAL_NVIC_DisableIRQ:00000000 $t
/tmp/ccB9Q52u.s:589 .text.HAL_NVIC_DisableIRQ:00000000 HAL_NVIC_DisableIRQ
/tmp/ccB9Q52u.s:612 .text.HAL_NVIC_SystemReset:00000000 $t
/tmp/ccB9Q52u.s:618 .text.HAL_NVIC_SystemReset:00000000 HAL_NVIC_SystemReset
/tmp/ccB9Q52u.s:637 .text.HAL_SYSTICK_Config:00000000 $t
/tmp/ccB9Q52u.s:643 .text.HAL_SYSTICK_Config:00000000 HAL_SYSTICK_Config
/tmp/ccB9Q52u.s:708 .text.HAL_SYSTICK_Config:00000024 $d
/tmp/ccB9Q52u.s:713 .text.HAL_MPU_Disable:00000000 $t
/tmp/ccB9Q52u.s:719 .text.HAL_MPU_Disable:00000000 HAL_MPU_Disable
/tmp/ccB9Q52u.s:756 .text.HAL_MPU_Disable:00000018 $d
/tmp/ccB9Q52u.s:761 .text.HAL_MPU_Enable:00000000 $t
/tmp/ccB9Q52u.s:767 .text.HAL_MPU_Enable:00000000 HAL_MPU_Enable
/tmp/ccB9Q52u.s:821 .text.HAL_MPU_Enable:0000001c $d
/tmp/ccB9Q52u.s:826 .text.HAL_MPU_EnableRegion:00000000 $t
/tmp/ccB9Q52u.s:832 .text.HAL_MPU_EnableRegion:00000000 HAL_MPU_EnableRegion
/tmp/ccB9Q52u.s:854 .text.HAL_MPU_EnableRegion:00000014 $d
/tmp/ccB9Q52u.s:859 .text.HAL_MPU_DisableRegion:00000000 $t
/tmp/ccB9Q52u.s:865 .text.HAL_MPU_DisableRegion:00000000 HAL_MPU_DisableRegion
/tmp/ccB9Q52u.s:887 .text.HAL_MPU_DisableRegion:00000014 $d
/tmp/ccB9Q52u.s:892 .text.HAL_MPU_ConfigRegion:00000000 $t
/tmp/ccB9Q52u.s:898 .text.HAL_MPU_ConfigRegion:00000000 HAL_MPU_ConfigRegion
/tmp/ccB9Q52u.s:975 .text.HAL_MPU_ConfigRegion:00000054 $d
/tmp/ccB9Q52u.s:980 .text.HAL_NVIC_GetPriorityGrouping:00000000 $t
/tmp/ccB9Q52u.s:986 .text.HAL_NVIC_GetPriorityGrouping:00000000 HAL_NVIC_GetPriorityGrouping
/tmp/ccB9Q52u.s:1010 .text.HAL_NVIC_GetPriorityGrouping:0000000c $d
/tmp/ccB9Q52u.s:1015 .text.HAL_NVIC_GetPriority:00000000 $t
/tmp/ccB9Q52u.s:1021 .text.HAL_NVIC_GetPriority:00000000 HAL_NVIC_GetPriority
/tmp/ccB9Q52u.s:1056 .text.HAL_NVIC_SetPendingIRQ:00000000 $t
/tmp/ccB9Q52u.s:1062 .text.HAL_NVIC_SetPendingIRQ:00000000 HAL_NVIC_SetPendingIRQ
/tmp/ccB9Q52u.s:1104 .text.HAL_NVIC_SetPendingIRQ:00000018 $d
ARM GAS /tmp/ccB9Q52u.s page 97
/tmp/ccjFay11.s:20 .text.__NVIC_DisableIRQ:00000000 $t
/tmp/ccjFay11.s:25 .text.__NVIC_DisableIRQ:00000000 __NVIC_DisableIRQ
/tmp/ccjFay11.s:87 .text.__NVIC_DisableIRQ:00000020 $d
/tmp/ccjFay11.s:92 .text.__NVIC_SetPriority:00000000 $t
/tmp/ccjFay11.s:97 .text.__NVIC_SetPriority:00000000 __NVIC_SetPriority
/tmp/ccjFay11.s:139 .text.__NVIC_SetPriority:0000001c $d
/tmp/ccjFay11.s:145 .text.__NVIC_GetPriority:00000000 $t
/tmp/ccjFay11.s:150 .text.__NVIC_GetPriority:00000000 __NVIC_GetPriority
/tmp/ccjFay11.s:185 .text.__NVIC_GetPriority:00000018 $d
/tmp/ccjFay11.s:191 .text.NVIC_EncodePriority:00000000 $t
/tmp/ccjFay11.s:196 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority
/tmp/ccjFay11.s:258 .text.NVIC_DecodePriority:00000000 $t
/tmp/ccjFay11.s:263 .text.NVIC_DecodePriority:00000000 NVIC_DecodePriority
/tmp/ccjFay11.s:332 .text.__NVIC_SystemReset:00000000 $t
/tmp/ccjFay11.s:337 .text.__NVIC_SystemReset:00000000 __NVIC_SystemReset
/tmp/ccjFay11.s:398 .text.__NVIC_SystemReset:0000001c $d
/tmp/ccjFay11.s:404 .text.HAL_NVIC_SetPriorityGrouping:00000000 $t
/tmp/ccjFay11.s:410 .text.HAL_NVIC_SetPriorityGrouping:00000000 HAL_NVIC_SetPriorityGrouping
/tmp/ccjFay11.s:464 .text.HAL_NVIC_SetPriorityGrouping:0000001c $d
/tmp/ccjFay11.s:470 .text.HAL_NVIC_SetPriority:00000000 $t
/tmp/ccjFay11.s:476 .text.HAL_NVIC_SetPriority:00000000 HAL_NVIC_SetPriority
/tmp/ccjFay11.s:526 .text.HAL_NVIC_SetPriority:0000001c $d
/tmp/ccjFay11.s:531 .text.HAL_NVIC_EnableIRQ:00000000 $t
/tmp/ccjFay11.s:537 .text.HAL_NVIC_EnableIRQ:00000000 HAL_NVIC_EnableIRQ
/tmp/ccjFay11.s:578 .text.HAL_NVIC_EnableIRQ:00000018 $d
/tmp/ccjFay11.s:583 .text.HAL_NVIC_DisableIRQ:00000000 $t
/tmp/ccjFay11.s:589 .text.HAL_NVIC_DisableIRQ:00000000 HAL_NVIC_DisableIRQ
/tmp/ccjFay11.s:612 .text.HAL_NVIC_SystemReset:00000000 $t
/tmp/ccjFay11.s:618 .text.HAL_NVIC_SystemReset:00000000 HAL_NVIC_SystemReset
/tmp/ccjFay11.s:637 .text.HAL_SYSTICK_Config:00000000 $t
/tmp/ccjFay11.s:643 .text.HAL_SYSTICK_Config:00000000 HAL_SYSTICK_Config
/tmp/ccjFay11.s:708 .text.HAL_SYSTICK_Config:00000024 $d
/tmp/ccjFay11.s:713 .text.HAL_MPU_Disable:00000000 $t
/tmp/ccjFay11.s:719 .text.HAL_MPU_Disable:00000000 HAL_MPU_Disable
/tmp/ccjFay11.s:756 .text.HAL_MPU_Disable:00000018 $d
/tmp/ccjFay11.s:761 .text.HAL_MPU_Enable:00000000 $t
/tmp/ccjFay11.s:767 .text.HAL_MPU_Enable:00000000 HAL_MPU_Enable
/tmp/ccjFay11.s:821 .text.HAL_MPU_Enable:0000001c $d
/tmp/ccjFay11.s:826 .text.HAL_MPU_EnableRegion:00000000 $t
/tmp/ccjFay11.s:832 .text.HAL_MPU_EnableRegion:00000000 HAL_MPU_EnableRegion
/tmp/ccjFay11.s:854 .text.HAL_MPU_EnableRegion:00000014 $d
/tmp/ccjFay11.s:859 .text.HAL_MPU_DisableRegion:00000000 $t
/tmp/ccjFay11.s:865 .text.HAL_MPU_DisableRegion:00000000 HAL_MPU_DisableRegion
/tmp/ccjFay11.s:887 .text.HAL_MPU_DisableRegion:00000014 $d
/tmp/ccjFay11.s:892 .text.HAL_MPU_ConfigRegion:00000000 $t
/tmp/ccjFay11.s:898 .text.HAL_MPU_ConfigRegion:00000000 HAL_MPU_ConfigRegion
/tmp/ccjFay11.s:975 .text.HAL_MPU_ConfigRegion:00000054 $d
/tmp/ccjFay11.s:980 .text.HAL_NVIC_GetPriorityGrouping:00000000 $t
/tmp/ccjFay11.s:986 .text.HAL_NVIC_GetPriorityGrouping:00000000 HAL_NVIC_GetPriorityGrouping
/tmp/ccjFay11.s:1010 .text.HAL_NVIC_GetPriorityGrouping:0000000c $d
/tmp/ccjFay11.s:1015 .text.HAL_NVIC_GetPriority:00000000 $t
/tmp/ccjFay11.s:1021 .text.HAL_NVIC_GetPriority:00000000 HAL_NVIC_GetPriority
/tmp/ccjFay11.s:1056 .text.HAL_NVIC_SetPendingIRQ:00000000 $t
/tmp/ccjFay11.s:1062 .text.HAL_NVIC_SetPendingIRQ:00000000 HAL_NVIC_SetPendingIRQ
/tmp/ccjFay11.s:1104 .text.HAL_NVIC_SetPendingIRQ:00000018 $d
ARM GAS /tmp/ccjFay11.s page 97
/tmp/ccB9Q52u.s:1109 .text.HAL_NVIC_GetPendingIRQ:00000000 $t
/tmp/ccB9Q52u.s:1115 .text.HAL_NVIC_GetPendingIRQ:00000000 HAL_NVIC_GetPendingIRQ
/tmp/ccB9Q52u.s:1161 .text.HAL_NVIC_GetPendingIRQ:00000020 $d
/tmp/ccB9Q52u.s:1166 .text.HAL_NVIC_ClearPendingIRQ:00000000 $t
/tmp/ccB9Q52u.s:1172 .text.HAL_NVIC_ClearPendingIRQ:00000000 HAL_NVIC_ClearPendingIRQ
/tmp/ccB9Q52u.s:1214 .text.HAL_NVIC_ClearPendingIRQ:00000018 $d
/tmp/ccB9Q52u.s:1219 .text.HAL_NVIC_GetActive:00000000 $t
/tmp/ccB9Q52u.s:1225 .text.HAL_NVIC_GetActive:00000000 HAL_NVIC_GetActive
/tmp/ccB9Q52u.s:1271 .text.HAL_NVIC_GetActive:00000020 $d
/tmp/ccB9Q52u.s:1276 .text.HAL_SYSTICK_CLKSourceConfig:00000000 $t
/tmp/ccB9Q52u.s:1282 .text.HAL_SYSTICK_CLKSourceConfig:00000000 HAL_SYSTICK_CLKSourceConfig
/tmp/ccB9Q52u.s:1317 .text.HAL_SYSTICK_Callback:00000000 $t
/tmp/ccB9Q52u.s:1323 .text.HAL_SYSTICK_Callback:00000000 HAL_SYSTICK_Callback
/tmp/ccB9Q52u.s:1336 .text.HAL_SYSTICK_IRQHandler:00000000 $t
/tmp/ccB9Q52u.s:1342 .text.HAL_SYSTICK_IRQHandler:00000000 HAL_SYSTICK_IRQHandler
/tmp/ccjFay11.s:1109 .text.HAL_NVIC_GetPendingIRQ:00000000 $t
/tmp/ccjFay11.s:1115 .text.HAL_NVIC_GetPendingIRQ:00000000 HAL_NVIC_GetPendingIRQ
/tmp/ccjFay11.s:1161 .text.HAL_NVIC_GetPendingIRQ:00000020 $d
/tmp/ccjFay11.s:1166 .text.HAL_NVIC_ClearPendingIRQ:00000000 $t
/tmp/ccjFay11.s:1172 .text.HAL_NVIC_ClearPendingIRQ:00000000 HAL_NVIC_ClearPendingIRQ
/tmp/ccjFay11.s:1214 .text.HAL_NVIC_ClearPendingIRQ:00000018 $d
/tmp/ccjFay11.s:1219 .text.HAL_NVIC_GetActive:00000000 $t
/tmp/ccjFay11.s:1225 .text.HAL_NVIC_GetActive:00000000 HAL_NVIC_GetActive
/tmp/ccjFay11.s:1271 .text.HAL_NVIC_GetActive:00000020 $d
/tmp/ccjFay11.s:1276 .text.HAL_SYSTICK_CLKSourceConfig:00000000 $t
/tmp/ccjFay11.s:1282 .text.HAL_SYSTICK_CLKSourceConfig:00000000 HAL_SYSTICK_CLKSourceConfig
/tmp/ccjFay11.s:1317 .text.HAL_SYSTICK_Callback:00000000 $t
/tmp/ccjFay11.s:1323 .text.HAL_SYSTICK_Callback:00000000 HAL_SYSTICK_Callback
/tmp/ccjFay11.s:1336 .text.HAL_SYSTICK_IRQHandler:00000000 $t
/tmp/ccjFay11.s:1342 .text.HAL_SYSTICK_IRQHandler:00000000 HAL_SYSTICK_IRQHandler
NO UNDEFINED SYMBOLS