ChTheo/RadioPhotonic_PCB_software
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This commit is contained in:
Ayzen
2026-03-13 17:49:58 +03:00
parent db80907a0b
commit eafc328caa
89 changed files with 36315 additions and 34500 deletions
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339
Src/main.c
View File

@ -97,6 +97,10 @@
#define AD9102_FLAG_TRIANGLE 0x0002u
#define AD9102_FLAG_SRAM 0x0004u
#define AD9102_FLAG_SRAM_FMT 0x0008u
#define AD9102_WAVE_OPCODE_BEGIN 0x0001u
#define AD9102_WAVE_OPCODE_COMMIT 0x0002u
#define AD9102_WAVE_OPCODE_CANCEL 0x0003u
#define AD9102_WAVE_MAX_CHUNK_SAMPLES 12u
#define AD9833_FLAG_ENABLE 0x0001u
#define AD9833_FLAG_TRIANGLE 0x0002u
@ -177,6 +181,10 @@ static const uint16_t ad9102_example2_regval[AD9102_REG_COUNT] = {
0x0000u, 0x0000u, 0x0000u, 0x0000u, 0x0fa0u, 0x0000u, 0x3ff0u, 0x0100u,
0x0001u, 0x0001u
};
static uint8_t ad9102_wave_upload_active = 0u;
static uint16_t ad9102_wave_expected_samples = 0u;
static uint16_t ad9102_wave_written_samples = 0u;
@ -220,6 +228,14 @@ static void AD9102_WriteRegTable(const uint16_t *values, uint16_t count);
static uint16_t AD9102_Apply(uint8_t saw_type, uint8_t enable, uint8_t saw_step, uint8_t pat_base, uint16_t pat_period);
static uint16_t AD9102_ApplySram(uint8_t enable, uint16_t samples, uint8_t hold, uint8_t triangle, uint16_t amplitude);
static void AD9102_LoadSramRamp(uint16_t samples, uint8_t triangle, uint16_t amplitude);
static void AD9102_ResetWaveUploadState(void);
static void AD9102_StopOutput(void);
static void AD9102_StartOutput(void);
static void AD9102_ConfigureSramPlayback(uint16_t samples, uint8_t hold);
static uint8_t AD9102_BeginWaveUpload(uint16_t samples);
static uint8_t AD9102_WriteWaveUploadChunk(const uint16_t *samples, uint16_t chunk_count);
static uint16_t AD9102_CommitWaveUpload(uint8_t *ok);
static void AD9102_CancelWaveUpload(void);
static uint8_t AD9102_CheckFlags(uint16_t pat_status, uint8_t expect_run, uint8_t saw_type, uint8_t saw_step, uint8_t pat_base, uint16_t pat_period);
static uint8_t AD9102_CheckFlagsSram(uint16_t pat_status, uint8_t expect_run, uint16_t samples, uint8_t hold);
static void SPI2_SetMode(uint32_t polarity, uint32_t phase);
@ -377,14 +393,15 @@ int main(void)
}
UART_transmission_request = MESS_01;
break;
case DEFAULT_ENABLE://2 - Go to HALT
//Set current setup to default
task.current_param = task.min_param;
Stop_TIM10();
Init_params();
LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1
LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2
CPU_state = HALT;
case DEFAULT_ENABLE://2 - Go to HALT
//Set current setup to default
task.current_param = task.min_param;
Stop_TIM10();
Init_params();
AD9102_CancelWaveUpload();
LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1
LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2
CPU_state = HALT;
CPU_state_old = HALT;//Save main current cycle
UART_transmission_request = MESS_01;
break;
@ -649,9 +666,86 @@ int main(void)
UART_transmission_request = MESS_01;
CPU_state = CPU_state_old;
break;
case AD9102_WAVE_CTRL_CMD://14 - Control custom AD9102 SRAM upload
State_Data[1] = 0u;
if (CalculateChecksum(COMMAND, AD9102_WAVE_CTRL_WORDS - 1) == COMMAND[AD9102_WAVE_CTRL_WORDS - 1])
{
uint16_t opcode = COMMAND[0];
uint16_t param0 = COMMAND[1];
uint16_t param1 = COMMAND[2];
switch (opcode)
{
case AD9102_WAVE_OPCODE_BEGIN:
if ((param1 != 0u) || !AD9102_BeginWaveUpload(param0))
{
AD9102_CancelWaveUpload();
State_Data[0] |= AD9102_ERR;
}
break;
case AD9102_WAVE_OPCODE_COMMIT:
{
uint16_t samples = ad9102_wave_expected_samples;
uint8_t ok = 0u;
uint16_t pat_status;
if ((param0 != 0u) || (param1 != 0u))
{
AD9102_CancelWaveUpload();
State_Data[0] |= AD9102_ERR;
break;
}
pat_status = AD9102_CommitWaveUpload(&ok);
State_Data[1] = (uint8_t)(pat_status & 0x00FFu);
if ((!ok) || AD9102_CheckFlagsSram(pat_status, 1u, samples, AD9102_SRAM_HOLD_DEFAULT))
{
State_Data[0] |= AD9102_ERR;
}
}
break;
case AD9102_WAVE_OPCODE_CANCEL:
if ((param0 != 0u) || (param1 != 0u))
{
State_Data[0] |= AD9102_ERR;
}
AD9102_CancelWaveUpload();
break;
default:
AD9102_CancelWaveUpload();
State_Data[0] |= AD9102_ERR;
break;
}
}
else
{
State_Data[0] |= UART_DECODE_ERR;
}
UART_transmission_request = MESS_01;
CPU_state = CPU_state_old;
break;
case AD9102_WAVE_DATA_CMD://15 - Write custom AD9102 SRAM samples
State_Data[1] = 0u;
if (CalculateChecksum(COMMAND, AD9102_WAVE_DATA_WORDS - 1) == COMMAND[AD9102_WAVE_DATA_WORDS - 1])
{
uint16_t chunk_count = COMMAND[0];
if (!AD9102_WriteWaveUploadChunk(&COMMAND[1], chunk_count))
{
AD9102_CancelWaveUpload();
State_Data[0] |= AD9102_ERR;
}
}
else
{
AD9102_CancelWaveUpload();
State_Data[0] |= UART_DECODE_ERR;
}
UART_transmission_request = MESS_01;
CPU_state = CPU_state_old;
break;
case DECODE_TASK:
if (CheckChecksum(COMMAND))
{
if (CheckChecksum(COMMAND))
{
Decode_task(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup);
TO6_before = TO6;
CPU_state = RUN_TASK;
@ -2852,8 +2946,176 @@ static void AD9102_WriteRegTable(const uint16_t *values, uint16_t count)
}
}
static void AD9102_ResetWaveUploadState(void)
{
ad9102_wave_upload_active = 0u;
ad9102_wave_expected_samples = 0u;
ad9102_wave_written_samples = 0u;
}
static void AD9102_StopOutput(void)
{
AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u);
HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET);
}
static void AD9102_StartOutput(void)
{
HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET);
AD9102_WriteReg(AD9102_REG_PAT_STATUS, AD9102_PAT_STATUS_RUN);
AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u);
for (volatile uint32_t d = 0; d < 1000; d++) {}
HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET);
}
static void AD9102_ConfigureSramPlayback(uint16_t samples, uint8_t hold)
{
uint16_t pat_timebase;
uint32_t pat_period;
if (samples < 2u)
{
samples = 2u;
}
if (samples > AD9102_SRAM_MAX_SAMPLES)
{
samples = AD9102_SRAM_MAX_SAMPLES;
}
if (hold == 0u)
{
hold = AD9102_SRAM_HOLD_DEFAULT;
}
if (hold > 0x0Fu)
{
hold = 0x0Fu;
}
pat_timebase = (uint16_t)(((uint16_t)(hold & 0x0Fu) << 8) |
((AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT & 0x0Fu) << 4) |
(AD9102_SRAM_START_DELAY_BASE_DEFAULT & 0x0Fu));
pat_period = (uint32_t)samples * (uint32_t)(hold & 0x0Fu);
if (pat_period == 0u)
{
pat_period = samples;
}
if (pat_period > 0xFFFFu)
{
pat_period = 0xFFFFu;
}
AD9102_WriteRegTable(ad9102_example2_regval, AD9102_REG_COUNT);
AD9102_StopOutput();
AD9102_WriteReg(AD9102_REG_WAV_CONFIG, AD9102_EX2_WAV_CONFIG);
AD9102_WriteReg(AD9102_REG_SAW_CONFIG, AD9102_EX2_SAW_CONFIG);
AD9102_WriteReg(AD9102_REG_DAC_PAT, AD9102_EX2_DAC_PAT);
AD9102_WriteReg(AD9102_REG_PAT_TIMEBASE, pat_timebase);
AD9102_WriteReg(AD9102_REG_PAT_PERIOD, (uint16_t)pat_period);
AD9102_WriteReg(AD9102_REG_PAT_TYPE, 0x0000u); // continuous pattern repeat
AD9102_WriteReg(AD9102_REG_START_DLY, AD9102_SRAM_START_DLY_DEFAULT);
AD9102_WriteReg(AD9102_REG_START_ADDR, 0x0000u);
AD9102_WriteReg(AD9102_REG_STOP_ADDR, (uint16_t)((samples - 1u) << 4));
AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u);
}
static uint8_t AD9102_BeginWaveUpload(uint16_t samples)
{
if ((samples < 2u) || (samples > AD9102_SRAM_MAX_SAMPLES))
{
return 0u;
}
AD9102_StopOutput();
AD9102_ResetWaveUploadState();
AD9102_ConfigureSramPlayback(samples, AD9102_SRAM_HOLD_DEFAULT);
AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0004u); // enable SRAM access
ad9102_wave_expected_samples = samples;
ad9102_wave_written_samples = 0u;
ad9102_wave_upload_active = 1u;
return 1u;
}
static uint8_t AD9102_WriteWaveUploadChunk(const uint16_t *samples, uint16_t chunk_count)
{
if (ad9102_wave_upload_active == 0u)
{
return 0u;
}
if ((chunk_count == 0u) || (chunk_count > AD9102_WAVE_MAX_CHUNK_SAMPLES))
{
return 0u;
}
if (((uint32_t)ad9102_wave_written_samples + (uint32_t)chunk_count) > (uint32_t)ad9102_wave_expected_samples)
{
return 0u;
}
for (uint16_t i = 0; i < chunk_count; i++)
{
int16_t sample = (int16_t)samples[i];
uint16_t sample_u14;
uint16_t word;
if ((sample < AD9102_SRAM_RAMP_MIN) || (sample > AD9102_SRAM_RAMP_MAX))
{
return 0u;
}
sample_u14 = ((uint16_t)sample) & 0x3FFFu;
word = (uint16_t)(sample_u14 << 2);
AD9102_WriteReg((uint16_t)(AD9102_REG_SRAM_DATA_BASE + ad9102_wave_written_samples + i), word);
}
ad9102_wave_written_samples = (uint16_t)(ad9102_wave_written_samples + chunk_count);
return 1u;
}
static uint16_t AD9102_CommitWaveUpload(uint8_t *ok)
{
uint16_t pat_status;
if (ok != NULL)
{
*ok = 0u;
}
if ((ad9102_wave_upload_active == 0u) ||
(ad9102_wave_expected_samples < 2u) ||
(ad9102_wave_written_samples != ad9102_wave_expected_samples))
{
AD9102_CancelWaveUpload();
return AD9102_ReadReg(AD9102_REG_PAT_STATUS);
}
AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u); // disable SRAM access
AD9102_WriteReg(AD9102_REG_START_ADDR, 0x0000u);
AD9102_WriteReg(AD9102_REG_STOP_ADDR, (uint16_t)((ad9102_wave_expected_samples - 1u) << 4));
AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u);
AD9102_StartOutput();
pat_status = AD9102_ReadReg(AD9102_REG_PAT_STATUS);
AD9102_ResetWaveUploadState();
if (ok != NULL)
{
*ok = 1u;
}
return pat_status;
}
static void AD9102_CancelWaveUpload(void)
{
if (ad9102_wave_upload_active != 0u)
{
AD9102_StopOutput();
}
AD9102_ResetWaveUploadState();
}
static uint16_t AD9102_Apply(uint8_t saw_type, uint8_t enable, uint8_t saw_step, uint8_t pat_base, uint16_t pat_period)
{
AD9102_ResetWaveUploadState();
if (enable)
{
uint16_t saw_cfg;
@ -2879,18 +3141,11 @@ static uint16_t AD9102_Apply(uint8_t saw_type, uint8_t enable, uint8_t saw_step,
AD9102_WriteReg(AD9102_REG_PAT_PERIOD, pat_period);
AD9102_WriteReg(AD9102_REG_PAT_TYPE, 0x0000u); // continuous pattern repeat
// Update RUN then RAMUPDATE at the end of the write sequence.
// AD9102 output is started by a falling edge of TRIGGER pin when RUN=1.
HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET);
AD9102_WriteReg(AD9102_REG_PAT_STATUS, AD9102_PAT_STATUS_RUN);
AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u);
for (volatile uint32_t d = 0; d < 1000; d++) {}
HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET);
AD9102_StartOutput();
}
else
{
AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u);
HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET);
AD9102_StopOutput();
}
return AD9102_ReadReg(AD9102_REG_PAT_STATUS);
@ -2966,13 +3221,13 @@ static void AD9102_LoadSramRamp(uint16_t samples, uint8_t triangle, uint16_t amp
}
}
if (value < -8192)
if (value < AD9102_SRAM_RAMP_MIN)
{
value = -8192;
value = AD9102_SRAM_RAMP_MIN;
}
else if (value > 8191)
else if (value > AD9102_SRAM_RAMP_MAX)
{
value = 8191;
value = AD9102_SRAM_RAMP_MAX;
}
uint16_t sample_u14 = (uint16_t)((int16_t)value) & 0x3FFFu;
@ -2986,6 +3241,8 @@ static void AD9102_LoadSramRamp(uint16_t samples, uint8_t triangle, uint16_t amp
static uint16_t AD9102_ApplySram(uint8_t enable, uint16_t samples, uint8_t hold, uint8_t triangle, uint16_t amplitude)
{
AD9102_ResetWaveUploadState();
if (samples == 0u)
{
samples = AD9102_SRAM_SAMPLES_DEFAULT;
@ -3012,46 +3269,16 @@ static uint16_t AD9102_ApplySram(uint8_t enable, uint16_t samples, uint8_t hold,
amplitude = AD9102_SRAM_AMP_DEFAULT;
}
uint16_t pat_timebase = (uint16_t)(((uint16_t)(hold & 0x0Fu) << 8) |
((AD9102_SRAM_PAT_PERIOD_BASE_DEFAULT & 0x0Fu) << 4) |
(AD9102_SRAM_START_DELAY_BASE_DEFAULT & 0x0Fu));
uint32_t pat_period = (uint32_t)samples * (uint32_t)(hold & 0x0Fu);
if (pat_period == 0u)
{
pat_period = samples;
}
if (pat_period > 0xFFFFu)
{
pat_period = 0xFFFFu;
}
AD9102_WriteRegTable(ad9102_example2_regval, AD9102_REG_COUNT);
AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u);
AD9102_WriteReg(AD9102_REG_WAV_CONFIG, AD9102_EX2_WAV_CONFIG);
AD9102_WriteReg(AD9102_REG_SAW_CONFIG, AD9102_EX2_SAW_CONFIG);
AD9102_WriteReg(AD9102_REG_DAC_PAT, AD9102_EX2_DAC_PAT);
AD9102_WriteReg(AD9102_REG_PAT_TIMEBASE, pat_timebase);
AD9102_WriteReg(AD9102_REG_PAT_PERIOD, (uint16_t)pat_period);
AD9102_WriteReg(AD9102_REG_PAT_TYPE, 0x0000u); // continuous pattern repeat
AD9102_WriteReg(AD9102_REG_START_DLY, AD9102_SRAM_START_DLY_DEFAULT);
AD9102_WriteReg(AD9102_REG_START_ADDR, 0x0000u);
AD9102_WriteReg(AD9102_REG_STOP_ADDR, (uint16_t)((samples - 1u) << 4));
AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u);
AD9102_ConfigureSramPlayback(samples, hold);
AD9102_LoadSramRamp(samples, triangle, amplitude);
if (enable)
{
HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET);
AD9102_WriteReg(AD9102_REG_PAT_STATUS, AD9102_PAT_STATUS_RUN);
AD9102_WriteReg(AD9102_REG_RAMUPDATE, 0x0001u);
for (volatile uint32_t d = 0; d < 1000; d++) {}
HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_RESET);
AD9102_StartOutput();
}
else
{
AD9102_WriteReg(AD9102_REG_PAT_STATUS, 0x0000u);
HAL_GPIO_WritePin(AD9102_TRIG_GPIO_Port, AD9102_TRIG_Pin, GPIO_PIN_SET);
AD9102_StopOutput();
}
return AD9102_ReadReg(AD9102_REG_PAT_STATUS);

50
Src/stm32f7xx_it.c
View File

@ -490,6 +490,12 @@ void UART_RxCpltCallback(void)
case STM32_DAC_CMD_HEADER: // STM32 internal DAC command
UART_rec_incr = 2;//timeout flag is still setting!
break;
case AD9102_WAVE_CTRL_HEADER: // AD9102 custom waveform control command
UART_rec_incr = 2;//timeout flag is still setting!
break;
case AD9102_WAVE_DATA_HEADER: // AD9102 custom waveform data packet
UART_rec_incr = 2;//timeout flag is still setting!
break;
default: //error decoding header
UART_rec_incr = 0;
flg_tmt = 0;//Reset the timeout flag
@ -542,6 +548,16 @@ void UART_RxCpltCallback(void)
UART_rec_incr = 0;
flg_tmt = 0;//Reset the timeout flag
}
else if (UART_header == AD9102_WAVE_CTRL_HEADER)
{
if ((UART_rec_incr & 0x0001) > 0)
COMMAND[(UART_rec_incr >> 1) - 1] += ((uint16_t)(uart_buf)) << 8;
else
COMMAND[(UART_rec_incr >> 1) - 1] = (uint16_t)(uart_buf);
CPU_state = AD9102_WAVE_CTRL_CMD;
UART_rec_incr = 0;
flg_tmt = 0;//Reset the timeout flag
}
else
{
if ((UART_rec_incr&0x0001)>0)
@ -556,19 +572,29 @@ void UART_RxCpltCallback(void)
case (CL_8 - 1):
if (UART_header == 0x1111)
{
if ((UART_rec_incr & 0x0001) > 0)
COMMAND[(UART_rec_incr >> 1) - 1] += ((uint16_t)(uart_buf)) << 8;
else
if ((UART_rec_incr & 0x0001) > 0)
COMMAND[(UART_rec_incr >> 1) - 1] += ((uint16_t)(uart_buf)) << 8;
else
COMMAND[(UART_rec_incr >> 1) - 1] = (uint16_t)(uart_buf);
CPU_state = DECODE_ENABLE;
UART_rec_incr = 0;
flg_tmt = 0;//Reset the timeout flag
}
else
{
if ((UART_rec_incr&0x0001)>0)
COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
else
CPU_state = DECODE_ENABLE;
UART_rec_incr = 0;
flg_tmt = 0;//Reset the timeout flag
}
else if (UART_header == AD9102_WAVE_DATA_HEADER)
{
if ((UART_rec_incr & 0x0001) > 0)
COMMAND[(UART_rec_incr >> 1) - 1] += ((uint16_t)(uart_buf)) << 8;
else
COMMAND[(UART_rec_incr >> 1) - 1] = (uint16_t)(uart_buf);
CPU_state = AD9102_WAVE_DATA_CMD;
UART_rec_incr = 0;
flg_tmt = 0;//Reset the timeout flag
}
else
{
if ((UART_rec_incr&0x0001)>0)
COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8;
else
COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf);
UART_rec_incr++;
UART_transmission_request = NO_MESS;