35 lines
865 B
Makefile
35 lines
865 B
Makefile
# SPDX-License-Identifier: MIT
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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PWD := $(shell pwd)
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# Directory with axi_pkg.sv, axi_if.sv and axi4l_reg_map.sv.
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# Override it from command line if your tree is different:
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# make SIM=verilator RTL_DIR=/path/to/rtl_libs/axi
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RTL_DIR ?= $(PWD)/../../../axi
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TB_DIR ?= $(PWD)
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TOPLEVEL = tb_axi4l_reg_map
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MODULE = test_axi4l_reg_map
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export PYTHONPATH := $(TB_DIR):$(PYTHONPATH)
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VERILOG_SOURCES += $(RTL_DIR)/rtl/axi_pkg.sv
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VERILOG_SOURCES += $(RTL_DIR)/rtl/axi_if.sv
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VERILOG_SOURCES += $(RTL_DIR)/axi_reg/axi4l_reg_map.sv
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VERILOG_SOURCES += $(TB_DIR)/tb_axi4l_reg_map.sv
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COMPILE_ARGS += -I$(RTL_DIR)
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ifeq ($(SIM),verilator)
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EXTRA_ARGS += --trace
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EXTRA_ARGS += --trace-structs
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EXTRA_ARGS += --public-flat-rw
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EXTRA_ARGS += -Wno-fatal
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EXTRA_ARGS += --timing
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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