24 lines
653 B
Makefile
24 lines
653 B
Makefile
TOPLEVEL_LANG = verilog
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SIM ?= verilator
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PWD := $(shell pwd)
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RTL_DIR ?= $(PWD)/../../rtl
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TB_DIR ?= $(PWD)
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TOPLEVEL = tb_axis_loopback
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MODULE = test_axis_loopback
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VERILOG_SOURCES += $(RTL_DIR)/axis_if.sv
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VERILOG_SOURCES += $(RTL_DIR)/axis_flat_to_if.sv
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VERILOG_SOURCES += $(RTL_DIR)/axis_if_to_flat.sv
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VERILOG_SOURCES += $(RTL_DIR)/axis_desc_flat_to_if.sv
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VERILOG_SOURCES += $(RTL_DIR)/axis_desc_if_to_flat.sv
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VERILOG_SOURCES += $(TB_DIR)/axis_loopback.sv
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VERILOG_SOURCES += $(TB_DIR)/tb_axis_loopback.sv
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COMPILE_ARGS += -I$(RTL_DIR)
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EXTRA_ARGS += --trace
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EXTRA_ARGS += --trace-structs
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include $(shell cocotb-config --makefiles)/Makefile.sim
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