48 lines
1.2 KiB
Systemverilog
48 lines
1.2 KiB
Systemverilog
`define AXIS_TYPEDEF_ALL(__name, __data_t, __keep_t, __strb_t, __id_t, __dest_t, __user_t) \
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typedef struct packed { \
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__data_t data; \
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__keep_t keep; \
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__strb_t strb; \
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logic last; \
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__id_t id; \
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__dest_t dest; \
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__user_t user; \
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logic valid; \
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} __name``_chan_t; \
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typedef struct packed { \
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__name``_chan_t t; \
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} __name``_req_t; \
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typedef struct packed { \
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logic ready; \
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} __name``_resp_t;
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interface axis_if #(
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parameter int unsigned DATA_W = 64,
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parameter int unsigned KEEP_W = DATA_W / 8,
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parameter int unsigned ID_W = 8,
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parameter int unsigned DEST_W = 8,
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parameter int unsigned USER_W = 1
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)(
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input logic aclk,
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input logic aresetn
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);
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typedef logic [DATA_W-1:0] data_t;
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typedef logic [KEEP_W-1:0] keep_t;
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typedef logic [KEEP_W-1:0] strb_t;
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typedef logic [ID_W-1:0] id_t;
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typedef logic [DEST_W-1:0] dest_t;
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typedef logic [USER_W-1:0] user_t;
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`AXIS_TYPEDEF_ALL(axis, data_t, keep_t, strb_t, id_t, dest_t, user_t)
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axis_req_t req;
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axis_resp_t resp;
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modport master (input aclk, aresetn, output req, input resp);
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modport slave (input aclk, aresetn, input req, output resp);
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modport monitor (input aclk, aresetn, input req, input resp);
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endinterface : axis_if
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