69 lines
2.3 KiB
Systemverilog
69 lines
2.3 KiB
Systemverilog
package axi4l_reg_map_example_pkg;
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import axi4l_reg_map_pkg::*;
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localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 4;
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localparam int unsigned REG_CTRL = 0;
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localparam int unsigned REG_STATUS = 1;
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localparam int unsigned REG_CONFIG = 2;
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localparam int unsigned REG_VERSION = 3;
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localparam logic [15:0] REG_CTRL_ADDR = 16'h0000;
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localparam logic [15:0] REG_STATUS_ADDR = 16'h0004;
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localparam logic [15:0] REG_CONFIG_ADDR = 16'h0008;
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localparam logic [15:0] REG_VERSION_ADDR = 16'h000c;
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localparam int unsigned CTRL_START_BIT = 0;
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localparam int unsigned CTRL_SOFT_RESET_BIT = 1;
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localparam int unsigned CTRL_ENABLE_BIT = 2;
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localparam int unsigned CTRL_IRQ_ENABLE_BIT = 3;
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localparam int unsigned STATUS_BUSY_BIT = 0;
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localparam int unsigned STATUS_DONE_BIT = 1;
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localparam int unsigned STATUS_ERROR_BIT = 2;
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localparam int unsigned STATUS_ERROR_CODE_LSB = 8;
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localparam int unsigned STATUS_ERROR_CODE_MSB = 15;
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localparam logic [31:0] CONFIG_RST = 32'h0000_0001;
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localparam logic [31:0] VERSION_VAL = 32'h0001_0000;
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localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{
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REG_CTRL: '{
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CTRL_START_BIT : REG_BIT_W1S,
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CTRL_SOFT_RESET_BIT : REG_BIT_W1S,
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CTRL_ENABLE_BIT : REG_BIT_RW,
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CTRL_IRQ_ENABLE_BIT : REG_BIT_RW,
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default : REG_BIT_RSVD
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},
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REG_STATUS: '{
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STATUS_BUSY_BIT : REG_BIT_RO,
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STATUS_DONE_BIT : REG_BIT_RO,
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STATUS_ERROR_BIT : REG_BIT_RO,
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STATUS_ERROR_CODE_LSB : REG_BIT_RO,
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STATUS_ERROR_CODE_LSB+1 : REG_BIT_RO,
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STATUS_ERROR_CODE_LSB+2 : REG_BIT_RO,
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STATUS_ERROR_CODE_LSB+3 : REG_BIT_RO,
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STATUS_ERROR_CODE_LSB+4 : REG_BIT_RO,
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STATUS_ERROR_CODE_LSB+5 : REG_BIT_RO,
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STATUS_ERROR_CODE_LSB+6 : REG_BIT_RO,
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STATUS_ERROR_CODE_LSB+7 : REG_BIT_RO,
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default : REG_BIT_RSVD
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},
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REG_CONFIG: '{
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default: REG_BIT_RW
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},
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REG_VERSION: '{
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default: REG_BIT_RO
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}
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};
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localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0] AXI4L_REG_MAP_EXAMPLE_REG_RST = '{
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REG_CTRL : 32'h0000_0000,
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REG_STATUS : 32'h0000_0000,
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REG_CONFIG : CONFIG_RST,
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REG_VERSION : 32'h0000_0000
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};
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endpackage : axi4l_reg_map_example_pkg
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