385 lines
16 KiB
Systemverilog
385 lines
16 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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//
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// Thin SystemVerilog interface wrapper around alexforencich/verilog-axi axi_dma.v.
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//
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// Policy used here:
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// * AXI memory master is exposed as axi4_if.master.
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// * AXI-Stream read/write data paths are exposed as axis_if master/slave.
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// * Descriptor and status channels remain flat because they are DMA-specific
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// command/status streams, not generic AXI-Stream data interfaces.
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`default_nettype none
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module axi_dma_if_wrapper #(
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parameter int unsigned AXI_DATA_WIDTH = 32,
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parameter int unsigned AXI_ADDR_WIDTH = 16,
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parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
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parameter int unsigned AXI_ID_WIDTH = 8,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_MAX_BURST_LEN = 16,
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parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
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parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
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parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
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parameter int unsigned AXIS_LAST_ENABLE = 1,
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parameter int unsigned AXIS_ID_ENABLE = 1,
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parameter int unsigned AXIS_ID_WIDTH = 8,
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parameter int unsigned AXIS_DEST_ENABLE = 0,
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parameter int unsigned AXIS_DEST_WIDTH = 8,
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parameter int unsigned AXIS_USER_ENABLE = 1,
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parameter int unsigned AXIS_USER_WIDTH = 1,
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parameter int unsigned LEN_WIDTH = 20,
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parameter int unsigned TAG_WIDTH = 8,
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parameter int unsigned ENABLE_SG = 0,
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parameter int unsigned ENABLE_UNALIGNED = 0
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)(
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input logic clk,
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input logic rst,
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/*
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* AXI read descriptor input, kept flat intentionally.
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*/
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input logic [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_addr,
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input logic [LEN_WIDTH-1:0] s_axis_read_desc_len,
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input logic [TAG_WIDTH-1:0] s_axis_read_desc_tag,
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input logic [AXIS_ID_WIDTH-1:0] s_axis_read_desc_id,
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input logic [AXIS_DEST_WIDTH-1:0] s_axis_read_desc_dest,
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input logic [AXIS_USER_WIDTH-1:0] s_axis_read_desc_user,
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input logic s_axis_read_desc_valid,
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output logic s_axis_read_desc_ready,
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/*
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* AXI read descriptor status output, kept flat intentionally.
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*/
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output logic [TAG_WIDTH-1:0] m_axis_read_desc_status_tag,
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output logic [3:0] m_axis_read_desc_status_error,
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output logic m_axis_read_desc_status_valid,
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/*
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* AXI stream read data output.
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*/
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axis_if.master m_axis_read_data,
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/*
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* AXI write descriptor input, kept flat intentionally.
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*/
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input logic [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_addr,
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input logic [LEN_WIDTH-1:0] s_axis_write_desc_len,
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input logic [TAG_WIDTH-1:0] s_axis_write_desc_tag,
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input logic s_axis_write_desc_valid,
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output logic s_axis_write_desc_ready,
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/*
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* AXI write descriptor status output, kept flat intentionally.
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*/
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output logic [LEN_WIDTH-1:0] m_axis_write_desc_status_len,
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output logic [TAG_WIDTH-1:0] m_axis_write_desc_status_tag,
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output logic [AXIS_ID_WIDTH-1:0] m_axis_write_desc_status_id,
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output logic [AXIS_DEST_WIDTH-1:0] m_axis_write_desc_status_dest,
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output logic [AXIS_USER_WIDTH-1:0] m_axis_write_desc_status_user,
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output logic [3:0] m_axis_write_desc_status_error,
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output logic m_axis_write_desc_status_valid,
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/*
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* AXI stream write data input.
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*/
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axis_if.slave s_axis_write_data,
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/*
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* AXI memory master interface.
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*/
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axi4_if.master m_axi,
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/*
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* Configuration.
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*/
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input logic read_enable,
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input logic write_enable,
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input logic write_abort
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);
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// --------------------------------------------------------------------------
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// Flat wires connected to original alexforencich axi_dma.v
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// --------------------------------------------------------------------------
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logic [AXIS_DATA_WIDTH-1:0] dma_m_axis_read_data_tdata;
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logic [AXIS_KEEP_WIDTH-1:0] dma_m_axis_read_data_tkeep;
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logic dma_m_axis_read_data_tvalid;
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logic dma_m_axis_read_data_tready;
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logic dma_m_axis_read_data_tlast;
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logic [AXIS_ID_WIDTH-1:0] dma_m_axis_read_data_tid;
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logic [AXIS_DEST_WIDTH-1:0] dma_m_axis_read_data_tdest;
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logic [AXIS_USER_WIDTH-1:0] dma_m_axis_read_data_tuser;
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logic [AXIS_DATA_WIDTH-1:0] dma_s_axis_write_data_tdata;
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logic [AXIS_KEEP_WIDTH-1:0] dma_s_axis_write_data_tkeep;
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logic [AXIS_KEEP_WIDTH-1:0] unused_s_axis_write_data_tstrb;
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logic dma_s_axis_write_data_tvalid;
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logic dma_s_axis_write_data_tready;
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logic dma_s_axis_write_data_tlast;
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logic [AXIS_ID_WIDTH-1:0] dma_s_axis_write_data_tid;
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logic [AXIS_DEST_WIDTH-1:0] dma_s_axis_write_data_tdest;
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logic [AXIS_USER_WIDTH-1:0] dma_s_axis_write_data_tuser;
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logic [AXI_ID_WIDTH-1:0] dma_m_axi_awid;
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logic [AXI_ADDR_WIDTH-1:0] dma_m_axi_awaddr;
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logic [7:0] dma_m_axi_awlen;
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logic [2:0] dma_m_axi_awsize;
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logic [1:0] dma_m_axi_awburst;
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logic dma_m_axi_awlock;
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logic [3:0] dma_m_axi_awcache;
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logic [2:0] dma_m_axi_awprot;
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logic dma_m_axi_awvalid;
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logic dma_m_axi_awready;
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logic [AXI_DATA_WIDTH-1:0] dma_m_axi_wdata;
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logic [AXI_STRB_WIDTH-1:0] dma_m_axi_wstrb;
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logic dma_m_axi_wlast;
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logic dma_m_axi_wvalid;
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logic dma_m_axi_wready;
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logic [AXI_ID_WIDTH-1:0] dma_m_axi_bid;
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logic [1:0] dma_m_axi_bresp;
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logic dma_m_axi_bvalid;
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logic dma_m_axi_bready;
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logic [AXI_ID_WIDTH-1:0] dma_m_axi_arid;
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logic [AXI_ADDR_WIDTH-1:0] dma_m_axi_araddr;
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logic [7:0] dma_m_axi_arlen;
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logic [2:0] dma_m_axi_arsize;
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logic [1:0] dma_m_axi_arburst;
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logic dma_m_axi_arlock;
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logic [3:0] dma_m_axi_arcache;
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logic [2:0] dma_m_axi_arprot;
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logic dma_m_axi_arvalid;
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logic dma_m_axi_arready;
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logic [AXI_ID_WIDTH-1:0] dma_m_axi_rid;
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logic [AXI_DATA_WIDTH-1:0] dma_m_axi_rdata;
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logic [1:0] dma_m_axi_rresp;
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logic dma_m_axi_rlast;
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logic dma_m_axi_rvalid;
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logic dma_m_axi_rready;
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logic [AXI_USER_WIDTH-1:0] unused_m_axi_buser;
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logic [AXI_USER_WIDTH-1:0] unused_m_axi_ruser;
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// Original DMA: flat ports only.
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axi_dma #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
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.AXI_STRB_WIDTH (AXI_STRB_WIDTH),
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.AXI_ID_WIDTH (AXI_ID_WIDTH),
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.AXI_MAX_BURST_LEN (AXI_MAX_BURST_LEN),
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.AXIS_DATA_WIDTH (AXIS_DATA_WIDTH),
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.AXIS_KEEP_ENABLE (AXIS_KEEP_ENABLE),
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.AXIS_KEEP_WIDTH (AXIS_KEEP_WIDTH),
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.AXIS_LAST_ENABLE (AXIS_LAST_ENABLE),
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.AXIS_ID_ENABLE (AXIS_ID_ENABLE),
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.AXIS_ID_WIDTH (AXIS_ID_WIDTH),
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.AXIS_DEST_ENABLE (AXIS_DEST_ENABLE),
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.AXIS_DEST_WIDTH (AXIS_DEST_WIDTH),
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.AXIS_USER_ENABLE (AXIS_USER_ENABLE),
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.AXIS_USER_WIDTH (AXIS_USER_WIDTH),
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.LEN_WIDTH (LEN_WIDTH),
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.TAG_WIDTH (TAG_WIDTH),
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.ENABLE_SG (ENABLE_SG),
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.ENABLE_UNALIGNED (ENABLE_UNALIGNED)
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) u_axi_dma (
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.clk (clk),
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.rst (rst),
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.s_axis_read_desc_addr (s_axis_read_desc_addr),
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.s_axis_read_desc_len (s_axis_read_desc_len),
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.s_axis_read_desc_tag (s_axis_read_desc_tag),
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.s_axis_read_desc_id (s_axis_read_desc_id),
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.s_axis_read_desc_dest (s_axis_read_desc_dest),
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.s_axis_read_desc_user (s_axis_read_desc_user),
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.s_axis_read_desc_valid (s_axis_read_desc_valid),
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.s_axis_read_desc_ready (s_axis_read_desc_ready),
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.m_axis_read_desc_status_tag (m_axis_read_desc_status_tag),
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.m_axis_read_desc_status_error (m_axis_read_desc_status_error),
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.m_axis_read_desc_status_valid (m_axis_read_desc_status_valid),
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.m_axis_read_data_tdata (dma_m_axis_read_data_tdata),
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.m_axis_read_data_tkeep (dma_m_axis_read_data_tkeep),
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.m_axis_read_data_tvalid (dma_m_axis_read_data_tvalid),
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.m_axis_read_data_tready (dma_m_axis_read_data_tready),
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.m_axis_read_data_tlast (dma_m_axis_read_data_tlast),
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.m_axis_read_data_tid (dma_m_axis_read_data_tid),
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.m_axis_read_data_tdest (dma_m_axis_read_data_tdest),
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.m_axis_read_data_tuser (dma_m_axis_read_data_tuser),
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.s_axis_write_desc_addr (s_axis_write_desc_addr),
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.s_axis_write_desc_len (s_axis_write_desc_len),
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.s_axis_write_desc_tag (s_axis_write_desc_tag),
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.s_axis_write_desc_valid (s_axis_write_desc_valid),
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.s_axis_write_desc_ready (s_axis_write_desc_ready),
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.m_axis_write_desc_status_len (m_axis_write_desc_status_len),
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.m_axis_write_desc_status_tag (m_axis_write_desc_status_tag),
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.m_axis_write_desc_status_id (m_axis_write_desc_status_id),
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.m_axis_write_desc_status_dest (m_axis_write_desc_status_dest),
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.m_axis_write_desc_status_user (m_axis_write_desc_status_user),
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.m_axis_write_desc_status_error (m_axis_write_desc_status_error),
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.m_axis_write_desc_status_valid (m_axis_write_desc_status_valid),
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.s_axis_write_data_tdata (dma_s_axis_write_data_tdata),
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.s_axis_write_data_tkeep (dma_s_axis_write_data_tkeep),
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.s_axis_write_data_tvalid (dma_s_axis_write_data_tvalid),
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.s_axis_write_data_tready (dma_s_axis_write_data_tready),
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.s_axis_write_data_tlast (dma_s_axis_write_data_tlast),
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.s_axis_write_data_tid (dma_s_axis_write_data_tid),
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.s_axis_write_data_tdest (dma_s_axis_write_data_tdest),
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.s_axis_write_data_tuser (dma_s_axis_write_data_tuser),
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.m_axi_awid (dma_m_axi_awid),
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.m_axi_awaddr (dma_m_axi_awaddr),
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.m_axi_awlen (dma_m_axi_awlen),
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.m_axi_awsize (dma_m_axi_awsize),
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.m_axi_awburst (dma_m_axi_awburst),
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.m_axi_awlock (dma_m_axi_awlock),
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.m_axi_awcache (dma_m_axi_awcache),
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.m_axi_awprot (dma_m_axi_awprot),
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.m_axi_awvalid (dma_m_axi_awvalid),
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.m_axi_awready (dma_m_axi_awready),
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.m_axi_wdata (dma_m_axi_wdata),
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.m_axi_wstrb (dma_m_axi_wstrb),
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.m_axi_wlast (dma_m_axi_wlast),
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.m_axi_wvalid (dma_m_axi_wvalid),
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.m_axi_wready (dma_m_axi_wready),
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.m_axi_bid (dma_m_axi_bid),
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.m_axi_bresp (dma_m_axi_bresp),
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.m_axi_bvalid (dma_m_axi_bvalid),
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.m_axi_bready (dma_m_axi_bready),
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.m_axi_arid (dma_m_axi_arid),
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.m_axi_araddr (dma_m_axi_araddr),
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.m_axi_arlen (dma_m_axi_arlen),
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.m_axi_arsize (dma_m_axi_arsize),
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.m_axi_arburst (dma_m_axi_arburst),
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.m_axi_arlock (dma_m_axi_arlock),
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.m_axi_arcache (dma_m_axi_arcache),
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.m_axi_arprot (dma_m_axi_arprot),
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.m_axi_arvalid (dma_m_axi_arvalid),
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.m_axi_arready (dma_m_axi_arready),
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.m_axi_rid (dma_m_axi_rid),
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.m_axi_rdata (dma_m_axi_rdata),
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.m_axi_rresp (dma_m_axi_rresp),
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.m_axi_rlast (dma_m_axi_rlast),
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.m_axi_rvalid (dma_m_axi_rvalid),
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.m_axi_rready (dma_m_axi_rready),
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.read_enable (read_enable),
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.write_enable (write_enable),
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.write_abort (write_abort)
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);
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// DMA read data flat output -> local axis_if.master
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axis_flat_to_if #(
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.DATA_W (AXIS_DATA_WIDTH),
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.KEEP_W (AXIS_KEEP_WIDTH),
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.ID_W (AXIS_ID_WIDTH),
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.DEST_W (AXIS_DEST_WIDTH),
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.USER_W (AXIS_USER_WIDTH)
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) u_m_axis_read_data_flat_to_if (
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.s_axis_tdata (dma_m_axis_read_data_tdata),
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.s_axis_tkeep (dma_m_axis_read_data_tkeep),
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.s_axis_tstrb (dma_m_axis_read_data_tkeep), // axi_dma has no tstrb; mirror tkeep
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.s_axis_tlast (dma_m_axis_read_data_tlast),
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.s_axis_tid (dma_m_axis_read_data_tid),
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.s_axis_tdest (dma_m_axis_read_data_tdest),
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.s_axis_tuser (dma_m_axis_read_data_tuser),
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.s_axis_tvalid (dma_m_axis_read_data_tvalid),
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.s_axis_tready (dma_m_axis_read_data_tready),
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.m_axis (m_axis_read_data)
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);
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// local axis_if.slave -> DMA write data flat input
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axis_if_to_flat #(
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.DATA_W (AXIS_DATA_WIDTH),
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.KEEP_W (AXIS_KEEP_WIDTH),
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.ID_W (AXIS_ID_WIDTH),
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.DEST_W (AXIS_DEST_WIDTH),
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.USER_W (AXIS_USER_WIDTH)
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) u_s_axis_write_data_if_to_flat (
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.s_axis (s_axis_write_data),
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.m_axis_tdata (dma_s_axis_write_data_tdata),
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.m_axis_tkeep (dma_s_axis_write_data_tkeep),
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.m_axis_tstrb (unused_s_axis_write_data_tstrb),
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.m_axis_tlast (dma_s_axis_write_data_tlast),
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.m_axis_tid (dma_s_axis_write_data_tid),
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.m_axis_tdest (dma_s_axis_write_data_tdest),
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.m_axis_tuser (dma_s_axis_write_data_tuser),
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.m_axis_tvalid(dma_s_axis_write_data_tvalid),
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.m_axis_tready(dma_s_axis_write_data_tready)
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);
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// DMA AXI master flat output -> local axi4_if.master
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axi4_flat_to_if #(
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.ADDR_W (AXI_ADDR_WIDTH),
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.DATA_W (AXI_DATA_WIDTH),
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.ID_W (AXI_ID_WIDTH),
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.USER_W (AXI_USER_WIDTH)
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) u_m_axi_flat_to_if (
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.s_axi_awid (dma_m_axi_awid),
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.s_axi_awaddr (dma_m_axi_awaddr),
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.s_axi_awlen (dma_m_axi_awlen),
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.s_axi_awsize (dma_m_axi_awsize),
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.s_axi_awburst (dma_m_axi_awburst),
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.s_axi_awlock (dma_m_axi_awlock),
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.s_axi_awcache (dma_m_axi_awcache),
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.s_axi_awprot (dma_m_axi_awprot),
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.s_axi_awqos (4'd0),
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.s_axi_awregion (4'd0),
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.s_axi_awuser ({AXI_USER_WIDTH{1'b0}}),
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.s_axi_awvalid (dma_m_axi_awvalid),
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.s_axi_awready (dma_m_axi_awready),
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.s_axi_wdata (dma_m_axi_wdata),
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.s_axi_wstrb (dma_m_axi_wstrb),
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.s_axi_wlast (dma_m_axi_wlast),
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.s_axi_wuser ({AXI_USER_WIDTH{1'b0}}),
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.s_axi_wvalid (dma_m_axi_wvalid),
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.s_axi_wready (dma_m_axi_wready),
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.s_axi_bid (dma_m_axi_bid),
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.s_axi_bresp (dma_m_axi_bresp),
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.s_axi_buser (unused_m_axi_buser),
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.s_axi_bvalid (dma_m_axi_bvalid),
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.s_axi_bready (dma_m_axi_bready),
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.s_axi_arid (dma_m_axi_arid),
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.s_axi_araddr (dma_m_axi_araddr),
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.s_axi_arlen (dma_m_axi_arlen),
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.s_axi_arsize (dma_m_axi_arsize),
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.s_axi_arburst (dma_m_axi_arburst),
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.s_axi_arlock (dma_m_axi_arlock),
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.s_axi_arcache (dma_m_axi_arcache),
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.s_axi_arprot (dma_m_axi_arprot),
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.s_axi_arqos (4'd0),
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.s_axi_arregion (4'd0),
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.s_axi_aruser ({AXI_USER_WIDTH{1'b0}}),
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.s_axi_arvalid (dma_m_axi_arvalid),
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.s_axi_arready (dma_m_axi_arready),
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.s_axi_rid (dma_m_axi_rid),
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.s_axi_rdata (dma_m_axi_rdata),
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.s_axi_rresp (dma_m_axi_rresp),
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.s_axi_rlast (dma_m_axi_rlast),
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.s_axi_ruser (unused_m_axi_ruser),
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.s_axi_rvalid (dma_m_axi_rvalid),
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.s_axi_rready (dma_m_axi_rready),
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.m_axi (m_axi)
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);
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endmodule : axi_dma_if_wrapper
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`default_nettype wire
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