332 lines
13 KiB
Systemverilog
332 lines
13 KiB
Systemverilog
// AXIS compat wrapper above axi_dma_if_wrapper.
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//
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//
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// s_axis_desc_cmd = one-beat command stream carrying read + write desc
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// m_axis_desc_status = one-beat status stream carrying read + write status
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//
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// read_enable and write_enable select which descriptor is used
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`default_nettype none
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module axi_dma_axis_compat #(
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parameter int unsigned AXI_DATA_WIDTH = 32,
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parameter int unsigned AXI_ADDR_WIDTH = 16,
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parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
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parameter int unsigned AXI_ID_WIDTH = 8,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_MAX_BURST_LEN = 16,
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parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
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parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
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parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
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parameter int unsigned AXIS_LAST_ENABLE = 1,
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parameter int unsigned AXIS_ID_ENABLE = 1,
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parameter int unsigned AXIS_ID_WIDTH = 8,
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parameter int unsigned AXIS_DEST_ENABLE = 0,
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parameter int unsigned AXIS_DEST_WIDTH = 8,
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parameter int unsigned AXIS_USER_ENABLE = 1,
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parameter int unsigned AXIS_USER_WIDTH = 1,
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parameter int unsigned LEN_WIDTH = 20,
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parameter int unsigned TAG_WIDTH = 8,
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parameter int unsigned ENABLE_SG = 0,
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parameter int unsigned ENABLE_UNALIGNED = 0,
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// Raw packed command/status widths. rounded up to full bytes
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parameter int unsigned READ_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH,
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parameter int unsigned WRITE_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH,
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parameter int unsigned DESC_CMD_RAW_WIDTH = READ_DESC_WIDTH + WRITE_DESC_WIDTH,
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parameter int unsigned DESC_CMD_DATA_WIDTH = ((DESC_CMD_RAW_WIDTH + 7) / 8) * 8,
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parameter int unsigned DESC_CMD_KEEP_WIDTH = DESC_CMD_DATA_WIDTH / 8,
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parameter int unsigned READ_STATUS_WIDTH = TAG_WIDTH + 4,
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parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4,
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parameter int unsigned DESC_STATUS_RAW_WIDTH = READ_STATUS_WIDTH + WRITE_STATUS_WIDTH,
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parameter int unsigned DESC_STATUS_DATA_WIDTH = ((DESC_STATUS_RAW_WIDTH + 7) / 8) * 8,
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parameter int unsigned DESC_STATUS_KEEP_WIDTH = DESC_STATUS_DATA_WIDTH / 8,
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parameter int unsigned DESC_STATUS_USER_WIDTH = 2
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)(
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input logic clk,
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input logic rst,
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// Unified command stream. One beat carries both read and write descriptors.
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// Which parts are used is selected by read_enable/write_enable.
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axis_if.slave s_axis_desc_cmd,
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// Unified status stream. One beat can carry read status, write status, or both.
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// m_axis_desc_status.tuser[0] = read status valid in this beat
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// m_axis_desc_status.tuser[1] = write status valid in this beat
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axis_if.master m_axis_desc_status,
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// Original DMA data streams and AXI memory master, still exposed as normal
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// generic interfaces.
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axis_if.master m_axis_read_data,
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axis_if.slave s_axis_write_data,
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axi4_if.master m_axi,
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input logic read_enable,
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input logic write_enable,
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input logic write_abort
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);
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// --------------------------------------------------------------------------
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// packing layout
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// --------------------------------------------------------------------------
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// s_axis_desc_cmd.tdata:
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// [READ_DESC_*] read descriptor
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// [WRITE_DESC_*] write descriptor
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//
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// m_axis_desc_status.tdata:
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// [READ_STATUS_*] read descriptor status
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// [WRITE_STATUS_*] write descriptor status
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//
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// offsets are LSB-first. padding in upper bits (if required)
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localparam int unsigned RD_ADDR_LSB = 0;
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localparam int unsigned RD_LEN_LSB = RD_ADDR_LSB + AXI_ADDR_WIDTH;
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localparam int unsigned RD_TAG_LSB = RD_LEN_LSB + LEN_WIDTH;
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localparam int unsigned RD_ID_LSB = RD_TAG_LSB + TAG_WIDTH;
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localparam int unsigned RD_DEST_LSB = RD_ID_LSB + AXIS_ID_WIDTH;
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localparam int unsigned RD_USER_LSB = RD_DEST_LSB + AXIS_DEST_WIDTH;
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localparam int unsigned WR_BASE_LSB = READ_DESC_WIDTH;
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localparam int unsigned WR_ADDR_LSB = WR_BASE_LSB;
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localparam int unsigned WR_LEN_LSB = WR_ADDR_LSB + AXI_ADDR_WIDTH;
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localparam int unsigned WR_TAG_LSB = WR_LEN_LSB + LEN_WIDTH;
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localparam int unsigned RD_STS_TAG_LSB = 0;
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localparam int unsigned RD_STS_ERROR_LSB = RD_STS_TAG_LSB + TAG_WIDTH;
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localparam int unsigned WR_STS_BASE_LSB = READ_STATUS_WIDTH;
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localparam int unsigned WR_STS_LEN_LSB = WR_STS_BASE_LSB;
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localparam int unsigned WR_STS_TAG_LSB = WR_STS_LEN_LSB + LEN_WIDTH;
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localparam int unsigned WR_STS_ID_LSB = WR_STS_TAG_LSB + TAG_WIDTH;
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localparam int unsigned WR_STS_DEST_LSB = WR_STS_ID_LSB + AXIS_ID_WIDTH;
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localparam int unsigned WR_STS_USER_LSB = WR_STS_DEST_LSB + AXIS_DEST_WIDTH;
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localparam int unsigned WR_STS_ERROR_LSB = WR_STS_USER_LSB + AXIS_USER_WIDTH;
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wire rstn = ~rst;
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// --------------------------------------------------------------------------
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// Internal DMA-specific descriptor/status interfaces
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// --------------------------------------------------------------------------
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axi_dma_read_desc_if #(
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.ADDR_W (AXI_ADDR_WIDTH),
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.LEN_W (LEN_WIDTH),
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.TAG_W (TAG_WIDTH),
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.ID_W (AXIS_ID_WIDTH),
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.DEST_W (AXIS_DEST_WIDTH),
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.USER_W (AXIS_USER_WIDTH)
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) read_desc_if (
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.aclk (clk),
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.aresetn (rstn)
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);
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axi_dma_read_desc_status_if #(
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.TAG_W (TAG_WIDTH)
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) read_desc_status_if (
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.aclk (clk),
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.aresetn (rstn)
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);
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axi_dma_write_desc_if #(
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.ADDR_W (AXI_ADDR_WIDTH),
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.LEN_W (LEN_WIDTH),
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.TAG_W (TAG_WIDTH)
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) write_desc_if (
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.aclk (clk),
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.aresetn (rstn)
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);
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axi_dma_write_desc_status_if #(
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.LEN_W (LEN_WIDTH),
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.TAG_W (TAG_WIDTH),
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.ID_W (AXIS_ID_WIDTH),
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.DEST_W (AXIS_DEST_WIDTH),
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.USER_W (AXIS_USER_WIDTH)
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) write_desc_status_if (
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.aclk (clk),
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.aresetn (rstn)
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);
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// --------------------------------------------------------------------------
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// Command AXIS -> read/write descriptors
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// --------------------------------------------------------------------------
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wire cmd_valid = s_axis_desc_cmd.req.t.valid;
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wire cmd_ready = (!read_enable || read_desc_if.resp.ready) &&
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(!write_enable || write_desc_if.resp.ready);
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// Only assert a descriptor valid when the complete command can be accepted.
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// This prevents partial consumption when both read and write are enabled.
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assign read_desc_if.req.valid = cmd_valid && read_enable && (!write_enable || write_desc_if.resp.ready);
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assign write_desc_if.req.valid = cmd_valid && write_enable && (!read_enable || read_desc_if.resp.ready);
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assign s_axis_desc_cmd.resp.ready = cmd_ready;
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assign read_desc_if.req.addr = s_axis_desc_cmd.req.t.data[RD_ADDR_LSB +: AXI_ADDR_WIDTH];
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assign read_desc_if.req.len = s_axis_desc_cmd.req.t.data[RD_LEN_LSB +: LEN_WIDTH];
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assign read_desc_if.req.tag = s_axis_desc_cmd.req.t.data[RD_TAG_LSB +: TAG_WIDTH];
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assign read_desc_if.req.id = s_axis_desc_cmd.req.t.data[RD_ID_LSB +: AXIS_ID_WIDTH];
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assign read_desc_if.req.dest = s_axis_desc_cmd.req.t.data[RD_DEST_LSB +: AXIS_DEST_WIDTH];
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assign read_desc_if.req.user = s_axis_desc_cmd.req.t.data[RD_USER_LSB +: AXIS_USER_WIDTH];
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assign write_desc_if.req.addr = s_axis_desc_cmd.req.t.data[WR_ADDR_LSB +: AXI_ADDR_WIDTH];
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assign write_desc_if.req.len = s_axis_desc_cmd.req.t.data[WR_LEN_LSB +: LEN_WIDTH];
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assign write_desc_if.req.tag = s_axis_desc_cmd.req.t.data[WR_TAG_LSB +: TAG_WIDTH];
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// --------------------------------------------------------------------------
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// Lower DMA wrapper
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// --------------------------------------------------------------------------
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axi_dma_if_wrapper #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
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.AXI_STRB_WIDTH (AXI_STRB_WIDTH),
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.AXI_ID_WIDTH (AXI_ID_WIDTH),
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.AXI_USER_WIDTH (AXI_USER_WIDTH),
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.AXI_MAX_BURST_LEN (AXI_MAX_BURST_LEN),
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.AXIS_DATA_WIDTH (AXIS_DATA_WIDTH),
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.AXIS_KEEP_ENABLE (AXIS_KEEP_ENABLE),
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.AXIS_KEEP_WIDTH (AXIS_KEEP_WIDTH),
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.AXIS_LAST_ENABLE (AXIS_LAST_ENABLE),
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.AXIS_ID_ENABLE (AXIS_ID_ENABLE),
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.AXIS_ID_WIDTH (AXIS_ID_WIDTH),
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.AXIS_DEST_ENABLE (AXIS_DEST_ENABLE),
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.AXIS_DEST_WIDTH (AXIS_DEST_WIDTH),
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.AXIS_USER_ENABLE (AXIS_USER_ENABLE),
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.AXIS_USER_WIDTH (AXIS_USER_WIDTH),
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.LEN_WIDTH (LEN_WIDTH),
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.TAG_WIDTH (TAG_WIDTH),
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.ENABLE_SG (ENABLE_SG),
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.ENABLE_UNALIGNED (ENABLE_UNALIGNED)
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) u_axi_dma_if_wrapper (
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.clk (clk),
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.rst (rst),
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.s_axis_read_desc (read_desc_if),
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.m_axis_read_desc_status (read_desc_status_if),
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.m_axis_read_data (m_axis_read_data),
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.s_axis_write_desc (write_desc_if),
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.m_axis_write_desc_status (write_desc_status_if),
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.s_axis_write_data (s_axis_write_data),
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.m_axi (m_axi),
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.read_enable (read_enable),
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.write_enable (write_enable),
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.write_abort (write_abort)
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);
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// --------------------------------------------------------------------------
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// Status capture and unified AXIS output
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// --------------------------------------------------------------------------
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// Forencich descriptor status channels have valid but no ready. A regular
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// AXI-Stream output can be stalled
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// this wrapper stores one pending read status and one pending write status.
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// if you need more, please attack a fifo
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logic rd_status_pending;
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logic [TAG_WIDTH-1:0] rd_status_tag_q;
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logic [3:0] rd_status_error_q;
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logic wr_status_pending;
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logic [LEN_WIDTH-1:0] wr_status_len_q;
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logic [TAG_WIDTH-1:0] wr_status_tag_q;
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logic [AXIS_ID_WIDTH-1:0] wr_status_id_q;
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logic [AXIS_DEST_WIDTH-1:0] wr_status_dest_q;
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logic [AXIS_USER_WIDTH-1:0] wr_status_user_q;
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logic [3:0] wr_status_error_q;
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wire status_valid = rd_status_pending || wr_status_pending;
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wire status_fire = status_valid && m_axis_desc_status.resp.ready;
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always_ff @(posedge clk) begin
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if (rst) begin
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rd_status_pending <= 1'b0;
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wr_status_pending <= 1'b0;
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rd_status_tag_q <= '0;
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rd_status_error_q <= '0;
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wr_status_len_q <= '0;
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wr_status_tag_q <= '0;
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wr_status_id_q <= '0;
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wr_status_dest_q <= '0;
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wr_status_user_q <= '0;
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wr_status_error_q <= '0;
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end else begin
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if (status_fire) begin
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rd_status_pending <= 1'b0;
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wr_status_pending <= 1'b0;
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end
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if (read_desc_status_if.req.valid) begin
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`ifndef SYNTHESIS
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if (rd_status_pending && !status_fire) begin
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$error("axi_dma_axis_compat: read status overflow; add a FIFO or do not backpressure status output");
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end
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`endif
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rd_status_pending <= 1'b1;
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rd_status_tag_q <= read_desc_status_if.req.tag;
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rd_status_error_q <= read_desc_status_if.req.error;
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end
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if (write_desc_status_if.req.valid) begin
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`ifndef SYNTHESIS
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if (wr_status_pending && !status_fire) begin
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$error("axi_dma_axis_compat: write status overflow; add a FIFO or do not backpressure status output");
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end
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`endif
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wr_status_pending <= 1'b1;
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wr_status_len_q <= write_desc_status_if.req.len;
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wr_status_tag_q <= write_desc_status_if.req.tag;
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wr_status_id_q <= write_desc_status_if.req.id;
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wr_status_dest_q <= write_desc_status_if.req.dest;
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wr_status_user_q <= write_desc_status_if.req.user;
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wr_status_error_q <= write_desc_status_if.req.error;
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end
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end
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end
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logic [DESC_STATUS_DATA_WIDTH-1:0] status_tdata;
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logic [DESC_STATUS_USER_WIDTH-1:0] status_tuser;
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always_comb begin
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status_tdata = '0;
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status_tuser = '0;
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if (rd_status_pending) begin
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status_tdata[RD_STS_TAG_LSB +: TAG_WIDTH] = rd_status_tag_q;
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status_tdata[RD_STS_ERROR_LSB +: 4] = rd_status_error_q;
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status_tuser[0] = 1'b1;
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end
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if (wr_status_pending) begin
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status_tdata[WR_STS_LEN_LSB +: LEN_WIDTH] = wr_status_len_q;
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status_tdata[WR_STS_TAG_LSB +: TAG_WIDTH] = wr_status_tag_q;
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status_tdata[WR_STS_ID_LSB +: AXIS_ID_WIDTH] = wr_status_id_q;
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status_tdata[WR_STS_DEST_LSB +: AXIS_DEST_WIDTH] = wr_status_dest_q;
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status_tdata[WR_STS_USER_LSB +: AXIS_USER_WIDTH] = wr_status_user_q;
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status_tdata[WR_STS_ERROR_LSB +: 4] = wr_status_error_q;
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status_tuser[1] = 1'b1;
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end
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end
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assign m_axis_desc_status.req.t.data = status_tdata;
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assign m_axis_desc_status.req.t.keep = {DESC_STATUS_KEEP_WIDTH{1'b1}};
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assign m_axis_desc_status.req.t.strb = {DESC_STATUS_KEEP_WIDTH{1'b1}};
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assign m_axis_desc_status.req.t.last = 1'b1;
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assign m_axis_desc_status.req.t.id = '0;
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assign m_axis_desc_status.req.t.dest = '0;
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assign m_axis_desc_status.req.t.user = status_tuser;
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assign m_axis_desc_status.req.t.valid = status_valid;
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endmodule : axi_dma_axis_compat
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`default_nettype wire
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