31 lines
1.0 KiB
Systemverilog
31 lines
1.0 KiB
Systemverilog
module axis_flat_to_if #(
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parameter int unsigned DATA_W = 64,
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parameter int unsigned KEEP_W = DATA_W / 8,
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parameter int unsigned ID_W = 8,
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parameter int unsigned DEST_W = 8,
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parameter int unsigned USER_W = 1
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)(
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input logic [DATA_W-1:0] s_axis_tdata,
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input logic [KEEP_W-1:0] s_axis_tkeep,
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input logic [KEEP_W-1:0] s_axis_tstrb,
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input logic s_axis_tlast,
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input logic [ID_W-1:0] s_axis_tid,
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input logic [DEST_W-1:0] s_axis_tdest,
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input logic [USER_W-1:0] s_axis_tuser,
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input logic s_axis_tvalid,
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output logic s_axis_tready,
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axis_if.master m_axis
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);
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assign m_axis.req.t.data = s_axis_tdata;
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assign m_axis.req.t.keep = s_axis_tkeep;
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assign m_axis.req.t.strb = s_axis_tstrb;
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assign m_axis.req.t.last = s_axis_tlast;
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assign m_axis.req.t.id = s_axis_tid;
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assign m_axis.req.t.dest = s_axis_tdest;
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assign m_axis.req.t.user = s_axis_tuser;
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assign m_axis.req.t.valid = s_axis_tvalid;
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assign s_axis_tready = m_axis.resp.ready;
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endmodule : axis_flat_to_if
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