68 lines
1.8 KiB
Systemverilog
68 lines
1.8 KiB
Systemverilog
module axi4l_reg_map_example #(
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parameter int unsigned ADDR_W = 16,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1
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)(
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input logic clk,
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input logic rst_n,
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axi4l_if.slave s_axil,
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output logic start_o,
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output logic soft_reset_o,
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output logic enable_o,
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output logic irq_enable_o,
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output logic [31:0] config_o,
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input logic busy_i,
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input logic done_i,
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input logic error_i,
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input logic [7:0] error_code_i
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);
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import axi4l_reg_map_example_pkg::*;
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localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS;
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logic [N_REGS-1:0][31:0] reg_i;
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logic [N_REGS-1:0][31:0] reg_o;
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logic [N_REGS-1:0][31:0] reg_pulse;
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axi4l_reg_map #(
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.ADDR_W (ADDR_W),
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.DATA_W (DATA_W),
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.USER_W (USER_W),
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.N_REGS (N_REGS),
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.REG_MODE (AXI4L_REG_MAP_EXAMPLE_REG_MODE),
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.REG_RST (AXI4L_REG_MAP_EXAMPLE_REG_RST)
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) u_reg_map (
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.clk (clk),
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.rst_n (rst_n),
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.s_axil (s_axil),
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.reg_i (reg_i),
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.reg_o (reg_o),
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.reg_pulse (reg_pulse)
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);
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always_comb begin
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reg_i = '0;
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// REG_STATUS @ 0x04
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reg_i[REG_STATUS][STATUS_BUSY_BIT] = busy_i;
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reg_i[REG_STATUS][STATUS_DONE_BIT] = done_i;
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reg_i[REG_STATUS][STATUS_ERROR_BIT] = error_i;
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reg_i[REG_STATUS][STATUS_ERROR_CODE_MSB:STATUS_ERROR_CODE_LSB] = error_code_i;
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// REG_VERSION @ 0x0c
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reg_i[REG_VERSION] = VERSION_VAL;
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end
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// REG_CTRL @ 0x00
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assign start_o = reg_pulse[REG_CTRL][CTRL_START_BIT];
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assign soft_reset_o = reg_pulse[REG_CTRL][CTRL_SOFT_RESET_BIT];
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assign enable_o = reg_o[REG_CTRL][CTRL_ENABLE_BIT];
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assign irq_enable_o = reg_o[REG_CTRL][CTRL_IRQ_ENABLE_BIT];
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// REG_CONFIG @ 0x08
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assign config_o = reg_o[REG_CONFIG];
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endmodule : axi4l_reg_map_example
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