165 lines
6.3 KiB
Systemverilog
165 lines
6.3 KiB
Systemverilog
module axil_cdc_wrapper #(
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parameter int ADDR_WIDTH = 32,
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parameter int DATA_WIDTH = 32
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)(
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input wire s_clk,
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input wire s_rst,
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axi4l_if.slave s_axi,
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input wire m_clk,
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input wire m_rst,
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axi4l_if.master m_axi
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);
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localparam int STRB_WIDTH = (DATA_WIDTH/8);
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wire [ADDR_WIDTH-1:0] cdc_s_axil_awaddr;
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wire [2:0] cdc_s_axil_awprot;
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wire cdc_s_axil_awvalid;
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wire cdc_s_axil_awready;
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wire [DATA_WIDTH-1:0] cdc_s_axil_wdata;
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wire [STRB_WIDTH-1:0] cdc_s_axil_wstrb;
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wire cdc_s_axil_wvalid;
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wire cdc_s_axil_wready;
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wire [1:0] cdc_s_axil_bresp;
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wire cdc_s_axil_bvalid;
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wire cdc_s_axil_bready;
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wire [ADDR_WIDTH-1:0] cdc_s_axil_araddr;
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wire [2:0] cdc_s_axil_arprot;
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wire cdc_s_axil_arvalid;
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wire cdc_s_axil_arready;
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wire [DATA_WIDTH-1:0] cdc_s_axil_rdata;
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wire [1:0] cdc_s_axil_rresp;
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wire cdc_s_axil_rvalid;
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wire cdc_s_axil_rready;
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wire [ADDR_WIDTH-1:0] cdc_m_axil_awaddr;
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wire [2:0] cdc_m_axil_awprot;
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wire cdc_m_axil_awvalid;
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wire cdc_m_axil_awready;
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wire [DATA_WIDTH-1:0] cdc_m_axil_wdata;
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wire [STRB_WIDTH-1:0] cdc_m_axil_wstrb;
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wire cdc_m_axil_wvalid;
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wire cdc_m_axil_wready;
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wire [1:0] cdc_m_axil_bresp;
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wire cdc_m_axil_bvalid;
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wire cdc_m_axil_bready;
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wire [ADDR_WIDTH-1:0] cdc_m_axil_araddr;
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wire [2:0] cdc_m_axil_arprot;
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wire cdc_m_axil_arvalid;
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wire cdc_m_axil_arready;
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wire [DATA_WIDTH-1:0] cdc_m_axil_rdata;
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wire [1:0] cdc_m_axil_rresp;
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wire cdc_m_axil_rvalid;
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wire cdc_m_axil_rready;
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axi4l_if_to_flat #(
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.ADDR_W (ADDR_WIDTH),
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.DATA_W (DATA_WIDTH)
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) i_axi4l_if_to_flat (
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.s_axil (s_axi),
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.m_axil_awaddr (cdc_m_axil_awaddr),
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.m_axil_awprot (cdc_m_axil_awprot),
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.m_axil_awuser (cdc_m_axil_awuser),
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.m_axil_awvalid (cdc_m_axil_awvalid),
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.m_axil_awready (cdc_m_axil_awready),
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.m_axil_wdata (cdc_m_axil_wdata),
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.m_axil_wstrb (cdc_m_axil_wstrb),
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.m_axil_wuser (cdc_m_axil_wuser),
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.m_axil_wvalid (cdc_m_axil_wvalid),
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.m_axil_wready (cdc_m_axil_wready),
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.m_axil_bresp (cdc_m_axil_bresp),
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.m_axil_buser (cdc_m_axil_buser),
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.m_axil_bvalid (cdc_m_axil_bvalid),
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.m_axil_bready (cdc_m_axil_bready),
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.m_axil_araddr (cdc_m_axil_araddr),
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.m_axil_arprot (cdc_m_axil_arprot),
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.m_axil_aruser (cdc_m_axil_aruser),
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.m_axil_arvalid (cdc_m_axil_arvalid),
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.m_axil_arready (cdc_m_axil_arready),
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.m_axil_rdata (cdc_m_axil_rdata),
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.m_axil_rresp (cdc_m_axil_rresp),
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.m_axil_ruser (cdc_m_axil_ruser),
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.m_axil_rvalid (cdc_m_axil_rvalid),
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.m_axil_rready (cdc_m_axil_rready)
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);
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axil_cdc #(
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.ADDR_WIDTH (ADDR_WIDTH),
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.DATA_WIDTH (DATA_WIDTH)
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) i_axil_cdc (
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.s_clk (s_clk),
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.s_rst (s_rst),
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.s_axil_awaddr (cdc_m_axil_awaddr),
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.s_axil_awprot (cdc_m_axil_awprot),
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.s_axil_awvalid (cdc_m_axil_awvalid),
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.s_axil_awready (cdc_m_axil_awready),
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.s_axil_wdata (cdc_m_axil_wdata),
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.s_axil_wstrb (cdc_m_axil_wstrb),
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.s_axil_wvalid (cdc_m_axil_wvalid),
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.s_axil_wready (cdc_m_axil_wready),
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.s_axil_bresp (cdc_m_axil_bresp),
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.s_axil_bvalid (cdc_m_axil_bvalid),
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.s_axil_bready (cdc_m_axil_bready),
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.s_axil_araddr (cdc_m_axil_araddr),
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.s_axil_arprot (cdc_m_axil_arprot),
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.s_axil_arvalid (cdc_m_axil_arvalid),
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.s_axil_arready (cdc_m_axil_arready),
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.s_axil_rdata (cdc_m_axil_rdata),
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.s_axil_rresp (cdc_m_axil_rresp),
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.s_axil_rvalid (cdc_m_axil_rvalid),
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.s_axil_rready (cdc_m_axil_rready),
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.m_clk (m_clk),
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.m_rst (m_rst),
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.m_axil_awaddr (cdc_s_axil_awaddr),
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.m_axil_awprot (cdc_s_axil_awprot),
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.m_axil_awvalid (cdc_s_axil_awvalid),
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.m_axil_awready (cdc_s_axil_awready),
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.m_axil_wdata (cdc_s_axil_wdata),
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.m_axil_wstrb (cdc_s_axil_wstrb),
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.m_axil_wvalid (cdc_s_axil_wvalid),
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.m_axil_wready (cdc_s_axil_wready),
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.m_axil_bresp (cdc_s_axil_bresp),
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.m_axil_bvalid (cdc_s_axil_bvalid),
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.m_axil_bready (cdc_s_axil_bready),
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.m_axil_araddr (cdc_s_axil_araddr),
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.m_axil_arprot (cdc_s_axil_arprot),
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.m_axil_arvalid (cdc_s_axil_arvalid),
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.m_axil_arready (cdc_s_axil_arready),
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.m_axil_rdata (cdc_s_axil_rdata),
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.m_axil_rresp (cdc_s_axil_rresp),
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.m_axil_rvalid (cdc_s_axil_rvalid),
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.m_axil_rready (cdc_s_axil_rready)
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);
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axi4l_flat_to_if #(
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.ADDR_W (ADDR_WIDTH),
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.DATA_W (DATA_WIDTH)
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) i_axi4l_flat_to_if (
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.s_axil_awaddr (cdc_s_axil_awaddr),
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.s_axil_awprot (cdc_s_axil_awprot),
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.s_axil_awuser (cdc_s_axil_awuser),
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.s_axil_awvalid (cdc_s_axil_awvalid),
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.s_axil_awready (cdc_s_axil_awready),
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.s_axil_wdata (cdc_s_axil_wdata),
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.s_axil_wstrb (cdc_s_axil_wstrb),
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.s_axil_wuser (cdc_s_axil_wuser),
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.s_axil_wvalid (cdc_s_axil_wvalid),
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.s_axil_wready (cdc_s_axil_wready),
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.s_axil_bresp (cdc_s_axil_bresp),
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.s_axil_buser (cdc_s_axil_buser),
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.s_axil_bvalid (cdc_s_axil_bvalid),
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.s_axil_bready (cdc_s_axil_bready),
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.s_axil_araddr (cdc_s_axil_araddr),
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.s_axil_arprot (cdc_s_axil_arprot),
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.s_axil_aruser (cdc_s_axil_aruser),
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.s_axil_arvalid (cdc_s_axil_arvalid),
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.s_axil_arready (cdc_s_axil_arready),
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.s_axil_rdata (cdc_s_axil_rdata),
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.s_axil_rresp (cdc_s_axil_rresp),
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.s_axil_ruser (cdc_s_axil_ruser),
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.s_axil_rvalid (cdc_s_axil_rvalid),
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.s_axil_rready (cdc_s_axil_rready),
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.m_axil (m_axil)
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);
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endmodule |